SU1233161A1 - Device for distributing tasks in computer system - Google Patents

Abstract

This invention relates to the field of computing. The purpose of the invention is to reduce the average time of service jobs in the computing system. The device contains a block for selecting the maximum number, registers, counters, triggers, decoders, AND elements, OR elements, comparison element, delay element, OR-NOT element, pulse generator. .New in the device is the use of the maximum number selection block, triggers, decoders, OR elements, pulse generator and OR NOT element, allowing it to be assigned to service by free processors in the first place tasks with maximum execution time, to ensure parallel task scheduling and correction information and control graph of connectivity between tasks. The device detects tasks that are independent in information control communications, selects tasks with the maximum execution duration from among them and assigns them to free processors, and after completing tasks in processors by the processors, the information control correlation graph between tasks is corrected. 2 Il. with S (L to with so about

Description

one

The invention relates to computing, in particular, devices for distributing tasks in computing systems.

The purpose of the invention is to reduce the time of service tasks in the computing system.

FIG. 1 shows a block diagram of the device; Fig. 2 is a block diagram for selecting the maximum number.

The proposed device contains a matrix 1 (size NN) of arc formers, the first element SH 2, block 3 for selecting the maximum number, triggers 4, the first group of elements OR 5, the first group of elements AND 6, the group of counters 7, counter 8, the group circuits 9 comparison, the first group of triggers 10, the second group of elements And 11, the first and second groups of registers 12 and 13, the third group of elements And 14, the second group of elements OR 15, the second group of triggers 16, the second element OR 17, element And 18, 19 pulse generator, the third group of elements OR 20, the fourth group of elements And 21 group of elements OR-NOT 22, group of decoders 23, fourth group of elements OR 24, third element OR 25, element YPI-NE 26, first and second elements 27 and 28 delays, group of blocks of bitwise analysis nodes 29, third, the fourth and fifth groups of elements And 30 - 32, the fifth and sixth groups of elements OR 33 and 34, the third group of triggers 35, the group of elements AND-NE 3, the seventh group of elements 1-1PI 37, the third group of registers 38, the third group of elements And 39, the first, second, third, fourth, and fifth groups of inputs 40–44, input 45, output 46, output group 47 va, a first group 48 of inputs, the first input 49, a second group of inputs 50, a second input 51 and output 52 group unit 3 selecting the maximum number.

The device works as follows.

In the initial state, triggers 4 and 10, counters 7 and 8 are cleared.

Initially, the triggers 4 of the matrix 1 of the formers of arcs along the inputs 40 enter information about the topology of the graph (the vertices of which correspond to the tasks, and the arcs to the information controlling links between them). At. This corresponding triggers 4 us1233161

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0

tantalized in a single state. The number of a trigger set to one is determined by the intersection of the row number; equal to the number of the initial vertex of the arc, and the column with the number equal to the number of its final vertex with

The corresponding register 13 is entered at input 42, the code of the task number and the initial ones for its execution. In J, and register 12 (j -1, N, where N is the number of tasks), at input 41, the time code of the jth ask. In general, task execution time codes differ from each other.

In the operation of the device there are three stages.

On. In the first stage, independent tasks are determined (planned; task processing). At the same time, the potentials of the OR 5 elements in the columns corresponding to the initial vertices of the information control 2 graph appear low potentials, since the initial vertices do not contain an input The arcs and triggers 4 in these columns are in the zero state, the start pulse at input 45 through the 0 stree element OR 2 is fed to the second BhodB of all elements 6 and 6 and the counting input of the counter 8. The start pulse sets to one state all triggers: 10. In this case, the start pulse does not pass through the AND 6 elements to the counters 7 of those columns of matrix 1, all the triggers 4 of which are in the zero state. In addition, the trigger pulse sets all the triggers 10 to one state. In the dynamics of the device’s operation, the j-th and the trigger is set to the zero state after assignment of the j -th

tasks on the processor.

Next, the contents of each counter 7 are fed to the first input of the corresponding comparison element 9, and from the other, the INPUT of this element is information from the counter 8. If the readings of the counters 7 and 8 do not match, the comparison element 9 generates a signal that goes to the second input of the corresponding element 11 At the output of the J-th element And 11 a single signal appears only if the J-and the trigger 10 is in the single state, and the output of the j-th comparison element 9 is also a single signal,

five

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five

. 31

At the second stage of the device operation, a selection is made from among the independent tasks of the task with the maximum duration of execution. This is done as follows. In the initial state, the tasks execution time codes are recorded in the triggers of the registers 38 of the block 3 for selecting the maximum number (from the registers 12 they are fed to the inputs 50 of the block 3). The set of compared numbers is set by setting the unit 3 of triggers 36 of unit 3 to select the maximum number of signals from the outputs of the corresponding And 11 elements on the inputs 48 of the maximum number selector 3. The launch of block 3 for selecting the maximum number at input 51 is provided by a pulse from the generator of 19 pulses through an element AND 18, provided that at least one processor of the computing system is free (if there is a signal at the inputs 43 of the device that sets the i- and flip-flop 16 to one , -1 1, and, where h is the number of processors of the computing system, according to which the output signal of the element OR 17 is a single signal). In this case, a one-by-one analysis of the compared numbers is provided as follows. If in the first digit of numbers there are both O and 1, then through the elements AND 30 and 31 of the analysis nodes 29 there are single signals for the group of elements OR 33 and 37. At the output of the NAND 36 element, a zero signal is generated, which is closed by the element AND 39,. Through the elements AND 32 analysis nodes and OR elements 34, belonging to those registers, in the first discharge of which O is recorded, a single signal is fed to the inputs of setting the corresponding triggers 35 to the zero state. And elements 30 and 31 of the corresponding analysis nodes are closed, and a single signal is only at the output of the OR element 37. At the output of the AND-NO element, a single signal is generated, according to which AND 39 is opened. Next, the analysis of the next bit of the remaining compared numbers is performed.

If in the first digit of the compared numbers only zero codes or

only single ones, then at the output of the AND-NO 36 element there is a single signal that opens the element AND 39. Therefore, in this case

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5 y 15 20 25 h. 35

40

45

55

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An analysis of the second or subsequent bits is performed immediately. After all bits of the compared numbers are analyzed, a single level is formed at the output of the AND 39 element. At the same time, the outputs 32 of the maximum number selection block 3 contain the unitary code j of the task number with the maximum execution time from the number specified (unitary code 00100 indicates that the third task number is selected).

A single signal on the K-th selected output 52 of the block 3 for selecting the maximum number allows the passage of the K-th task number code and its source data from the K-th register 13 through the K-th block of elements AND 14, the block of elements OR 15 to the first inputs of the blocks of elements And 21. In addition, the signal from the K-th output 52 of the block 3 for selecting the maximum number sets the K-th trigger 10 to the zero state, which is excluded from further analysis of the K-th task.

At the third stage, the operation of the device ensures assignment of the selected task to a free processor of the computing system and correction of the matrix of the information control graph, i.e. setting the triggers to the zero state 4 matrices of 1 of those rows, the numbers of which correspond to the codes of the task numbers served by the processors. The processor readiness signals at the device inputs 43 set the corresponding triggers 16 to one state and allow the K code of the selected task with the maximum duration to pass through the block of elements And 21 corresponding to the free processor with the minimum number. This is provided by the block of elements OR-NOT 22, in which the 5th input 43 of the device is connected to the inputs (i + 1, h) of the IPI-NE elements. Thus, the signal at the 1st lower input 43 of the device prohibits the passage of information through blocks of elements And 21 with large numbers. The code of the K number of the task and the source data for its execution are fed to a group of outputs 47 of the device. In addition, at the output of the i-th element OR 20, a single signal appears, which sets the first trigger 16 to the zero state, which indicates the occupation of the 1st processor of the computing system.

Upon completion of the K-th task service (the -th processor appears at the i-th readiness input 43 of the device, a single signal appears, at the input group A4 - the K-number of the served task. The K-code is decoded by the decoder 23, through the K-th element OR 24 The triggers 4 of the Kth row of the matrix 1 and through the OR 25 element are fed to the input of the OR 2 element, then perform the function of a trigger pulse, and the first stage of the device operation is repeated.

When all the triggers 4 of the matrix 1 are zeroed, the outputs of all the elements of OR 5 are zero signals, and the output of the element OR NOT 26 is a single signal. This signal, through delay element 27, zeroes counters 7 and 8 and enters output 46 of the device. The operation of the device ends there.

Claims (1)

Invention Formula A device for distributing a task in a computer system containing a matrix of arcs of N -.N triggers (N is the number of tasks to be implemented), the first, second and third elements of OR, the first group of triggers, the first and second groups of registers, the first second, third and the fourth group of elements AND, the first, second and third groups of elements OR, the element AND, the element IL-NOT, the first and second elements of the delay, a group of counters, a counter, a group of comparison circuits, with j and the input (c, j 1, M) of the first group of information inputs of the device is connected to a single input from the j-th trigger of the array of arcs; single outputs of the triggers of the j-th column of the arc-forming array are connected to the inputs of the j -th element OR of the first group, the outputs of the elements OR of the first group are connected to the inputs of the OR-NOT element and the first inputs of the corresponding elements AND of the first group, the outputs of which are connected to the counting inputs of the corresponding group counters, the outputs of which are connected to the first inputs of the corresponding V comparison circuits ppy outputs the comparison circuits connected to the first group of inputs of the corresponding AND gates of the second group, j s input of the second group of information inputs Arrange o 50 five Q 0 five five 0 state is connected to the information input of the j-th register of the first group, the outputs of the registers of the first group are connected to the first inputs of the corresponding AND elements of the third group, the outputs of which are connected to the inputs of the OR elements of the second group, the outputs of which are connected to the first inputs of the AND group of the fourth group, the outputs of which It is connected to the group of information outputs of the device, the trigger input of the device is connected to the single inputs of the first group trigger and the first input of the first OR element, the output of which is connected to the second inputs Both the first group of elements and the counting input of the counter, the output of which is connected to the second inputs of the group comparison circuits, the output of the NAND element are connected to the input of the first delay element, the output of which is the device shutdown output and connected to the zero inputs of the group counters and counter about t-lich. In order to reduce task service time in a computer system, a block for selecting the maximum number is entered into the device, the second group of triggers, the pulse generator, the group of elements OR-NOT, the group of decoders, the fourth group of elements OR, and the input j- second register of the second group is connected to the Jth input of the third group of information inputs of the device, the outputs of the registers of the second group are connected to the corresponding inputs of the first group of inputs of the block for selecting the maximum number, j is the output of the output group of which single with the second input of the corresponding element of the third group and zero input J is the trigger of the first group, the single outputs of the first group of flip-flops are connected to the second inputs of the corresponding elements of the second group whose outputs are connected to the corresponding inputs of the second group of inputs of the maximum number selection block, generator output pulses are connected to the third inputs of the elements AND the second group and the first input of the element I, the output of which is connected to the first triggering input of the maximum number selection unit and the input of the second the second delay element, the output of which is connected to the second triggering input of the maximum number selection block 7123 and third inputs of elements AND of the third group, outputs of elements AND of the fourth group are connected to the inputs of the corresponding elements OR of the third group, the outputs of which are connected to, zero inputs of the corresponding triggers of the second group, single outputs of which are connected to the inputs of the second OR element, the output of which is connected to the second input of the element AND, the single inputs of the second group of trigger inputs to the information inputs of the fourth group of device inputs, second inputs of the fourth group of elements of the fourth group, inputs of elements ilJ ... E 1 ± and you   -iLa eight 161 NO groups, 1st output (j 1, N-P element OR-NOT Group is connected to the third input i + 1 element AND the fourth group, the inputs of the group decoders are a group of inputs of the device job number code, the decoder outputs are connected to the corresponding inputs the OR elements of the fourth group, the outputs of which are connected to the inputs of the third OR element and the zero inputs of the flip-flops of the corresponding row of the array of arc drivers, and the output of the third OR element is connected to the second input of the first OR element. V7 Lj Sh-sh Editor N. Rogulich Compiled by S. Nazarov Tehred SiSopko Proofreader E. Sirohman Order 2772/51 Circulation 671 Subscription BNISH USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk .ab. 4/5 Production floor igraphic enterprise, Uzhgorod, st. Project, 4