SU1242982A1 - Device for determining minimum paths in graphs - Google Patents

Abstract

The invention relates to computing and can be used to assess the reliability of systems described by graphs. The purpose of the invention is to expand the functionality of the device by finding independent paths in the graph between two vertices. The device consists of a matrix model of a graph, groups of elements OR, AND, NOT, a code calculation unit, a maximum number of control triggers and triggers, elements AND , OR, NOT and NAND, the decoder clock generator. The device allows you to find the minimum path in the graph. In addition, the group of elements I, the counter, the decoder, the RSHI element, the differentiating chain and the memory block are introduced, which ensure the sequential finding of minimum paths in the graph and their storage in the storage unit. 2 з.п, ф-л, 3 Il. § GCR

Description

1242982

The invention relates to computing and can be used to quantify the reliability of systems described by graphs.

The aim of the invention is to enhance the functionality of the device by finding independent paths in the graph between the two vertices. .

FIG. 1 is a functional diagram of the device in FIG. 2 is a functional diagram of the arc former in FIG. 3 - a functional block diagram of the memory.

 The device for determining the minimum paths in the graphs contains the matrix model of graph 1, formers of arcs 2 ,,, the first group of elements OR 3 ,, - 3 (,, the second group of elements OR 4, -4 ", the trigger group p

ditch, a group of elements is NOT the first group of elements And 7, | -7, register counters, second group of elements AND 9, -9, block 10 of calculating the maximum number code, third group of elements AND 11, -11p, group of registering triggers 12j-12f ,, memory block 13, differentiating the chain 14 , element AND-NOT 15 generator 16 clock pulses, element And 17, element DPS 18, element NOT 19, first counter 20, element And 21, first decoder 22, second counter 23, second decoder 24, fourth group of elements And start input 26 devices.

The arc shaper contains the first trigger 27, the first element And 28 the second trigger 29, the second element And 30, differentiating the chain 31.

The memory block contains a group of elements AND 32, | - 32 "p ,, trigger group 33 ,, - 33 ,,, a group of elements TILI 34, - 34, a group of elements NOT 35, -

The device works as follows.

Initially, information from the topology of the graph is entered into model 1. At the same time, the triggers 27 of the corresponding formers Doug 2 Jj (i ,, n where n is the number of vertices in: the simulated graph, are set to one state if there is an information link from the i-th vertex to the j-th vertex. The corresponding driver is defined It is the intersection of the line number l (vertex) and the column number i (i-vertex).

0

five

0

five

All the triggers 29 of the arc drivers 2 m are set to the zero state, as well as all the triggers 32 of the memory block, the first counter 20 is in the reset state. The trigger state 5f |, corresponding to the final vertex of the graph, and trigger 12, corresponding to the initial vertex of the graph, are set to one.

The device operates in cycles.

In each cycle, it finds one minimum path in the graph. The trigger signal from the start input 26 through the element OR 18 resets the counters 8 and 23, sets the triggers 5, except trigger 5, triggers 12, except trigger 12, to the zero state, and goes to the element AND 17. Pulses from the generator 16 clock pulses through the element And 17 arrive at the inputs of the elements And 7 of the first group. The pulses will pass through those elements: And 7, at the second entrances of which there is a high potential. Initially, all the triggers 5, except for the trigger 5, are in the zero state, and the zero potentials from their outputs through the elements of the He 6 group are transferred to high potentials and fed to the second inputs of all And 7 elements, except the And 7 element. Counting pulses through the elements And 7, except for the element And 7, arrive at the register counters of group 8. At the same time, the high potential from the output of the trigger of group 5, which is in the single state, goes to the input of the same name of the AND –NE element and transfers the triggers of the 27 formers of the arcs of the same name to zero. condition. The flip-flop of triggers 27 to the zero state causes the pulse to appear through the differentiating chain 31 at the inputs of the flip-flops 29, as a result of which they remember the previous state of the triggers 27 of the same name of the former 2 arcs, and the pulse from the second group at the input of the trigger 5 next column. This impulse translates trigger 5 into a single state, as a result of which the high potential from the output of trigger 5 is transformed by element 55 NOT to zero potential at the output of element 7. And the increase in the inhibitory potential at the input of element 7 stops the counting them.

40

 45

50

pulses on the recording counter 8 of the next column. This forms the prohibition of the arrival of counting pulses at the inputs of the registering counters 8, from the corresponding vertices of which the arcs emanate, leading to the previously formed vertex. .

The arrival of counting pulses to the counters continues until all the triggers of the 5th group are transferred to one state. This indicates that all nodes of the studied graph are formed. The presence of high potentials at the outputs of the flip-flops 5 through the elements AND-NOT 15 stops the supply of pulses from the generator output to 16 clocks through the element 17 and the inputs of the elements of group 7. The number of pulses arriving at the registering counters 8 corresponds to the codes for the minimum paths of the graph (by the number of arcs that make up the path) from this (including the initial) vertex of the simulated graph.

The low potential from the output of the element NE-15 through the element NOT 19 provides the delivery of counting pulses from the output of the generator 16 through the element 21 to the second counter 23, from the output of which information is fed to the input of the decoder 24. The output of the decoder 24 is alternately excited from the first and ending nth. When the first output bus is excited at the output of the decoder 24, a high potential arrives at the input of the element And llj /, as a result of which a high potential will arrive at the second inputs of the elements 30 of the first column of the matrix model of the graph. A high potential is observed only at those outputs of elements AND 30 formers of 2 arcs, the corresponding triggers 29 of which are in a single state, therefore only in these lines there will be high potentials on the OR elements of the 3 groups that arrive at the second inputs of the corresponding elements AND 9 groups, as a result of which, the inputs of block 10 receive codes from the corresponding recording counters 8. Block 10 provides the selection of the maximum number of codes received at its inputs and transferring the corresponding trigger (or trigger 10

15

20

five

429824

geers, if there are several) 12 in

single state.

Next, another pulse is added to the contents of counter 23, the next bus is excited at the output of the decoder 24, and the process of identifying the vertices that form, and their minimum path lasts until the trigger 12, corresponding to the last vertex of the graph, is placed in one state. When trigger 12 goes to a single state at the output of the differentiating chain 14, the pulse that arrives at the input of the counter 20, the information from the output of the counter 20 enters the decoder 22, resulting in a high potential at its first output inputs of elements AND 32 of the first row of block 12. Potentials from the outputs of the corresponding recording triggers 8 are fed to the first inputs of elements of AND 32 of the same column. High potential is at the outputs of only those elements of AND 32 of the first row of block 12 , the first inputs of which are fed a high potential from the outputs of the corresponding recording triggers 8 that identify the vertices of the minimum path in the graph. Under the action of high potentials from the outputs of the And 32 elements of the first -line of the block 13, the flip-flops 33 will be transferred to the unit state - 5. Thus, the triggers 33 of the first row of the memory block 13 are stored in the first minimum path.

At the same time, the pulse from the output of the differentiating chain 14 will go to the input of the element OR 18 and will make a new launch of the device. In this case, the starting impulse from the output of the element IL 18 also goes to the second inputs of elements AND 25 of the fourth group. The impulse will pass only through those elements And 25 of the fourth group, at the first inputs of which a low potential is supplied from the outputs of the flip-flops 33 of block 13 through the elements OR 34 and the elements 0, NOT 35. The pulses from the outputs

elements And 25 of the fourth group are fed to the second inputs of elements And 28 and triggers 29 shapers. arcs 2 of the same name row of the matrix 5 model of the graph 1. A pulse at the input of the element I 28 ensures the switching of the trigger 27 to the unit state, if in the unit state it is

A trigger 29 is reached, and a pulse, at the input of the trigger 29, ensures its switching to the zero state.

Thus, model 1 will contain information about the topology of the original graph, in which arcs are excluded, starting from the vertices constituting the minimum paths defined in the previous cycles of the device and under the effect of the starting pulse from the output of the element OR 18, a new cycle will begin. In each cycle, the recording of the minimum path is impaired into the new line of the flip-flops 33 of the storage device 13, as in the causal cycle, the high potential from the output of the decoder 22 will be fed to the inputs of the And 32 elements of the next line of the block 13.

The operation of the device continues until model 1 contains information about the topology of the unrelated graph, with all independent paths between the pair of vertices being recorded in block 13 of the storage device.

Claims (3)

1. Device for determining minimum paths in graphs containing a matrix model of a graph, arc generators by the number of rows and columns of a matrix model of a graph, the first group of elements OR by the number of rows of a matrix model of a graph, the second group of elements OR by the number of columns of a matrix model of a graph, group trig - gers by the number of columns of the matrix model of a graph, a group of elements NOT by the number of columns of the matrix model of a graph, the first, second and third groups of elements AND by the number of columns of the matrix model of a graph, a group of registers x counters the columns of the matrix model of the graph, the group of registering triggers by the number of columns of the matrix model of the graph, the element AND-NOT, the first and second shements And, the element -NE, the first counter, the first decoder, the block for selecting the maximum number code and the clock pulse generator, the first information the output of each i, j-ro mapper of the arc of each i-th row of the matrix model (i ,, 2, ..., n) is connected to the j-th input of the i-ro element 11PI of the first group, whose code five 0 five 0 five 0 five O five connected to the first input of the element of the same name AND of the second group, the output of the register counter of the column of the same name, the second information output of each i, j-ro former is connected to the second input of each element AND of the second group. arc is connected to the i-th input of the FUIH element of the second group, the output of which is connected to the installation input of 1 identical trigger groupj and the output of each j-ro group trigger is connected to the input of the same element NOT group, to the first inputs of the arc former of the same name line and to j-i -ty input of the element is NOT, the output of each element of the NOT group is connected to the first input of the element of the same name AND of the first group, the output of each element of the first group is connected to the counting input of the same recording group counter, the outputs of the elements of the second group We are connected respectively to the inputs of the block of selection of the maximum number code, each (the th output of the group of information outputs of which is connected to the installation input to 1 of the corresponding registering trigger group, the output of each recording trigger is connected to the first input of the same element AND of the third group, the output of each element AND the third group is connected to the second information inputs of the formers of arcs of the same name column of the matrix model, the output of the clock generator is connected to the first inputs of the first The second element is AND, the code of the first element AND is connected to the second inputs of elements AND of the first group, the output of the element AND NOT is connected to the second input of the first element AND, to the input of the element NOT, the code of which is connected to the second input of the second element And whose output is connected to the counter - to the input of the first counter, the output of which is connected to the input of the first decoder., the outputs of the first decoder are connected respectively to the second inputs of the third AND group: group, characterized in that, in order to expand the functionality of the We are able to find independent paths in the graph between two vertices, the element OR, the second counter is entered into it. the second decoder, the memory block, the differentiating chain and the fourth group of elements AND by the number of rows of the matrix model of the graph, the first input of the OR element is the device start input, and the second input of the OR element is connected to the output of the differentiating chain, whose input is connected with the output of the n-th registering trigger group, the output of the element OR is connected to the first inputs of the elements AND of the fourth group, with the third information input of the arc former of the n-th row of the first column of the matrix model of the graph, with the third input And, with the zeroing input of the first counter, with the zeroing inputs of group triggers and the zeroing inputs of the registering counters of the group, the counting input of the second counter is connected to the output of the differentiating chain, and its output is connected to the input of the second decoder, the outputs of which are respectively connected to the first group of information the inputs of the memory block, each input of the second group of INFORMATION inputs of which is connected to the output of the corresponding registering trigger group, each output of the group of outputs of the memory block n Connected to the second input of the same element of the fourth group, the output of each element of the fourth group is connected to the third inputs of the formers of the arcs of the same name of the matrix model of the graph, except for the former of the arc of the nth row of the first column; matrix graph model. 2. The device according to claim 1, characterized in that the arc generator of the matrix model of the graph contains the first and second triggers, the first and second elements AND, a trimming chain, and the input of the installation in O of the first trigger is connected to the first information input 15 20 the arc former, and the output of the first trigger is connected to the input of the differentiating chain, the output of which is connected to the input of the installation in 1 of the second trigger and is the first. the information output of the arc generator, the output of the second trigger is connected to the first inputs of the first and second, And elements, the code of the first I element And is connected to the input of the first 1 trigger, the second input of the second element And is the second information input of the arc generator, and the output The second element And is the second information output of the arc generator, the second input of the first element And and the installation in the O of the second flip-flop are the third information input of the arc generator. 3. The device according to claim 1, 1 of which is that the memory block contains memory cells by the number  rows and columns of the matrix model of a graph, a group of elements OR by the number of columns of the matrix model of a graph, a group of elements NOT by the number of columns of the matrix model of a graph, each memory cell contains an element AND and a trigger whose input is connected to the output of element AND, and the output of trigger i- j cell of a j-ro column is connected to the i-th input of the j-ro element OR group, the output of each 5 elements of the OR group is connected to the input of the element of the same name NOT the group, the code of each element of the NOT group is the corresponding output of the group of outputs of the memory block, the first  the inputs of the elements and memory cells of each i-th column are combined and are the first group of information inputs of the memory block, the second inputs of the elements of the memory cells of each 5th j-th lines are combined and are the second group of information inputs of the memory block. Sh fiv.1 (PU2.2 Editor V.Ivanova F / ,. lf Fig.Z Compiled by T. Sapunova Tehred I. Khodanych Proofreader T. Reshetnik Order 3707/49 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4