SU1376097A1 - Device for simulating network graphs - Google Patents

Abstract

The invention relates to computing and can be used in the construction of specialized computing devices for modeling and solving network problems. The purpose of the invention is to simplify the device. This is achieved in that a device containing a matrix of 1 arc drivers, a 3 pulse generator, triggers of 4 arc formers, a group of elements OR 5, a group of elements AND 6 and a group of counters 7, additionally introduced a group of elements BANGE 2 and an element AND 8. The essence of the invention consists in the fact that the use of the group of BANKS elements instead of the group of comparison blocks and the pulse number counter simplifies the technical implementation of the function of excluding from the simulated graph of arcs emanating from vertices distributed by rank. Starting the pulse generator on the input signal of the device and stopping this generator on the signal about the end of the distribution of all the vertices generated by the element And 8 excludes from the scheme of the basic device the control unit, which ultimately leads to the creation of a new device that implements all the functions of the basic device, but different from him more than a simple execution. 1 il. l cr 00 h4 O) O with si

Description

The invention relates to computing and can be used in the construction of specialized computing devices for modeling and solving network problems.

The purpose of the invention is to simplify the device.

The drawing shows the functional diagram of the proposed device.

The device contains a matrix of 1 arc formers, a group of BANKS 2, a generator of 3 pulses, triggers of 4 arc formers, a group of elements OR 5, a group of elements AND 6, a group of counters 7, an element AND 8,

The device works as follows.

Initially, information about the topology of the simulated network graph is entered into the matrix. In this case, the triggers of 4 formers of arcs simulating the branches of the graph are set to one. condition. The corresponding trigger of the arc formers is determined by the intersection of the row with the number equal to the number of the starting node of the simulated branch and the column with the number equal to the number of its ending node. After the initial information is applied, the outputs of elements 5 that combine the outputs of the triggers of the 4 Arcs in the columns corresponding to the initial nodes of the simulated graph have low potentials, since in the unidirectional graph without cycles and loops, the initial nodes do not contain incoming branches and the triggers of the arc formers those in this column will be in the zero state. The registering counters 7 in the initial state are reset to the zero state.

With the advent of a signal at the input of the device, a generator of 3 pulses is started. The first impulse from generator 3 enters the entrances of elements AND 6 of the group and produces an increase by one unit of those counters 7 groups that correspond to incomplete zero columns of matrix T. The vertices corresponding to zero columns of matrix 1 have zero rank, which is fixed by maintaining the zero value corresponding counters of group 7. The first

five

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the pulse after the passage of the elements And 6 of the group controls the inclusion of arcs from the graph emanating from the vertices corresponding to the zero rank. This is provided with the help of the elements of the PROHIBITION 2 groups, each of which allows the passage of signals from the second input to the output only if there is no inhibitory signal at its second input. Consequently, during operation, the signals appear at the outputs of only those BANNER elements 2 groups that correspond to vertices of zero rank. These signals zero the triggers of the 4 corresponding rows of matrix 1.

With the full distribution of the vertices of the graph element And 8 will generate a signal to stop the generator 3 and complete the operation of the device.

The value of the number of pulses recorded in the counters 7 is equal to the numbers of the ranks of the corresponding vertices of the simulated graph.

Claims (1)

Invention Formula A device for simulating network graphs containing a pulse generator, a matrix of arc formers, a group of elements OR, a group of elements AND and a group of counters, a counting input j-ro counter (, ..., n, where n is the dimension of the graph vertex matrix) of the group is connected to the output of the j-ro element AND group, the output (i, j) of the th arc generator (, .., i) is connected to the i-th input of the j-ro element OR group, the output of which is connected to the first input of the j-ro element AND group It is distinguished by the fact that, in order to simplify the device, it contains a group of the elements BANNER and the element AND, moreover, The device is connected to the start input of the pulse generator, the output of which is connected to the second inputs of all elements of the group and to the second inputs of all elements of the BANNER group, as well as to the (n + 1) th input of the element And, the output of the j-th element of the group is connected to the first input of the i-ro element of the PROHIBITION of the group, the output of which is connected to the i-th input of the AND element to the inputs of the formers of arcs of the i-th row of the matrix, the output of the AND element is connected to the input of the stop of the pulse generator.