SU1203534A1 - Device for simulating network graphs - Google Patents

Description

the second; the inputs of elements And of the second group of the vertex rank block are connected to inverse inputs of the corresponding blocks of elements AND node of the rus duration determination and are connected to the moves of the corresponding elements OR of the block of ranks of vertices, the outputs of elements And of the second group of the rank blocks of vertices are connected to zero inputs of triggers of the same name rows of trigger matrix Rank block Verification relates to computing and can be applied when solving the tasks of determining the duration of the continuous execution of a network graph.

The purpose of the invention is to simplify the device and increase its speed.

The drawing shows a functional diagram of the device.

The device contains a registration unit 1, a control unit 2, a control unit 5, a unit for determining the length of a rus, a block of 4 ranks of vertices, a generator of 5 pulses, an installation 6 and a starting 7 inputs. Node 1 contains block 8;) elements AND, adder 9 and counter 1 block 2 - first 11 and second 12 elements OR, first 13 and second 14 elements And trigger 15, node 3 - group of registers 16, group of blocks 17 elements And, the element OR 18, a group of blocks 19 comparison. Block 4 contains the matrix h h (and is the number of graph vertices) of the triggers 20, the group of elements OR 21, the second group of pieHTOB And 22, the group of counters 23 and the first group of elements 24.

The device works as follows: im image.

I

In block 4, the graph topology information is entered by setting triggers 20 to one state j, the corresponding trigger 20 is determined by intersecting the row with the number of the starting node of the branch and the column with the number of the ending node o At the outputs of the elements OR 21, the corresponding ah

03534

The mHHj output of the second element OR of the control unit is connected to the stop input of the pulse generator, the output of the first element I of the control unit is connected to the installation input of the counter of the registration unit, the information input of which is connected to the output of the second element AND of the control unit whose first input is connected to the inverted trigger output of the control unit .

| columns of initial nodes, there are low potentials, because in a unidirectional graph without cycles and loops, branches to initial nodes are not

triggers 20 in these columns are in the zero state. The registers 16 enter the codes of the duration of the nodes of the graph.

The initial setup signal from input 6, the device is fed to the setup inputs of the adder 9, counter 23, wrapped them, and through the element OR 11 to the single input of the trigger 15; set it to the unit

condition. With the arrival of the start signal from input 7 to the start input of generator 5, signals that synchronize the operation of the device appear at its output. Single potential. On

the direct output of the trigger 15 permits the passage of the first pulse of the generator 5 through the element I 13 to the installation input of the counter 10, is set to 1 in all its bits,

zero input trigger 15 and control inputs of the elements And 24.

Subsequent pulses of the generator 5 through the element And 14, open single signal from the inverse output of the trigger 15, are fed to the subtractive input of the counter 10, reducing by one its code. This code is fed to the inputs of blocks 19 for comparison with the contents of registers 16. Comparison

it is produced only with the contents of those registers 16, whose codes are received through blocks 17 of elements AND, opened by null potentials from the outputs of the corresponding elements OR 21. When

 one

the coincidence of the codes in one of the blocks 19, the signal from its output through the element OR 18 is fed to the control input of the block 8 elements AND, allowing passage to the adder 9 from the counter 10 of the code corresponding to the duration of the zero-run, and through the element OR 11 to the input of the trigger 15 into one state. The same signal from the output of block 19 through AND 22 elements, which are open by zero potentials from the outputs of OR elements 21, resets to the zero state the triggers 20 of the corresponding row of the matrix and the corresponding

03534

registers 16. This completes the definition of the vertices of zero rank and the determination of the length of the rus, which includes the m.

5 Similarly, the successive vertices of the next ranks and the length of the keypad are summed up, summed to the contents of the adder 9. The process continues until

10 as long as all the triggers are 20

will be reset. Then the zero signals from the outputs of the elements OR 21 post. fall on the inputs of the element OR 12, the zero potential from the output of which arrives at the input of the stopping of the generator 5.

Claims (1)

DEVICE FOR SIMULATING NETWORK GRAPHS, comprising a registration unit consisting of a counter, a block of AND elements and an adder, a control unit consisting of two OR elements, a trigger and two AND elements, a node for determining the length of a tier consisting of a group of blocks of AND elements and an OR element, a vertex rank block consisting of a gene matrix (where h is the number of graph vertices) of triggers, a group of OR elements, a first group of AND elements and a group of counters, and a pulse generator, the start input of which is the start input of the device, and in the node itrations, the first input and output of the block of AND elements are connected respectively to the bit output of the counter and the information input of the adder, in the control unit, the output of the first OR element is connected to a single input of the trigger, the direct output of which is connected to the first input of the first And element, and the second inputs of the first and second elements And connected to the output of the pulse generator, in the block of ranks of the vertices, the outputs of the triggers of the columns of the matrix are connected to. the inputs of the corresponding OR elements, the outputs of which are connected to the first inputs of the elements of the same name AND the first group, the outputs of which are connected to the information inputs of the same counters of the group, the installation inputs of which are connected to the installation input of the adder, the first input of the first element AND of the control unit are the installation input of the device, outputs OR elements of the vertex rank block are connected to the inputs of the second OR element of the control unit, the output of the first element AND of the control unit is connected to the second inputs of the element ntents And of the first group of a block of ranks from the vertices, characterized in that, in order to simplify the device and increase its speed, a group of registers and a group of comparison blocks are entered in the node for determining the length of the tier, and in the block of ranks of the vertices there is a second group of AND elements, the first inputs of which are connected with the control input of the block of elements AND of the registration unit, the second input of the first element OR of the control unit and connected to the output of the element OR of the node for determining the length of the tier, to the inputs of which the outputs of the comparison blocks are connected, the first the odes of which are connected to the outputs of the corresponding blocks of AND elements, the second inputs of the comparison blocks are connected and connected to the bit output of the counter of the registration unit, the outputs and inputs of the registers are connected respectively to the first inputs of the blocks of elements AND of the node for determining the length of the tier and the outputs of the corresponding elements And the second group of block of vertex ranks , SU „1203534 second: inputs of the elements AND of the second group of vertex rank block are connected to the inverse inputs of the corresponding blocks of elements AND of the node for determining the length of the tier and connected to the outputs of the corresponding elements OR group of the block of vertex ranks, outputs of the elements AND of the second group of the block of vertex ranks connect! with zero inputs of the same line triggers of the matrix of triggers of the vertex unit block, the output of the second element OR of the control unit is connected to the stop input of the pulse generator, the output of the first element AND of the control unit is connected to the installation input of the counter of the registration unit, the information input of which is connected to the output of the second element AND of the block control, the first input of which is connected to the inverse output of the trigger of the control unit. .1