SU1120341A1 - Device for studying parameters of graph - Google Patents

Abstract

A DEVICE FOR RESEARCHING GRAPH PARAMETERS containing a clock pulse generator, the output of which is connected to the first input of the first element AND, the second input of which is connected to the output of the element NO, the input of which is connected to the overflow output of the reversible counter, which subtracts the input of which is connected to the output of the first element AND, This is due to the fact that, in order to expand the functional capabilities of the device due to the possibility of calculating the ranks of the graph vertices, the second element I, the element rzhki and n computing blocks, each of which consists of a shift register, a key block, the first and second groups of elements AND, the first and second elements OR, the first, second and third, its decoders, the first, second reversible counters, the counter, the first and the second elements of the NOT, the first and second elements And, the information block, and in each computing unit the outputs of the key block are connected to the installation inputs of the bits of the shift register, the outputs of the bits of the register of the shift register are connected to the first inputs of the elements And the first and second The first group, the outputs of the elements And the first group are connected to the input of the first IZH element, the output of which is connected to the summing input of the first reversible counter, the output of which is connected through the first decoder to the input of the first element NOT, the output of which is connected to the first input of the first element And the computing unit, the output which is connected to the subtractive input of the first reversible counter and to the second input of the corresponding element AND of the second group, the outputs of the elements AND of the second group are connected to the inputs of the second (L element OR, the output of which is connected (Chen to the information input of the counter, the output of which.the second decoder is connected to the input of the indication unit, the output of the last bit of the shift register is connected to the installation input of its first digit and connected to the summing input of the second reverse counter, whose input is connected to the output of the second: “element of the AND computational unit, the first input of which is connected to the output of the second element NOT, the input of which is connected to the output of the third decoder, the input of which is connected to the output The second reversible counter, the shift inputs of the shift registers of all computational units are connected to the output of the first element I, the output of the third decoder of each computational element of the block is connected to the corresponding input of the second element I, the output of which is connected to the second input of the first ele

Description

And the first computational unit, the output of the first decoder of each computational unit, except the last one, is connected to the second input of the first element, and the subsequent computational unit, the third input of the first element, And each computational unit is connected to the output of the clock generator, the output of the third decoder of each computational unit, in addition to the latter, connected to the second input of the second element And the subsequent computing unit, the second input of the second element And the first computing unit connected to the output of the reversible counter, the third input of the second element AND

0341

each computational unit is connected to the output of the clock generator, the output of the second element And the 1st computational unit is connected to the second inputs of the i-th elements of the first group and computational blocks, the output of the first element of the M-th computational unit is connected to the second inputs - D- x elements And the second group of p computing units (where {1,.,., h), the installation inputs of shift registers, counters, first and second reversible counters of all computing units are combined and connected to the input of the delay unit, the output of which connected to the inputs of the block of computing unit blocks.

The invention relates to computing technology, is intended for studying graph parameters, in particular for determining the ranks of graph vertices, and can be used for optimal distribution

: costs in building structurally complex systems, assessing the significance of elements in technical diagnostics, etc.

A device for examining connectivity and a probabilistic graph, containing a matrix of triggers, elements AND by the number of rows of a matrix of triggers, elements OR by the number of columns of the matrix of triggers OH, is closest to the invention by technical essence is a device for exploring paths in graphs containing the matrix fi x n triggers of forming arcs of a graph and a clock pulse generator, the output of which is connected to the first, the input of the element I, the second input of which is the input of the device, elements And arcs, according to the number of columns of the matrix e ementy OR, delay elements, registers, first, second and third groups of elements and group elements

.OR, multi-input adder, maximum selection node, decoder, element NOT and reversible counter, the input of which is connected to the output element

And, the third input of which is NOT connected via the element to the output of the device and to the output of the reversible counter, the VIEHD, which is connected to the input of the decoder, the -th (i 1, 2, ..., n) whose output is connected via the delay element to the control input the element And the first group of the i-th column, to the control input of the element AND the i-th column and to the first inputs of the elements And arcs of the row, the output of each trigger of arc formation is connected to the second INPUT1. the element And the arc, the output of each of which is connected to the input of the element OR of the i-ro column of the same name, the output of the element OR is connected to the control input of the element AND of the second group of the t-th column whose output is connected to the corresponding input of the maximum selection node, the output of the latter is connected to lane, input of a multi-input adder, the output of which is connected to the information inputs of the elements AND of the first group, output of the element AND of the first group of the i-ro column is connected to the input of the register of the i-ro column, the output of which is connected to the information input of the of the second group of the i-ro column and to the information input of the element of the third group -l-ro column, the outputs of the elements of the third rpyn-j

jTibi are connected respectively to the inputs of the OR elements of the group, the outputs of which are connected to the second input of the many input adder 2. A disadvantage of the known devices is the impossibility of calculating the ranks of the graph vertices. The purpose of the invention is to expand the functionality of the device by providing a calculation of the ranks of the graph vertices. The goal is achieved in that the device for examining the graph parameters contains a clock pulse generator, the output of which is connected to the first input of the first element AND, the second input of which is connected to the output of the element NO, whose input is connected to the overflow output of the reversible counter, which subtracts the input connected to the output of the first element And, introduced the second element And, the delay element and n computational blocks, each of which consists of a shift register, a key block, the first and second groups of elements And, first and second OR elements, first, second and third decoder, first, second reversible counters, counter, first and second elements NOT, first and second elements AND, information block, and in each computing unit the outputs of the key block are connected to installation inputs the shift register bits, the outputs of the shift register bits are connected to the first inputs of elements of the first and second groups, the outputs of elements of the first group are connected to the input of the first element OR, the output of which is connected to the summing input of the first reversible counter, the output of which through the first decoder is connected to the input of the first element NOT, the output of which is connected to the first input of the first element AND of the computational unit, the output of which is connected to the subtractive input of the first reversible counter and the second input of the corresponding element And the second group, the outputs of the elements And the second group are connected to the inputs of the second element OR, the output of which is connected to the information input of the counter whose output through the second decoder is connected to the input of the display unit, output The last bit of the shift register is connected to the setup input of its first bit and connected to the memory fy input of the second reversible counter, the subtractive input of which is connected to the output of the second element I of the computing unit, the first input of which is connected to the output of the second element NOT connected to to the output of the third decoder, the input of which is connected to the output of the second reversible counter, the shift inputs of the shift registers of all computational units are connected to the output of the first element And, the output of the third decrypt The mouth of each computational block is connected to the corresponding input of the second element, And the output of which is connected to the second input of the first element And the first computational block, the output of the first decoder of each computational block, except the last, is connected to the second input of the first element And the subsequent computation block, the third input of the first element And each computing unit is connected to the output of a clock generator, the output of the third decoder of each computing unit, except the last one, is connected to The second input of the second element And the subsequent computing unit, the second input of the second element And the first eight-unit block is connected to the output of the reversible counter, the third input of the second element And each computing unit is connected to the output of the clock generator, the output of the second element And the i-ro computing unit with the second inputs of the i-th elements And the first group of computational blocks, the output of the first element And the i-ro of the computational block connected to the second inputs of the -x elements And the second group h of the computation x blocks (where January 1, ..., h.), adjusting the inputs of shift registers, counters, the first and second reversible counters of all the computational units are combined and connected to the input of delay unit, whose output is connected to computational unit key block inputs. The proposed device calculates the rank of the vertices of the graph in accordance with the function (q1 + p; (qc ... p (1s), i 1 where P (Ic) is the number of paths of length I 3 going from the element (vertex) i to The drawing shows the proposed device. The device for examining the parameters of the graph contains the 1 1 shift registers, the key blocks, the first group of elements AND 3 - Zn, the second group of elements And 4 - Afj, the first elements of I.PI 5 -, the second elements OR 6-j - 6 ,, second 7 and first 8 - 8 reversible counters, counters 9 - 9, second decoders 10 - Yu, blocks 11 - llj, indications, first e decoders 12, 12j, the third decoders 13-, - 13 ,,, the first elements are NOT 14 - 14, the first elements are And 15 - 15, the second elements are NOT 16 - 16, the second elements are And 17 - 17, the second element And 18 delay element 19, input bus 20 Reset, bus 21, records of the number p reversible counter 22, element NOT 23, element 24, generator 25 clock pulses, input bus 26 Start, computing blocks 27. The device works as follows. Preliminarily, a number corresponding to the number of bits in the shift register C -1 is written to the reversing counter 22 via the input bus 21. The number of these bits also corresponds to the number of registers i. n, where and is the maximum difference of the adjacency matrix. Then, using a block 2-2, keys (for example, a jumper, a switch, etc.), the output of delay element 19 is switched to the input of register bits, and only those bits of registers that correspond to single elements of the adjacency matrix of the graph under study are switched. Each shift register corresponds to one corresponding row of the adjacency matrix, and the i-th bit of all registers corresponds to the -th column of this matrix. After switching the corresponding bits to the output of the delay element 19, the input bus 20 is given a reset pulse to the corresponding reset inputs of the 1–1 j shift registers, reversible counters 7–7, reversible counters 8–8 J counters 9-j – 9 dl bring them to zero state. The reset impulse delayed by delay element 19 writes, through the switched keys of a 2–2 key block, to the registers an adjacency matrix of the graph under study. After this operation is completed, the device is ready for operation. When applying the permit potential, the input bus 26 starts at the first input of the AND 24 element, and the clock pulses from the generator of 25 clock pulses appear at its output, since the input input of the AND 24 element is a single loss (HE from the output of the HE element 23, which disappears only when the state of the counter 22 is zero, i.e. after the n-th clock pulse. The clock pulses go to the control inputs of the registers 11 1 f, shift and information from the output of each register is fed to its input, as well as to the summing input corresponding reversing counter 7-, -7. After the arrival of the nth clock pulse to the second (subtractive) input of the reversing counter 22, it goes to the zero state, since in the initial state it contains the number n corresponding to the maximum dimension of the adjacency matrix. The output of the reversible counter 22 is the voltage of the logical unit, which, through the elements NOT 23, prohibits the further passage of the clock pulses through the element 24. During the t clock cycles, the information in the registers is completely rewritten and corresponds to the adjacency matrix. The corresponding reversible counters record the number of units contained in the corresponding row of the adjacency matrix. This is the end of the first iteration step. (h + 1) -th pulse from the generator 25 clock pulses through the element And the subtracting input of the reversible counter 7, since the element 15 is opened by a single potential from the output of the reversible counter 22 and the output of the decoder 12 through the element 14, and the counter 7 is in zero the state and at its output the voltage of a logical zero. Decoders and 13-13, at their output, the voltage of the logical unit is only in the case of the zero state of the corresponding reversible counter. Clock pulses, starting from (r + 1) -th, through element I, 15 begin to flow to the subtracting input of the reversing counter 7, as well as to the second inputs of the elements And 3 n corresponding to the first bits of all registers C - 1 shift, to the first inputs signals from the first bits of the respective shift registers are supplied. Therefore, if in the first discharge of the corresponding shift register 11-1 f, the unit is written down, the corresponding element AND 3-3 opens and the clock pulses through the corresponding element AND 3 the corresponding element of RSHI 5-5, arrive at the second summing input of the corresponding reversible counter 8 ., - 8. After the number of clock pulses, corresponding to the number of ones in the first row of the adjacency matrix, arrives at the subtracting input of the reversible counter 7, the counter goes to the zero state, at the output of the output signal. a voltage of logical unit appears, which through the element NOT 14 prohibits the passage of clock pulses through the element 15. The corresponding reversible counters write the number equal to the number of units in the first row of the adjacency matrix of the analyzed graph. The voltage of the logical unit from the output of the 1l decoder of the first group opens the element I 15-, since the first input of this element is supplied with the voltage of the logical unit from the element NOT 142. The clock pulses through the element 15 from the output of the clock generator go to the subtracting input of the reversible counter 7, as well as to the second inputs of all elements AND 3–3, corresponding to the second bit of all shift registers 1 ri, if one is written in them, then the clock pulses through the corresponding element OR 5–5 arrive at the summing input reversing counter. , t n After passing the clock pulses, the number of which corresponds to the number of units in the second line of the Mary, the adjacency, i.e. the number recorded in the reversible counter 7. At the output of the decoder 12, the first group 18 is the voltage of the logical unit, which through the element NOT 14 prohibits the passage of clock pulses through the element 5 and allows the passage of clock pulses through the next element 15 , In the future, the operation of the device proceeds in a similar way until the information from the last reversible counter 7 is not rewritten into the corresponding reversible counters 8 8p | . This completes the second iteration step. Single signals from the outputs of the decoders 12 - 12 are fed to the outputs of the element And 18, the voltage from the output of which opens the element And 17 for passing the clock pulses from the output of the generator 25 clock pulses, as the second input of the element And 17 receives the voltage of the logical unit output element HE 16, to the input of which a logical zero voltage is supplied from the output of the decoder 13. Clock pulses from the generator output 25 clock pulses are fed through the element 17 to the subtracting input of the reversing counter 8, as well as to the first inputs AND gates 4 - 4 corresponding to the first bit registers give 1 - 1 j shift to the second inputs of which are connected the outputs of the first discharge register rows 1 - 1 f shift. Elements AND 4-4p, which correspond to the first bits of the corresponding 1-1 shift registers, in which the unit is written, clock pulses through them and the corresponding elements OR 6-, -6 are opened, and written into the corresponding counters 9-9. the element AND 17 clock pulses, the number of which corresponds to the number recorded in the reversible counter 8, the counter 8 goes into the zero state and the output of the decoder 13 is the voltage of a logical unit. Therefore, at the output of the element NOT 16, a logical zero voltage appears, which prohibits the further passage of the clock pulses through the element And 17 ,. At the same time, the voltage of the logical unit from the output of the decoder 13 is fed to the first input and opens element I 17, through which the clock pulses begin to flow 9 to the subtracting input of the reversing counter 8 and the first inputs of elements I 4 - 4 corresponding to the second bits of registers 1 - 1 (the second column of the adjacency matrix), to the second inputs of which the outputs of the corresponding second bits of the 1–1 j shift registers are connected. The voltage of the logical unit from those bits in which the unit is written off opens the corresponding elements AND 4., - 4 and the clock pulses from their output through the corresponding elements OR arrive at the record in the corresponding counters 9–9 ,. The clock pulses through the element 172 pass until the reversible counter Sg goes to the zero state and closes it through the decoder 13, and the element NOT 16 element 17 and 17. The voltage of the logical unit from the output of the decoder 13j opens the next element 1 and 17, for the passage of clock pulses and the operation cycle proceeds in a similar way. The device operates until the information from the last reversing counter 8 is rewritten into the corresponding counters 9-9 (the third iteration step). After that, the passage of clock pulses to any elements of the device is prohibited by the elements And 15, - 15, 17 - 17 and 24. The information recorded in each counter 9., - 9, corresponds to the rank of the corresponding vertex of the graph under study. This information is decrypted by the corresponding decoder lOj - 1, and displayed on the corresponding block ll. - 11 |. indications. The proposed device, due to the presence of New Blocks and the connections between them, allows the calculation of the rank of the graph vertices.

Claims (1)

DEVICE FOR RESEARCH OF GRAPH PARAMETERS, containing a clock pulse generator, the output of which is connected to the first input of the first AND element, the second input of which is connected to the output of the element NOT, the input of which is connected to the overflow output of the reversible counter, the subtracting input of which is connected to the output of the first AND element, due to the fact that, in order to expand the functionality of the device at the expense of providing the ability to calculate the ranks of the graph vertices, the second element And, the delay element and η computing units, each of which consists of a shift register, a block of keys, the first and second groups of AND elements, the first and second elements OR, the first, second and third decoders, the first, second reversible counters, the counter, the first and second elements NOT, the first and second elements of And, the information block, and in each computing unit, the outputs of the key block are connected to the setting inputs of the bits of the shift register, the outputs of the bits of the shift register are connected! to the first inputs of the elements of the first and second groups, the outputs of the elements of the first group! connected! with the input of the first OR element, the output of which is connected to the summing input of the first reversible counter, the output of which through the first decoder is connected to the input of the first element NOT, the output of which is connected to the first input of the first element AND of the computing unit, the output of which is connected to the subtracting input of the first reversible counter and with the second input of the corresponding AND element of the second group, the outputs of the AND elements of the second group are connected to the inputs of the second OR element, the output of which is connected to the information input of the counter, you the course of which through the second decoder is connected to the input of the display unit, the output of the last bit of the shift register is connected to the installation input of its first discharge and connected to the summing input of the second reversible counter, the subtractive input of which is connected to the output of the second element AND of the computing unit, the first input of which is connected to the output of the second element is NOT, the input of which is connected to the output of the third decoder, the input of which is connected to the output of the second reverse counter, calculate the shift input of the shift registers of all ln blocks are connected to the output of the first element And, the output of the third decoder of each computing element of the block is connected to the corresponding input of the second element And, the output of which is connected to the second input of the first element 1120341 of the first computing block, the output of the first decoder of each computing block, except the last, is connected to the second input of the first element And the subsequent computing unit, the third input of the first element And of each computing unit is connected to the output of the clock generator, you the course of the third decoder of each computing unit, except the last, is connected to the second input of the second element And the subsequent computing unit, the second input of the second element And the first computing unit is connected to the output of the counter, the third input of the second element And of each computing unit is connected to the output of the clock the output of the second element AND of the t-th computing unit is connected to the second inputs of the элементов -th elements And the first group h of computing units, the output of the first element And the H-th computing of the unit is connected to the second inputs of the A-x elements And the second group of η computing blocks (where <= 1, ..., h), the installation inputs of the shift registers, counters, the first and second reversible counters of all computing blocks are combined and connected to the input a delay unit, the output of which is connected by the inputs of the block of kulches of computing blocks.