SU1241239A1 - Stochastic transformer - Google Patents

Abstract

The invention relates to the field of cleaning technology. The purpose of the invention is to increase speed. For this purpose, two counters, two switches, and two registers have been entered into the device, which are connected to each other and to the remaining blocks of the circuit by the corresponding functional links. The invention is expedient to use in stochastic computers for modeling and analyzing a number of random processes, as well as in various control devices with random selection for a limited time interval of a number from a certain set under conditions of dynamic assignment of bans on the use of individual numbers. The invention provides greater speed than the known ones, and can be used in highly reliable and fast systems, Il. c (O (L N 4 ND Au: &

Description

one

The invention relates to computing and can be used in stochastic calculator. machines for modeling a number of random processes.

The purpose of the invention is to increase the speed of work.

The drawing shows the functional diagram of the stochastic converter ..

The stochastic converter contains the first register 1, the outputs of which are connected to the inputs of the second register 2, the outputs of which are connected to the first group of inputs of the first switch 3. The outputs of this switch are connected to the information inputs of memory 4, and the second group of inputs of switch 3 is connected to the outputs the first counter 5. The address inputs of the memory block 4 are connected to the outputs of the second switch 6, the control input of which receives signals from the control block 7, which also controls the operation of blocks 1-5, the output register Strom 8, second counter 9 and 10 random numbers generator. The first input of the control unit 7 is connected to the output of the comparison circuit 11, and the second input of the unit 7 is the control input of the stochastic converter (Bx1). The first input of the comparison circuit 11 is connected to the output of the 4-unit unit, and the second input of the circuit 11 is the information input of the converter (Bx.2).

Comparison unit 11 contains a switch 12, a memory device 13 with an information volume of N one-bit words, the address inputs of which are connected to the outputs of the switch 12. The first group of inputs of the switch 12 is connected to the outputs of the memory block 4, an information volume of N words per word. The control input of the switch 12 is combined with the write input W of the block 13 and, together with the second group of inputs of the switch 12 and the information input D of the block 13, is the second input (Bx2) of the converter

The control unit 7 contains the elements AND 14-16, the clock generator 17, the counter 18 clock decoder 19, the elements AND 20-24, the elements OR NOT 25-27 and the RS-trigger 28.

The stochastic converter works as follows.

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In the initial installation mode, the user supplies 1 to the first input of the converter (Bx1, circuit A). In this case, the counter 18 is reset, the element OR-IS 27 is activated and closes the elements AND 22 and 23, therefore, at the address inputs of the switch. 6, the combination 00 appears, which corresponds to the connection to the address inputs

10A of the block 4 of the memory of the outputs of the counter 5. At the address input A of the switch 3, there is also 1, which determines the connection of the outputs of the counter 5 to the information inputs D of the block 4.

15 Clock pulses from the generator 17 post fall on the clock input of counter 5, which performs sequential counting. The recording pulses of the memory block 4 are received from the generator 17 by the write pulses through the open element 15. Thus, the elements of the set of numbers used are sequentially recorded in the memory block 4. Entering information into the scheme 1 1 about

The 25 placed subset is produced by the consumer via Bx. To do this, the consumer applies to the information input D of the storage device 13 1 if the number that is supplied

30 to the second group of inputs of the switch 12 is allowed, or O 3 otherwise. Synchronously with these signals, the address input A of the switch 12 and the input of the record W of the device 13 are fed 1, which causes the connection of the address inputs of the storage device 13 to Vx.2 and entry into this address of the information at input D. Consistently 40 In essence, the record, the consumer enters into the device 13 an information array of zeroes and ones, and 1 at any address means that the number corresponding to this resolution is allowed, and O means that this number is not included in the subset of allowed numbers.

The initial installation mode ends when the consumer removes

 1 with chain A in. 1, while the device enters the mode of permutations. In this mode, the information inputs of block 4 are permanently connected via switch 3 to the outputs of register 2

55 (because. At address input A of switch 3 is present O). At the output of the element OR NOT 27 there is 1, therefore the element AND 16 otkryts

3

for clock pulses from generator 17. One permutation is performed for 4 clock cycles.

In the zero cycle, the AND 22 element is open, since the inverse output of the OR-NOT 25 element is 1, the AND 23 element is closed, and the combination 01 is located at the address input of the switch 6, which determines the connection to the address inputs of the counter output memory block 4 9. Element 15 is closed, therefore, memory block 4 is in read mode. At the end of the clock, the number read from the counter 9 is written to the register 1 by the clock pulse through the open element AND 16. The element 14 is also open, and the pulse passed through it causes a sample of the next n-digit number in the generator 10 random numbers. The zero clock expires after the binary counter 18 is transmitted by the pulse passing through the element 16 to the state 01, which corresponds to the first clock.

In the first clock cycle, at the first output of the decoder 19, 1 appears, therefore, at the forward output of the OR element 25 there is 1, and at the inverse, O. Through the elements 22 and 23, this combination is transmitted to the address input of the switch 6, which causes a connection to the address The inputs of the memory block 4 of the generator outputs 10 random numbers. The number from block 4 read at this address is written to register 1, and at the same time information from register 1 is written to register 2 (since the recording inputs from registers 1 and 2 are combined).

In the second cycle 1, it appears at the second output of the decoder 19 and arrives at the inputs of the elements OR NONE 25 and 26f, therefore the outputs of the generator 10 are connected to the address inputs of block 4. The information inputs of block 4 are connected via switch 3 to the outputs of register 2. Logical the unit from the direct output of the element OR-NOT 26 enters the input of the element 15, therefore the clock pulse from generator 17 passes to the input of record W of memory block 4 and records the number from register 2 at the address from generator 10 random numbers. At the end of the clock cycle, information from register 1 is rewritten into register 2, and counter 18 is transferred

5 - O -) 5 20 25

Go, 40

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clock pulse to state 11, which corresponds to the third clock cycle.

In the third cycle at the inputs of the element OR NOT 27 there are O, therefore the element AND 22 is open and ale. And 23 is closed, it means that the outputs of counter 9 are connected to the address inputs of block 4. At the third output of decoder 19 there is 1, therefore, the direct output of SH-NOT 26 is also 1, which opens And 15 to pass a write pulse to memory 4. ti. The number from register 2 is written to block 4 at the address from counter 9. At the end of the clock cycle, this counter is transferred from the generator 17 through the open element 20 to the next, its state, 00 appears at the outputs of counter 18 and the next clock begins zero cycle permutations. As a result of a single permutation, the addresses of two numbers written in a block of 4 are changed, and after several permutations in block 4, the set of N numbers used in a random order is written in random order.

The permutation mode continues until a control impulse arrives at the control input (input 1, circuit B). This impulse translates trigger 28 into a single state. If the stochastic transducer is in permutation mode on the second or third cycle, the AND 24 gate is closed with a zero logic level from the inverse output of the OR-NOT 26 element. The permutation mode is not interrupted until the zero or first clock cycle occurs. At the same time, at the inverse output of the element OR-HE 26 there appears 1, which opens the element AND 24, and the device switches to the selection mode

-number belonging to an allowed subset.

In this mode, at the output of the element OR-NE 26, O appears, which locks the elements AND 16, 22 and 23, therefore the pulses from the generator 17 do not pass to the registers 1 and 2, the counter 18 and the generator 10 random numbers, and the address inputs The memory unit 4 is connected to the counter 5. The number counted at the address from this counter goes through the first input of the switch 12 to the address input of the storage device 13, which is also in read mode. If the number received at the address inputs of the device 13 does not belong to the subset of the allowed ones, then at its output there is an O that keeps the AND 21 element in the off state. The clock pulse from the generator 17 is fed to the input of the counter 5, which causes the appearance of the next number at its outputs. This number through the switch 6 arrives at the address input of the memory block 4, and the number read at this address through the switch 2 arrives at the address input for the memory device 13. The described process repeats cyclically until a number belonging to the address 13 arrives at the address input of the device 13. the allowed subset of the whole set of numbers used, which will cause the appearance of 1 at the output of the device 13. The element 21 opens and the clock pulse from the generator 17 passes through it. This pulse goes to the record input C of the output register and 8 is recorded in it. the number from block 4 belonging to the allowed set. The output of the AND 21 element is also connected to the input R of the trigger 28, therefore this trigger is reset, O appears at its output, which closes the AND 24 element, and the stochastic converter switches to the permutation mode. V which continues until the next request arrives.

Claims (1)

Invention Formula A stochastic converter containing an output register whose output is the output of the converter, a memory block whose output is connected to the first input of the comparison circuit, the second input of which is the information input of the converter, and the output of the comparison circuit is connected to the control input of the control unit, the first the second and third outputs of which are connected respectively to the trigger input of the random number generator, recording output register and memory block control, characterized in that, in order to increase the speed It contains the first and second registers of the first and second counters, the first and j tO ts 20 25 h, 5 0 about 5 the second switches, the outputs of the first and second switches are connected respectively to the information and address inputs of the memory unit, the output KOTOpoi o is connected to the information inputs of the output and first registers, the output of the first register is connected to the information input of the second register, the output of which is connected to the first information input of the first switch, the second information input of which is combined with the first information input of the second switch and connected to the output of the first counter, the output of the second counter from dinene with the second information input of the second switch, the third information input of which is connected to the output of the random number generator Hiiix, while the control unit contains a clock pulse generator, clock counter, decoder, RS-trigger.r S from the first to the eighth elements And, the first, second and third. the elements OR NOT, the input of the initial installation of the converter is connected to the reset input of the clock counter, the first inputs of the first and second elements II11 and NOT. the control input of the first switch, the output of the clock generator is connected to the first inputs of the first, second, third and fourth. AND elements and the counting input of the first counter, the output of the second element AND is connected to the recording control inputs of the first and second registers, the first input of the fifth element AND and the counting input of the clock counter, the first and second outputs of which are connected to the first and second inputs of the decoder, respectively, the first , the second, third and fourth outputs of which are connected respectively to the second input of the fifth element I, to the first input of the third element W-NOT, to the second. the inputs of the first and third elements OR NOT, to the third input of the first element OR NOT and the second Bxofi; y of the first element AND whose output is connected to the input of the second counter, the second input of the fourth element AND is the control, the input of the control unit, and the output the fourth element AND is connected to the input of the installation in the RS flip-flop and is the second output of the control unit, the outputs of the fifth and third AND elements are respectively the first and third outputs of control unit 1, the direct and inverse outputs of the first element OR are NOT connected respectively to the second input of the third and the first input of the sixth elements AND, the inverse output of the second element OR NOT connected to the second the second and the first inputs of the seventh and eighth elements are And, the second inputs of the seventh and eighth elements And are connected respectively to the inverse and the direct outputs of the third element SH-NONE, the outputs of the eighth element AND are connected to the first and second control inputs of the second switch, the installation input in R The RS flip-flop is the input of the initial setting of the transformer, and the output of the CB-tri1ter is connected to the second input of the sixth AND element, the output of which is connected to the second input of the second OR-NOT element and the third input of the fourth I. Editor L. Pchelinska Order 3490/44 Circulation 671 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Compiled by E.Sechina Tehred O. Gortvan Proofreader O. Lugov Subscription