SU1282221A1 - Device for checking dynamic memory blocks - Google Patents

Abstract

The invention relates to computing and can be used for the functional control of dynamic operational memory blocks. The aim of the invention is to expand the field of application of the device by providing a measurement of the limiting time for regeneration of information in a controlled memory block. The device contains a pulse generator, the first counter, a decoder, a multiplexer, two triggers, a delay element, three AND elements, a frequency divider, a comparison result register, a comparison unit, a second counter, a single signal conditioner, a reference data setting unit, a measuring range setting unit, a register display unit, display unit and analysis unit of the read information, which contains the control code generator, the reference code setting unit, the comparison unit, the pulse distributor, the display register and the display unit ation. The device provides the control of the memory block in the modes Read units / Write zeroes and Read zeroes / Write units. The measurement of the limiting regeneration time is that at the time when the memory unit is filled with reference information, it is interrupted for a specified period of time, after which the monitoring is resumed, and the control code generated from the memory information is compared with the reference control code. The result of the comparison is used to reduce or increase the time that the control is interrupted. The limiting time of regeneration is defined as the time interval, which, when the control is interrupted, ensures that the read and reference control codes coincide, i.e. in which the integrity of the information in the memory block is not yet violated. A binary record of the measured limit time of regeneration at a certain scale, selected by means of the measuring range setting unit, is recorded from the comparison result register in the display register and indicated by the display unit. 1 hp f-ly, 1 ill. (L to 00 to to

Description

The invention relates to computing and can be used for the functional control of dynamic random access memory blocks and organization with multiplexed address inputs.

The purpose of the invention is to expand the field of application of the device by providing measurement of the limiting time for the regeneration of information in a controlled memory block.

The drawing shows the functional diagrams of the device and analysis unit read information.

The device contains a pulse generator 1, the first counter 2, the decoder 3, the multiplexer 4, the first 5 and the second 6 triggers, delay element 7, elements 8-10 from first to third, switch 11, frequency divider 12, comparison result register 13, second a counter 14, a data register 15, a comparison unit 16, a single signal generator 17, a reference data setting unit 18, a measurement range unit 19, a display unit 20 and a read information analysis unit 21.

The read information analysis unit 2 comprises a reference code setting unit 22, a display unit 23, a comparison unit 24, a control code register 25, a control code generator 26 and a pulse distributor 27. The drawing also shows a controllable memory block 28.

The device works as follows.

In the initial state, the counter 2, the trigger 6, the driver 26, the registers 25 and 15, the block 24 and the counter 14 are in the zero state (no reset circuits are shown). Register 13 is set to state 10 ... O. The generator 1 generates pulses that pass through the element And 8 to the counting input of the counter 2, which

ten

15

Ras. At the second output of the decoder 3, a CAS column resolution signal shifted by a duration equal to one clock cycle is generated. Thus, during each Read command and each Write command, two samples are shifted relative to each other resolution. The address signals are fed to the input of block 28 from counter 2 through multiplexer 4, which multiplexes two halves of address signals in time successively, the lower bits of the addresses are transmitted from the outputs of the first group of counter 2 through multiplexer 4 to the address inputs of the monitored block 28 with a zero signal at the address input multiplexer 4, and the high bits - with a single value at the output of trigger 5 from the outputs of the second group of counter 2. Trigger 5 after completion of the operation Read or 25 The record is set to zero e, while at the output of multiplexer 4, lower address bits are set, which are received by the front of the RAS signal of the next operation. At the same time, element 7 is launched by the same front, which sets trigger 5 to one state, which ensures transmission of 4 high-order address bits to the output of the multiplexer before the appearance of a certain signal.

20

thirty

35

The outputs of the third group of counter 2 stimulate To the data inputs of the block 28, and the last of these outputs

40 of counter 2 controls the most senior () th data input of block 28 so that the first half of the total monitoring time for one-bit blocks 28 is read into units and zeros are written,

45 and the second half of the total time — zeros are read and units are sequentially entered at all addresses, the Marsh D test is performed for multi-digit blocks 28 besides the modes. It runs in the continuous zero-0 unit / 3-letter zeros and Read mode.

zeros / Write units For each of the bits, there are redundant modes Reading zeros / Writing zeros and Reading units / Writing ones. Data on redundancy when using the convolution of information is insignificant.

The use of block 21 provides the ability to control block 28 not only during the reading, Va,

accounts. In the decoder code 3, the following one is generated. For the other, signals of duration each cycle (.period) of the clock signal having a zero value And element 10 generates a double signal having a zero value and used as a row-selection signal.

five

Ras. At the second output of the decoder 3, the sample resolution signal of the CAS column is shifted by a duration equal to one clock cycle of the sync signal. Thus, during each Read command and each Write command, two samples are shifted relative to each other resolution. The address signals are fed to the input of block 28 from counter 2 through multiplexer 4, which multiplexes two halves of address signals in time successively, the lower bits of the addresses are transmitted from the outputs of the first group of counter 2 through multiplexer 4 to the address inputs of the monitored block 28 with a zero signal at the address input multiplexer 4, and the high-order bits - with a single value at the output of trigger 5 from the outputs of the second group of counter 2. Trigger 5 after completion of the operation Read or 5 The record is set to zero , Wherein the output multiplexer 4 are set lower address bits, which are received edge signal RAS next operation. At the same time, element 7 is launched by the same front, which sets trigger 5 to one state, which ensures transmission of 4 high-order address bits to the output of the multiplexer before the appearance of a certain signal.

0

0

five

The outputs of the third group of counter 2 stimulate To the data inputs of the block 28, and the last of these outputs

40 of counter 2 controls the most senior () th data input of block 28 so that the first half of the total monitoring time for one-bit blocks 28 is read into units and zeros are written,

45 and the second half of the total time — zeros are read and the units are written sequentially at all addresses, implement the Marsh D test for multi-bit blocks 28, in addition to the Read modes,

what is especially significant, and in all possible conditions, namely, with the ban of the Reading, with the ban of the Record, with the permission of the Record. This is due to the fact that the reception of read data from block 28 to block 21 is performed for each clock signal of generator 1. Therefore, for eight clock cycles characteristic of each address, the output information is received when the Read is disabled, when the Record is disabled, when the Record is disabled .

Each sync signal from the last output of the third group of the counter, 2 corresponds to one control cycle of block 28, through which all possible data layers are sequentially read and written in succession at all addresses. At the same time, the input of the imager 26 receives a signal from one of the outputs of the monitored block 28. When the next input signal from the high bit output of the counter 2 arrives at the control input of the block 21, the next output of the block 28 is connected. When all the outputs of the block 28 are sequentially checked, The bit of the imager 26 on the control of the input of the distributor 27 is given a start / stop signal. At the same time, the operation of the distributor 27 is allowed for four cycles and it is the first four impulses from the output of the element 8 and alternately outputs signals at its four outputs that ensure the sequential implementation of the following functions: writing to the register 25 of the generator 26, comparison in the block 24 of the register contents 25, the obtained control code and the contents of the block 22, which serves to set the reference control code, zeroing the gating driver 26 j. writing the comparison result from block 24 to register 13.

The received control code is indicated by block 23 and at the same time the same block indicates uncorrection of the control code formed from the read information with the reference one from the output of block 24.

The essence of the measurement of the limiting time of regeneration is that at a certain point in time when the storage array of the block 28 is filled with well-defined information

25

5 Yu

15 20 30 35 40 45

50

55

nation, the block 28 interrupts for a predetermined period of time, after which the control is resumed from the same place where it was interrupted. The resulting control code is compared with the reference code and the result of the comparison is used for cor-. Reactions of time for which the control is interrupted. After repeatedly performing the described operations, the final pregloganization time thus adjusted is the limiting regeneration time, i.e. time, which, when interrupting the test, still ensures that the read control code coincides with the reference one, but when it is increased (within the specified measurement accuracy), the control code ceases to coincide with the reference one, i.e. the integrity of information in block 28 is violated.

Block 18 is used to select slot data, when filled with an array in block 28, measurement of the limiting regeneration time is performed. Divider 12 together with block 19 sets the measurement range.

The measurement of the limiting regeneration time is carried out as follows. Until the higher bits of the counter reach 2, the value specified by block 18, the device operates as described above. When these values coincide, when the storage array of block 28 is filled with the selected data word, a negative signal is output at the output of block 16, which starts the shaper 17, which sets trigger 6 into one state. The zero potential from the inverted output of the trigger 6 closes the element AND 8 and the arrival of the clock signals to the counter 2 and the driver 26 stop c. As a result, all signals to the monitored block 28 stop. At the same time, the leading edge of the same pulse from the generator 17 records the contents of the register 13 (for example, code 10 ... 0) into the counter 14. With the unit potential from the direct output, trigger 6 opens element 9. and pulses from the output of the generator 1 are fed through a divider 12 to the input of the subtraction of the counter 14. When the counter 14 passes through a zero value

5128222

at its overflow output, a signal is detected that sets trigger 6 to the zero state. By;

setting pulses on counter 2 and

the driver 26 is resumed, and 5 to the subtracting input of the counter 14 is stopped. At the same time, control of unit 28 is resumed from the same state in which it was interrupted.

At the end of the monitoring process Ш (the first measurement window), the next bit of information from the output of block 24 is written to the register 13 from the fourth output of the distributor 27, depending on 15 whether the received control code matches the reference code from the output 24. .In a mismatch, a logical O signal is generated, and if it does coincide, a logical one is generated. The next value is 20

the code in register 13 will be 110 ... O (if it coincides in block 24) and 010 ... O - if there is a mismatch. Further, in the next measurement window, the described operations are repeated with interrupt time 25 corresponding to the specified code. After repeated repetitions, the number of repetitions being equal to the register size 13, the latter generates an overflow signal, according to which 30 records the contents of register 13 to register 15. This value is a binary record of the measured limit time of the regenerator in May. - 35 to headquarters selected by block 19, which is indicated by block 20.

Claims (2)

1. A device for monitoring dynamic memory blocks, comprising a pulse generator, a first counter, a decoder, a multiplexer, triggers, a delay element, AND elements, a switch and a read information analysis unit, the output of the pulse generator connected to the first inputs of the first and second AND elements, the output of the first element I is connected to the synchronous input of the block of analysis of the read information and the counting input of the first counter, the first and second outputs of which are connected to the inputs of the decoder, the first output of which is connected to the first input Ohm of the third element And the input of the delay element, the output of which is connected to the input of the installation 50 5 0 5 0 0 sixteen 1 of the first trigger, whose information input is connected to the zero potential bus, and the synchronization input is connected to the second output of the decoder, the second input of the third And element and the first input of the switch, the second and third inputs of which are connected to the output of the third And element and the third output of the first counter, outputs the first and second groups of which are connected to the information inputs of the multiplexer, the outputs of which are connected to the inputs of the first group of the switch, the inputs of the second group of which are connected to the outputs of the third group of the first The output of the first trigger is connected to the address input of the multiplexer, the inverse output of the second trigger is connected to the second input of the first And element, one of the switch outputs is connected to the control input of the read information analysis block, the information inputs of which are the inputs of the device whose outputs are others switch outputs, that is, due to the fact that, in order to expand the scope of application by providing measurement of the limiting time for regeneration of information in a monitored memory block, Frequency divider, reference data setting unit, measurement range setting unit, comparison result register, second counter, data register, display unit, single signal shaper and comparison unit, whose inputs are connected to the outputs of the reference data unit and the third group of the first counter, are provided The output of the comparison cell is connected to the input of a single pulse shaper, the output of which is connected to the single input of the second trigger and to the control input of the second counter, information Its inputs and data register inputs are connected to one of the outputs of the comparison result register, the other output of which is connected to the control input of the data register, the outputs of which are connected to the inputs of the display unit, the input of the second counter reading is connected to the output of the frequency divider, control inputs which is connected to the outputs of the block set the measurement range, the input of the frequency divider sub71 the keys to the output of the second element I, the second input of which is connected to the direct output of the second trigger, the zero input of which is connected to the overflow output of the second counter, the information input and the synchronization input of the comparison result register are connected respectively to the first and second outputs of the read information analysis block. 2. The device according to claim 1, wherein the read information analysis block comprises a check code generator, a check code register, a display block, a comparison block, a reference code setting block and a pulse distributor, the first and second outputs of which are connected respectively to the control register entries ten 282221. eight code and the comparison unit, the output and one of the inputs of which are connected respectively to the control input of the display unit and the outputs of the reference data set, the other inputs of the comparison unit and the inputs of the display unit are connected to the outputs of the control code register, whose inputs are connected to the outputs of the pilot code generator, the reset input and the control output of which are connected to the third output and the control input of the pulse distributor, the output of the comparison unit and the fourth output of the pulse distributor are the first and second vpsrdami unit, which are clock terminal the clock distributor J pulse shaper and the control code, the control input of which is a control input unit. 15 20