SU1275413A1 - Device for generating codes with given weight - Google Patents

Abstract

The invention relates to computing. Use in: data transmission systems with redundant coding allows to expand the functionality of the device by automating the formation of quasi-cyclic codes of a given length and mass. It contains two counters, a shift register and a control unit. Due to the introduction of two master blocks, a switch, a gate And, a gate of comparison, masking of unused bits and a block of RAM, it automatically generates all circuits with the specified parameters. 2 hp f-ly, 6 ill.

Description

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The invention relates to computing and can be used in data transmission systems with redundant coding.

The purpose of the invention is to expand the functionality by automating the formation of quasi-cyclic codes of a given length and weight.

FIG. 1 is a block diagram of the deviceJ in FIG. 2 is a functional block diagram of the mask for unused bits in FIG. 3 is a functional block diagram of the control unit; FIG. 4 shows the time diagrams of the operation of the device for the case when the weight of the next code does not correspond to the specified BecyJ in FIG. 5, time diagrams for the case when the next code is the result of a cyclic shift of one of the previously tested codes in FIG. 6, the same when the weight of the next code corresponds to a given weight.

The device for generating codes of a given weight contains the first counter 1, the shift register 2, the unused bits masking unit 3, the RAM block 4, the first master block 5, the switch 6, the second master block 7, the reference element 3, the second counter 9, And 10 , control unit 11, informational 4a and control outputs 12 and 13

The masking unit 3, the unused bits (Fig. 2), includes N - 1 elements OR 14, N elements AND 15 and a decoder 16, where N is the longest generated code length.

The RAM unit 4 is a random access memory with a capacity of 2 single-bit cells. It is designed in such a way that after powering up all its cells contain, Yugic O after the arrival of the logical G signal at the write input, the contents of the cell corresponding to the incoming code arriving at the address input, takes the value of logical 1, and when it is at the recording input of the logical O signal, corresponding cell enters the output unit 4. In particular, the block 4 of the RAM can be executed on the microchips (the information input of each of the microcircuits must be connected to the source Coy 1).

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The driver blocks 5 and 7 can be executed, for example, as a set of toggle switches, a normally open contact of each of which is connected to a signal source of logical 1, a normally closed contact to a signal source of a logical O, and a switchable contact to the corresponding output of the block.

The control unit 11 (FIG. 3) includes a clock pulse generator 17, a HE element 18, first and second counters 19 and 20, a decoder 21, first and second triggers 22 and 23, and elements 24-29 from one to six, element AND-NOT 30, elements OR 31-33 first to third, elements 34-38 delays from the first to fifth.

The principle of operation of the device is based on the fact that all possible binary codes of a given length n from O (i.e., 0 ... 0) to 2-1 (i.e.1 ... 1) are alternately generated in the first counter 1. For each successive code, according to the information accumulated by this time in block 4 of the operating memory, it is first checked that it does not coincide with the cyclic signal of one of the previously tested combinations. If this is indeed the case, the verification of this code is stopped and the first counter 1 generates the following binary code, this allows shortening the duration of the verification. If the checked binary code is not a shift of one short-circuit of the previously checked codes, then using the shift register 2, block 5 specifying the code length, the switch

6, element And 10, the second counter 9u counting the weight of the code block

7, which specifies the weight, and the comparison element 10, its weight is checked. If the code being tested corresponds to a given weight, i.e. is one of the required circuits, it enters the information outputs 12 of the device simultaneously with the Strobe code signal at the control output 13. Thereafter, at the outputs 12, n - 1 quasi-cyclic codes are formed, which are cyclic shifts of the circulatory found, and Once in the control unit 11, a Strobe code signal is generated, and for each of them, in the operating memory block 4, the sign of the already verified code is stored. Thereafter, the following binary code is generated and verified in the device. If, as a result of checking the weight of the next binary code, the discrepancy to the specified weight is found, then for him and dp n - 1 codes that are cyclic shifts, in block 4 of the operating memory, the codes of the previously checked codes are remembered. Thus, by the end of checking all the kodos of a given length in the block 4 of the RAM, the signs of the previously checked codes will not be remembered. Thus, by the end of checking all the codes of a given length in the operative memory block 4, the signs of the previously checked codes will not be filled only for those codes that are circuits of quasicyclic codes of a given weight, and all the quasicyclic codes of a given weight will arrive at the outputs 12 the device is accompanied by a Strobe code signal from output 13. In FIG. 4-6, illustrating the operation of the device, are designated: q - clock pulses at the generator output 17 & same pulses at the output of delay element 34 E - state code at the outputs of the first counter 19j t - code increment signal from the first output of the decoder 21 - write signal to register 2. the shift from the second output of the decoder 21-e is the signal to write to counter 20 from the output of the element OR 32 g - the signal from the output of the element OR 33 that the counter 20 is not empty h, - Sigal Demand of the discharge code from the output of the element AND 27 j U - code shift signal in register 2 from the output of delay element 37, k - signal from the output of comparison element 8 that the code weight is equal to the specified L - signal from the output of the first trigger 22, M is the sign write signal in the block. 4 RAM from the output of the element And 28, H-signal A sign of the previously verified code from the output of the block 4 of the operational memory; о - strobe code on control you running 13 J 134 h - signal from the output of the second trigger 23. The device operates as follows. In the initial state (after power up), the first counter 1, block 4 of the RAM, and in block 11 of the control, the counter 19 and the triggers 22 and 23 are cleared (contain zeros in all digits and cells of the memory). From the output of block 5 to the second inputs of control block 11 and to the control inputs of block 3 for masking unused bits and switch 6, a parallel code of a given length of code combinations is received. From the output of block 7, a parallel code of a given weight of code combinations arrives at the second inputs of the comparison element 8. From the first output of the control unit 11, the code increment signal (Fig. 4d) is sent to the counting input of the first counter 1, and the content code of the counter 1, which is the next checked combination, is increased by 1 (in particular, at the beginning of operation of the device code 00. ..00 is replaced with the code 00 ... 01). With some delay relative to this signal, necessary for the termination of transients in the first counter 1, the second output of control unit 11 generates a signal to write to the shift register, which arrives on zero zero of the second counter 9 and to the input of the shift register 2. At the same time, the code of the next checked combination, arriving at the first information inputs of the shift register 2, is written to this register 2 and from its outputs through the block 3 enters the address inputs of the RAM 4. At the start of operation of the device, when checking the code combination 00 ... 01, the RAM block 4 contains all zeros in all cells, therefore its signal, the Sign of the previously checked code, arriving at the first input of the control unit 11, will have a logic level O (the value of this signal corresponds to the contents of that cell block 4 RAM, whose address is equal to the code at the address input of the same block). As a result, with some delay, sufficient for the termination of transients when writing a parallel code in the shift register 2 and

reading the contents of the RAM block 4, the device begins to determine the weight of the code being tested in order to verify its compliance with the specified value. In this case, the control unit 11 at its third and fourth outputs generates a burst of n pulses of the Oyros code-discharge signal (Fig. 4) and a burst of n pulses of the Shift-code signal (Fig. 4i). The number of pulses in each of these packs corresponds to the code of a given combination length, which arrives at the second inputs of the control unit 11 from the length setting unit 5. During the formation of a packet of pulses of a signal Code shift, switch 6, together with the N-bit shift register 2, provides a digital shift of the contents of the lower half bits of this register (the contents of the high N — n its bits are determined by the contents of the n-th bit preceding N — n shift pulses, which does not affect the operation of the device as a whole). To ensure the cyclic shift of the lower n bits of the register 2 shift, the output of its bit n through the switch 6, controlled by a code of a given length n (coming from the length setting unit 5), is connected to the second (serial) input of the same register 2. As a result this, for example, for a given length of code n 3 and verifiable combination 0 ... 0001 after each,: next signal Shift code (the total number of which will be 3) the contents of shift register 2 will accordingly take the values:

0 ... 00110 0 ... 01101 0 ... 11011,

.four

which corresponds to cyclic

the shift of the lower 3 bits of the combination (the numbering of the bits in the above entry is from right to left).

When determining the weight of the code being tested, the signal from the output of the switch 6 is fed to the first input of the And 10 element. The second input of this element 10 receives the Poll of the code discharge signal (Fig. 4j). If the current value of the nth digit of the code being checked is equal to logical 1, then from the output of the AND 10 element to the counting input of counter 9 a pulse arrives, increasing the contents of the counter by one. Since the total number of pulses of the signal Poll of the code discharge is equal to n and after each of these pulses (with a delay sufficient for reliable formation of a pulse at the output of the And 10 element), control unit 11 generates the next pulse of the Code Shift signal (Fig. 4o), pulses on the counting input of the counter 9 during this time will be equal to the number of bits of the combination being tested, the value of which is equal to logical 1, i.e. her weight. This same number will correspond after the completion of the formation of all n pulses of the signal. Interrogation of the code discharge and the code at the outputs of the counter 9, arriving at the first inputs of the comparison element 8. The second inputs of this element 8 receive the setpoint weight code from the output of block 7. In the case of equality of codes on both inputs of the comparison element 8, the Weight signal is equal to the specified (Fig. 4k) generated at its output and fed to the third input of control unit 11, takes the value of logical 1, otherwise the logical O. The value of this signal after the end of the formation of bursts of signals Interrogate code bit and code shift and determines the further operation of the device. If the value of this signal is O, i.e. if the weight of the combination being tested turned out to be unequal to the specified one, the device then writes the sign of the previously verified code in all the cells of the 4th RAM memory whose addresses are equal to the cyclic, shifts of the combination being tested or to it itself. When this device operates as follows. After completing the check of the combination weight, from the outputs of the masking unit 3 of the unused bits, a code equal to the code of the initial checked combination is sent to the target input of the main memory unit 4. In particular, in the example considered above, this code will be equal to 0 ... 00011 (although the code of the contents of the shift register will be equal to 0. .. 1 1 О 1), the values of the higher N-and-bits of this code will always be equal to 0.

Then, from the fifth output of the control unit 11, the first pulse of the signal is written to the input of the recording of block 4 of the operational memory. A sign (Fig. 4m) is recorded and logical 1 is written in the cell with the corresponding address (equal in the considered case 0 ... 00011). After a period of time sufficient to record the feature, the shift of the code shift signal will return to the shift control input of the shift register 2 (Fig. 4i). In this case, similarly to what has been described, a cyclical shift of the code being tested and masking of unused bits of the code arriving at the address input of the main memory unit 4 will be performed, and after completion of the transient processes, the next input signal signal will be sent to the recording input of the same block. In the described sequence, a block 11 controls on the Fifth and Fourth outputs will form a stack of n signal pulses. Record the feature and the code-shift signal. At the same time, for the above specific code of the combination being tested, the feature of the previously verified code will be written in the cell with the addresses 0 ... 0011, 0 ... 011 and 0 ... 0101. If, however, the combination 0 ... 000 was checked (as it takes place at the first time after the device starts working) and after the weight check is completed, the signal Weight of the code equal to the given value takes a zero value, then for the particular case considered, the 3 sign of the previously checked The code will be written into the cells of block 4 of the RAM with addresses 0 ... ... 0001, 0 ... 0010 and 0 ... 0100. After the characteristic is written in the cells of the memory block 4, the actions associated with the next checked combination are terminated, and from the first output of the control unit 11, the code increment signal is received again at the counting input of the first counter 1 (Fig. 4d) The following code combination is formed and the device performs its verification. The verification of the next code combination is significantly reduced in time if it is a cyclic shift of one of the previously tested combinations. This is the case for the considered example, when following the combination check 13 days O ... OOtO after generating signals, the code increment and zspis in the shift register (fig. 4) after a period of time sufficient for the next combination code (0 ... 0010) to be sent to the address the input of the RAM block 4 and the read operation from the corresponding cell; from the output of this block 4, the first input of the control block 11 will receive a signal Sign of a previously verified code (Fig. 5H) with a logic level of 1, - the definable value of the sign previously recorded in this cell. In this case, a further check of the weight of the next combination is not performed, and the device proceeds to form and check the following code combination — from the first output of the control unit 11. The increment signal of the code returns to the counting input of the first counter 1 (Fig. 52). If the combination turns out to be the required circulator, the device operates when it is checked in the same way as described until the formation of the first bursts of n pulses of signals is completed. Interrogating the code bit and Shifting the code (Fig. b). After polling the last zero bit of the code (i.e., after the arrival of the signal corresponding to the pulse pulse Poll of the code bit (Fig. B) to the second input, element 10), the code in the counter 9 arriving at the first inputs of the comparison element 8 appears equal to the code of a given weight, coming from the output of block 7 to the second inputs of the same reference element 8. As a consequence, from the output of element 8 to the third input of control unit 11, the signal Weight arrives equal to the set value (Fig. 6k), the unit value of which is preserved in the considered case even after the formation of the first batch of code shift pulses is completed. In this case, during the formation of the second bundle of n signal pulses Polling the code discharge simultaneously with each of them, the sixth output of the control unit 11, which is simultaneously and the control output 13 of the device, will generate a pulse of the Strobe code (Fig. 6o), Signal pulses Sign Record (Fig. 6m) will be generated at the fifth output.

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of the same block 11 simultaneously with the second and subsequent pulses of the same second batch of signal pulses Poll code discharge. Since the first impulse of the second packet of this signal is formed after all n cyclic shifts have been completed, then at the moment of its formation the code of the next checked combination (i.e., a circular circulator) is present at the outputs 12 of the device, therefore the recording of the sign into the cell with the corresponding circulating signal This address will not be executed. During the remaining n - 1 signal pulses. Recording a prize on the device outputs 12 successively receives n - 1 quasi-cyclic codes generated by the newly found circulator, and each of them is recorded in the operating memory unit 4 of a previously verified code. After the formation of the second bursts of n interrogation signal pulses and a shift, the device proceeds to normalize and check the next code pattern, and so on until the combination 1 ... 1111 is checked. Thus, during the operation of the device, a pulse of the code strobe signal appears at its control output 13, with the first pulse of each of the packs corresponding to the presence of a new circulation at the outputs 12 with a given weight, and the remaining n - 1 pulses are simultaneously generated with the formation at outputs of 12 quasi-cyclic codes generated by this circulator. In addition, after finishing the operation of the device, from the .2 - 1 junior at the address of the cells of the RAM 4 (except cell 0 ... 0000) will contain logical О only those cells whose address codes are equal to the circuits detected during the test. Thus, the formation and memorization of all possible circulations for a given length and weight of the code of the circulation code as well as the automatic formation of all the quasi-cyclic codes generated by them are provided.

The control unit 11 during the operation of the device operates as follows. After power is turned on, counters 19 and 20, as well as triggers 22 and 23, are in the zero state. In this case, all the inputs of the element

ten

13

Claims (3)

OR 33, the corresponding bit outputs of counter 20 receive low level signals, as a result of which the output of this element 33 also forms a low logic level of the signal. The shift counter is not empty (Fig. 4g). Due to this, a high potential is supplied to the second inputs of the first and second elements AND 24 and 25 from the output of the element HE 18 through the third delay element 36. The first clock pulse (Fig. 4a), arriving at the first input of the first element And 24, will cause the formation of a pulse at the counting input of counter 19, and the code 001 will go to the input of the decoder 21. Due to this, at the time of arrival of the first delayed clock pulse from the output of the first element 34 delay through the second element And 25 to the synchronization input of the decoder 21 at its first output, which is 1c and the first output of the control unit 11, a pulse is generated in the signal of the code increment. With the arrival of the next clock pulse, the status code (the contents of counter 19) will become 010, so that simultaneously with the second pulse of the delayed clock pulses (Fig. 4S), the second output of the decoder 21, which is the second output of the control unit 11, will generate a pulse Write to shift register If after this, the second input of the third element And 26, which is simultaneously the first input of the control unit 11, receives a high signal level Sign of the previously verified code (Fig. 5i), the further operation of the block is as follows. After passing the third clock pulse through the first element AND 24 to the counting input of the counter 19, the status code takes the value 011. The delayed clock pulse from the output of the first delay element 34 passes through the second element AND 25 to the synchronization input of the decoder 21, so that the third output of the same decoder 21 pulse occurs. Since the second input of the third element And 26 at this point in time has a high signal level, a Sign of a previously verified code, a pulse also appears at its output, which passed; through the first element n OR 31 and the second delay element 35 arrives at the reset input of the counter 19 and sets it back to its original state. Due to this, the operation of the control unit 11 will resume later, starting with the formation of the Sign Code function. In the case of operation of the device, when after the formation of a signal, a high signal level is not received at the second input of the third element 26, the signal of the previously verified code is not generated and the pulse at the output of the same element 2 during the third state of the 19 state counter. Therefore, the counter 19 in the arrival time of the fourth clock pulse goes into the fourth state 100, and after the next delayed clock pulse has been formed, a pulse appears at the fourth output of the decoder 21, which passed through The second element, OR 32, will go to the recording control input of the counter 20 as a signal Record in the shift counter (Fig. 4e). In this case, a predetermined length of combinations arriving at the parallel information input of counter 20 will be recorded into this counter. At the same time, the nonzero bits of the code written to the counter 20 come from its bit outputs to the corresponding inputs of the third element OR 33 and a high signal level will appear at the output of the last counter. The shift counter is not empty (Fig. 4g). Owing to this, at the second input of the fourth element, And 27 allows for Wits, and at the second inputs of the first and second elements. And 24, 25 - prohibiting (low) signal levels. In this connection, over the next periods of clock pulses, no new signals were received at the inputs of the counter 10 and the decoder 21; will be During this time interval at the time of the appearance of clock pulses at the first input of the fourth element. And 27 on the output of the same element, which is simultaneously the third output of the control unit 11, a bundle of n signal pulses will be generated. Since the input of the fourth delay element 37 is connected to the output of the fourth element AND 27, the output of the latter, which is also the fourth 1312 b1.1X (.) House of the control unit 11, will form a bundle of code shift signal pulses. Since the triggers 22 and 23 during this period of time are in the initial states (which correspond to low levels of signals from their outputs), the Code Strobe and Record of Signals from the outputs of the And 28 and 29 elements will not be generated. Each of the pulses of the code shift signal, coming from the output of the fourth element 37 to the input of the subtraction of the counter 20, reduces the content of the latter by one. After n such pulses in the counter 20, the code 0 ... 0 will appear and the signal at the output of the third element OR 33 will again take on the value of logical O. Due to this, the prohibiting signal level occurs at the second input of the fourth element And 27 (which leads to the cessation of the formation of pulse signals) , and after a certain period of time at the second inputs of the first and second elements, And 24 and 25, the resolution of the signal level occurs. Thus, when forming the next clock pulse, the counter (9 goes into the next - fifth state (101). When forming the next delayed clock pulse at the fifth output of the decoder 21, a pulse occurs, which, having passed through the second element OR 32, causes re-formation signal Record in the shift counter. In addition, the same pulse arrives at the input of the trigger 23 and the synchronization input of the trigger 22. The further operation of the control block 11 is determined by the signal level Weight equal to the specified this moment of time to the input of the fifth delay element 38, which is simultaneously the third input of this block. If after the end of the first batch of n pulses, the signal 0) code for the discharge of the code, the weight signal is equal to the specified level of logic O (Fig. 4k) then the signal at the output of the trigger 22 will also have the same level after the impulse synchronization arrives at its input from the fifth output of the decoder 21. In connection with this, the second input of the sixth element I 29 will be denied, and the second input p the element And 28.- authorizing level signal la Due to this, simultaneously with the n pulses of the second burst of the signal, the interrogation of the code discharge, generated similarly to that described, at the output of the fifth element And 28, which is the fifth output of the control unit 11, will form the five pulses of the Signal signal. If, after the termination of the first batch of n signal pulses, the interrogation of the code discharge, the signal Weight is equal to the preset will have a logic level 1 (FIG. Bk), then from this moment the control unit M will function as follows. At the moment of formation of a pulse at the fifth output of the decoder 21, the flip-flops 22 and 23 are set to one (corresponding to a high level of signals at their outputs). As a consequence, the output level of the element IS-NOT 30 will have a logic level of O. Therefore, simultaneously with the first pulse of the second packet of a signal, a code pulse survey of the signal will not be recorded. A sign will not be generated. Then, the first pulse of the second packet of the Shift Code signal, arriving at the input of zeroing trigger 23, will set it to the initial state (Fig. 6p) and allow the signal level at the second input of the fifth element 11 and 28. Therefore, a singleJHieHHO with the following n -. 1 pulses of the second burst of a signal Interrogation of a code discharge will be generated n - 1 pulses of a signal Record sign A due to the presence of a logic level 1 signal at the second input of the sixth element AND 29 simultaneously with each of the pulses of the second signal burst Poll of the discharge of the code at the output of the sixth element And 29, which is the pole output of the control unit 11, a pulse of the Stro code signal will be formed (Fig. 6o). After the formation of the second bursts of interrogation signals and the shift in the counter 20, a code 0 ... 0 is formed, the second potential and the second inputs 24 and 25 turn into the sixth state 110 and the sixth output A decoder 21 forms a pulse, which, having passed through the first element S1I 31 and the second element 35 a delay, enters the 1 1314 zeroing inputs of the counter 19 of the trigger 22, setting them to their original state. After that, the operation of the control unit 11 is resumed, starting with the first state of the counter 19u and proceeds in one of the three described modes. Block 3 masking unused bits works as follows. The inputs of the decoder 16, which are the control inputs of the block, receive a code of a given length p. At that, logic level 1 appears from the N outputs of the decoder 16, the number of which corresponds to n, and as a result, the first input of the corresponding element 15 also enters logic level 1. At the same time, the same signal with a logic level 1 will go to the second input of that element OR 14, whose number is one less. In this case, a signal with a logic level 1 from the output of this element will arrive at f the second input of the element OR 14 and the first input of the element AND 15, the number of which is respectively 1 and 1 less. From the output of this element OR 14, the logical 1 level will go to the second input of the previous one and so on up to the first element OR 14. Thus, at the first inputs of those AND 15 elements, the second inputs are connected to the information inputs of block 3 from the first to the fifth, there will always be a resolving potential level, and at the first inputs of the remaining elements And 15 there will be a logical zero level. As a result, at the outputs of block 3 from the first to the fifth, the values of the same-named bits of the information input of block 3 will be transmitted, and logical unsets will be sent to the unused high bits. This is what allows recording (and subsequent reading) of signs of a previously verified code only into those cells of the device’s 4 RAM, whose addresses fall in the interval from O to 2 - 1, regardless of the contents of the unused higher N - n bits of the register 2 shifts. Thus, the device allows to automatically generate all possible circulations with specified parameters. 15 Claim 1. A device for generating codes of a given weight, containing first and second counters, a shift register and a control unit, that is, that in order to expand functionality by automating the formation of quasi-cyclic codes of a given length and weight, The first and second master blocks, the switch element I, the comparison element, the masking block of unused bits and the memory block, the output of which is connected to the first input of the control unit, the first output of which The computer has a counting input for the first counter, the bit outputs of which are connected to the corresponding first information inputs of the shift register, the recording control input of which is combined with the zero input of the second counter and connected to the second output of the control unit, the second inputs of which are combined with the corresponding control inputs of the masking block of the unused bits and the switch and connected to the corresponding outputs of the first master block, the outputs of the shift register bits are connected to the corresponding information the ion inputs of the masking block of unused bits and the switch, the output of which is connected to the second information input of the shift register and the first input of the element I, the output of which is connected to the counting input of the second counter, and the second input connected to the third output of the control unit, the fourth output of which is connected to the input control of the shift register, the outputs of the masking unit of unused bits, which are the information outputs of the device, are connected to the corresponding address inputs of the operational unit the am, whose recording input is connected to the fifth output of the control unit, the outputs of the second counter and the master unit are connected respectively to the first and second inputs of the reference element, the output of which is connected to the third input of the control unit, the sixth output of which is the control output devices. 2. A device according to claim 1, characterized in that the masking unit of unused bits is made on N - 1 OR elements, N And elements and the decoder, whose inputs are control (they are the inputs of the masking block of unused bits, and the outputs, except N-ro, connected to the inputs of the corresponding OR elements, the output of the first of which is connected to the first input of the first element AND, the output of each of the remaining OR elements is connected to the first input of the corresponding element AND and the second input of the previous element OR, the Nth output of the decoder To the second input of the (N - 1) th OR element and the first input of the N th AND element, the second inputs and outputs of all AND elements are the corresponding information inputs and outputs of the masking block of unused bits, N being the longest generated codes. 3. The device according to claim 1, characterized in that the control unit is executed on the first and second counters, decoder, first and second triggers, AND elements from the first to the sixth, first, second and third elements of the 1SH, element NOT, the AND-NOT element first to fifth delay elements and a clock pulse generator, the output of which is connected to the first inputs of the first and fourth elements And, and through the first delay element to the first input of the second element And whose output is connected to the synchronizer input of the decoder, the first and second outputs of which are the corresponding outputs of the control unit, the third output of the cipher-ora is connected to the first input of the third element AND, the second input of which is the first input of the control unit, and the output is connected to the first input of the first OR element, the output of which is through the second delay element the first trigger and the first counter, the counting inlet of which is connected to the output of the first element I, and the outputs are connected to the information inputs of the decoder, the fourth output of which is connected to the first input of the second element and OR, fifth decoder output coupled to a second input of the second OR gate, the inputs of the first synchronizing flip-flop and the input setting unit in the second latch. the sixth output of the decoder is connected to the second input of the first SHW element, the output of the second OR element is connected to the write control input of the second counter, the information inputs of which are the second inputs of the control unit,. the outputs of the second counter are connected to the inputs of the third OR element, the output of which is connected through a serially connected element NOT and a third delay element to the second inputs of the first and second AND elements and directly to the second input of the fourth AND element whose output, which is the third output of the control unit, connected to the first inputs of the fifth and sixth elements And and the input of the fourth element of the terminal, the output of which is the fourth output of the control unit, is connected to the input of the second counter and the input setting to zero the second flip-flop, the direct output of which is connected to the first input of the NAND element, the output of which is connected to the second input of the fifth AND element, the output of which is the fifth output of the control unit, the third input of the control unit through the fifth delay element to the information input. the first trigger, the direct output of which is connected to the second inputs of the NAND element and the sixth AND element, the output of which is the sixth output of the control unit. Kj rvl 12 : Nlj FIG. one