SU1196897A1 - Device for forming ordinal statistics - Google Patents

Abstract

A DEVICE FOR THE FORMATION OF ORDER STATISTICS, containing the first and second registers, the first element OR, the elements AND, characterized in that, in order to expand the functionality by forming a sample of a given volume, multiplexers, a counter, a control unit, a group of registers are introduced into it. the third register, the block of the largest number, the second element OR, and the control unit contains a clock pulse generator, AND elements, delay elements, counter, trigger, first inputs of the first and second AND elements the control unit is combined and connected to the output of the clock generator, the second input of the first element I of the control unit is connected to the output of the trigger of the control unit, the zero input of which is combined with the input of the first delay element of the control unit and connected to the output of the third element I of the control unit, the first input to the cheap combined with the first input of the fourth element And the control unit and connected to the output of the counter of the control unit, the counting input of which is combined with the input of the second delay element and connected the output of the first element And the control unit, the second input of the third element And the control unit is connected to the supra third element of the delay, the input of which is combined with the second input of the fourth element And the control unit and connected to the overflow output of the first counter, the output of the fourth element And the control unit is connected to the counting input the first counter and the first input of the first element, OR, the output of the first ko delay element is connected to the information and control inputs of the first multiplexer, the single input trigger the control unit is combined with the reset inputs of the first counter and the first register, the second input of the first element OR, the first input of the first element AND, the clock; about 05 input of the second register and connected to the output of the second element SH, H) the second element AND of the control: connected to the counting input of the second counter, the second input of the second element And the control unit is combined with the third input of the first element And the control unit and connected to the overflow output of the second counter, the output of the second delay element is connected to acts input of the first register and via a fourth delay element to the clock input of the first register group, clock inputs of the N-1 group of registers are combined with the initial input of the third register and connected to the output of the first elements

Description

This control unit, the information input of the second multiplexer is the information input of the device, the t-th output of the second multiplexer, N) is connected to the information input of the group's register, the output of which is connected to the i-th information input of the third multiplexer, the address inputs of which are connected to the outputs the first counter, the output of the third multiplexer is connected to the information input of the allocation unit of the largest number, the output of which is connected to the information input of the first register, the output of which is connected to the first input of the second element And with the second information input of the block of the largest number, the clock input of which is connected to the output of the first element OR,

the address inputs of the second multiplexer are connected to the outputs of the second counter, the reset input of which is combined with the reset inputs of the third register and group registers and connected to the output of the first And element, the second input of which is combined with the first input of the third And element and connected to the output of the second register, the second input of the third element AND is combined with the input of the third register and connected to the output of the second element AND, the i-th input of the element OR is combined with the reset input of the i-ro register of the group and connected to the -th output of the first multiplexer, dresnye whose inputs are connected to outputs of the third register, the output of the third AND gate is the output device.

The invention relates to specialized computing and can be used in automation devices and computing devices in the study of random processes.

The purpose of the invention is to expand the functionality of the device by generating the required order statistics from a sample of random variables of a given volume.

In the study of random processes, the rth order of the statistics of the X. schiz sample of random variables of volume M Jt (X, X, ..., X) is the rth member of a non-decreasing row of N random variables formed from this sample: X.Xj ,, .. х,

FIG. 1 shows a block diagram of a device; FIG. 2 is a functional diagram of a control unit.

Device for generating order statistics contains multiplexer 1, 2 Group of registers, multiplexer 3, block 4 in the largest number, shift register 5, element And 6, register 7, element 8, multiplexer 9, address inputs of multiplexer 9, control input 9c multiplexer 9,

control unit 10, outputs iQ -lOfn + j of control unit, inputs lOj, control unit, IL 11 element, counter 12, OR element 13, register

5 14 masks, element And 15, counter 16, trigger 17, element And 18, generator 19 clock pulses, element And 20, elements 21 and 22 C-holding, counter 23, element And 24, element

0 and 25, elements 26 and 27 of the delay.

The operation of the device as a whole is organized as follows.

At the first stage, a sample of a given volume N is recorded,

5 by the incoming parallel code, in K parallel-serial registers 2, ..., 2 through multiplexer 1Хц (1 according to the clock pulses of the control unit 10 received at the counter 16. After the recording is finished, the overflow signal of the counter 16 prohibits the arrival of clock pulses at the counter 16 and permits their posting on.

5. Register inputs, .. ,, 2f (, 5,7. Information is read through a multiplexer to the input of block 4 of the largest number. The second compared number is read Q from register 5 (in the initial position, the zero code is written in it). Nai3

the larger compared number is again written to register 5 (for stable recording, the duration of the clock pulse is longer than the delay time of block 4). At the end of each comparison, a new counting pulse at the input of the counter 12 simultaneously brings the largest number to the initial selection block 4. This is repeated N times. At the end of the selection of the largest number from a sample of N values (it is recorded in register 5), a single signal is generated at the overflow output of counter 12, allowing the passage of a number from register 5 through AND 6 element. If M 2 then additionally is written to K-bit counter 12 - code number 2 -N. Block 4 is reset.

The number from register 5 through the element And 6 is fed to the input of the record of the register 7 and the element And 8. If the output of the register 14 is mask O, then the output of the device does not tread. In the serial-parallel register 7 (n-bit), only the code K of the lower bits of the number, i.e. code number register 2 with this number. This code is fed to the switching control inputs 9, ..., 9 (multiplexer, allowing the reset signal from output 10 of block 10 to pass to the reset input of register 2, which contains the most number for this moment. This register | is zero. Signal reset (reset to the initial state of the account {tick 12, shifts the mask code in register 14 by 1, returns to initial condition block 10, provides a new selection cycle for the most significant number and reset the register 2j with it. So repeats (Nh) In the (Kt-1) th cycle at the output of the mask register (1 in (m-d) th discharge, in the others), then in the (Nr) -M cycle, the largest number (r-statistics) is read into the output of the device through the AND element all registers 2, ..., 2 |, 7 and the counter 16 are output from the AND 15 element to the initial one. is.

The sequence N of random variables represented in the parallel M-bit code is fed to the information M-bit of the multiplexer and in accordance with the information received from the binary 68974

A counter 16 to the multiplexer switching control inputs is written to the corresponding N parallel-sequential cyclic shift (M + K) -disk registers 2, 2, ..., 2. Impulses of the Account go to the counting input of the binary counter 16 from the output of the clock generator 19

through the element 20, the second (inverse) input of which receives a signal from the (K- | -1) -th overflow output of this binary K-bit (Nj + 1) counter 16.

5 Upon receipt (N + 1) -ro of a counting pulse from the second output 10 of block 10 (output of element AND 20) at (K + Om I output of overflow of counter 16, a signal is generated that arrives at

Q second input lOjj block 10, i.e. to the inverse input of the element And 20 and to the third input of the element And 18. Thus, further passage of the counting pulses to the counting

5 the input of the counter 16 and the passage of clock pulses from the output of the clock generator 19 through the element AND 18 (the RS-flip-flop 17 of the unit Yu is in the one state) is permitted,

Q Clock pulses from the output of the element And 18 arrive at the counting input of the T-th counter 23 with the phase-pulse presentation of information, on the 6th, ..., (N) -th outputs 10, ..., 10 (5 block 10 and through the corresponding elements 21 and 22 of the delay for the fourth and fifth outputs 104, Yu of the block 10. From the 6th, ..., (N + 5) -ro outputs of the block 10, the clock pulses arrive at the shift control inputs (M + K) - discharge registers 2,2, ..., 2 and K-bit register 7. From registers 2, ..., 2f information in a sequential (M + K) -discharge code (in the K lower-order bits of each i register 2i is constantly recorded code of its time The serial number) goes to the corresponding input 3, ..., 3. The multiplexer. The choice of one of the registers 2, ..., 2 in the multiplexer is determined by the code of the first binary counter (K-bit) 12, arriving at the inputs of the switching control 3, 3 ,,,

KS multiplex

litter. On counting input 12

tt. . -. tt of the binary counter 12 (until it overflows) pulses come from the output of the phase-pulse counter 5 23 through the AND 25 element (from the output 10 of the block 10), the overflow signal on the (K + 1) th overflow output of the counter 12 prohibits further passage of pulses through the element 25 on the counting input 122 of the first binary counter 12 (via the third output lOj of block 10) prepares the reading of the selected largest number through the first element 6 of the order statistics generation device and the passage of the pulse for inhibiting the formation of clock pulses pulses from the output of the T-th counter 23 through the AND 24 element to the R-input of the RS flip-flop 17, arriving at the third input of the Yu block 10. The delay element 26 eliminates the possibility of generating a prohibition signal directly at the moment of generating the overflow signal of the counter 12, which is necessary for ensure the subsequent counting of numbers from register 2 i. The time of its delay is equal to the pulse duration at the output of counter 23. Thus, information from (M + K) -discharge registers 2, ..., 2 through the multiplexer is fed to the first input 4 of the 4th target of the largest number, to the second input 4j of which Receives (also in sequential form) the number from (M + K) -display register 5. Clock pulses to the input 5 of the register shift control 5 are received from the output of the clock generator 19 through the element 18 and -delay element 21 (the delay time is equal to the delay time signal in the multiplexer). Before the start of the comparison cycle, a zero code is recorded in register 5. The largest number selected in block 4 is recorded in serial code into register 5. At the end of the kaluga procedure, comparing two numbers with a pulse from the third output lOj of block 10 also connects to the counting input 12 of the binary counter 12 and through the SHSh 13 element to the clock input 4 j blo By the 4th largest number, the latter is returned to its original state. If there is an overflow signal at the binary counter overflow output 12, the number from register 5 through element 6 is rewritten into K-bit register 7 976 (after which in block 10 a prohibition pulse is generated on the R input of the RS flip-flop 17 due to the next pulse from the output of the counter 23). In this case, the first M bits are lost. The pulses at the input 7 of the shift control of the Diffraction Register 7 are received from the fifth output U of block 10 (through element 18, elements 21 and 22 of the delay from the output of the clock generator 19. To ensure synchronism of operation and recording at input 7 in register 7, the delay time in delay circuit 22 is equal to the delay in the elea | ent and 6. At the same time, the number from the output of the element 6 also arrives at the first input of the element 8 (a serial (M + (.) T-bit code). the number of the device’s output does not pass. code 7 of register number 2, in which the largest number is currently written, this number is received in parallel from the outputs of register 7 to the switching control inputs 9, 9, ..., 9j of the multiplexer. Thus, the number of the next registerable register is determined 2. At the end of the selection of one of the N outputs of the multiplexer, its information input and the switching enable input from the first output 10 of unit 10 receive a single signal. This signal comes from the output of counter 23 through AND 24 and delay elements 27, where the delay time T., is selected taking into account the arrival time at the inputs of multiplexer 9 of this signal and the code from the outputs of register 7: i7 V 2i i 9-i3-Uj where - j-ro device block delay time. The signal from one of the outputs of the multiplexer is fed to the reset input of the corresponding register 2}, wrapped it, as well as one of the N inputs of the element OR 11. The signal from the output of the latter is fed to the first input. block 10 (to the 5-input R5 of the trigger 17, which determines the passage of clock pulses from the output of the generator 19 through the element I 18), to the outputs 12 and 52 of the reset of the binary counter .12 and (M - - K T) -discharge register 5 through the SHSh 13 element to the clock input 4 of the block 4

. - 7

the largest number (brings it to its original state), to the input of the element 15 and the clock input of the (M-g) -sized register 14 of the mask. The signal arriving at the first input 10oi of the unit 10 is fed to the 5-input R5 of the trigger 17, transferring it to the single state (preparing the further passage of the clock pulses through the element 18).

The signal input to the shift register control register 14 of the mask shifts the mask code. By one bit. The (Nr) -ro bit of register 14 is fed to the second input of element 8 and the first input of element 15. To form random statistics from a sample of random variables | vj when forming a mask in register 14, the first bit is written 1 (in the remaining bit zeros).

At the end of the device’s cycle of operation, the j-cycle is determined by selecting the next largest number from a sample (Nj) of random variables, selecting the maximum number and eliminating it from further consideration by resetting the corresponding register 2i, then forming the order statistics is organized, starting with their larger number , in the (N-Om cycle to the first input of elements 968978

That AND 8 enters gpor dkova statistics in a sequential code.

Thus, at the end of the target, the highest number in the (Nrl) -M 5 cycle of operation at the output of register 14 (in its (Nr) -M rank) is formed on 1, ensuring in the next cycle of operation ((And-d) -m a) passing the zth order statistic through to the element AND 8 to the output of the device ("the lower bits, the generated binary number in the sequential (M + K) -disk code, are not used in the future). In addition, 1 from the output of the register t4, arriving at the first input of the element 15, when the signal from the output of the element 11 appears, ensures the formation at the output of the element 11

20 15 reset signals, the action of which to the reset inputs of registers 2, and the reset inputs 7j, 16 of register 7 and counter 16. The latter zeroes, the signal from the overflow output disappears,

5 thus, the counting pulses are allowed to return from the first output 10 of the block 10 to the counting input 16 g of the counter 16 and the passage of the clock pulses through

0 element and 18 ..

The selection of the gth statistic from the new sample of random variables begins, the operation of the device is repeated.

/ d

n

Fig1

Claims (1)

DEVICE FOR FORMING ORDER STATISTICS, containing the first and second registers, the first OR element, AND elements, characterized in that, in order to expand the functionality by sampling a given volume, multiplexers, a counter, a control unit, a group of registers, third are introduced into it a register, a block for allocating the largest number, a second OR element, the control unit comprising a clock pulse generator, AND elements, delay elements, a counter, a trigger, the first inputs of the first and second elements AND the unit block Power is combined and connected to the output of the clock, the second input of the first element AND of the control unit is connected to the output of the trigger of the control unit, the zero input of which is combined with the input of the first delay element of the control unit and is connected to the output of the third element And of the control unit, the first input of which is combined with the first input of the fourth element AND of the control unit and is connected to the output of the counter of the control unit, the counting input of which is combined with the input of the second delay element and is connected to the output of the first element AND of the control unit, the second input of the third element AND of the control unit is connected to the output of the third delay element, the input of which is combined with the second input of the fourth element AND of the control unit and connected to the overflow output of the first counter, the output of the fourth element AND of the control unit is connected to the counting input of the first counter and the first input of the first element. OR, the output of the first delay element is connected to the information and control inputs of the first multiplexer, a single trigger input to the control unit is connected with the reset inputs of the first counter and the first register, the second input of the first OR element, the first input of the first AND element, the clock input of the second register and connected to the output of the second OR element, the output of the second element AND of the control unit is connected to the counting input of the second * counter, the second input of the second element AND of the control unit is combined with the third input of the first element AND of the control unit and connected to the overflow output of the second counter, the output of the second delay element is connected to the clock input of the first register and through the fourth delay element to the clock input of the first register of the group, the clock inputs of the N-1 registers of the group are combined with SU ... A 196897 is the input of the third register and connected to the output of the first element 1196897 and the control unit, the information input of the second multiplexer is the information input of the device, the i-th output of the second multiplexer (l = 1, N) is connected to the information input ι-th register of the group, the output of which is connected to the i-th information input of the third multiplexer, whose address inputs are connected to the outputs of the first counter, the output of the third multiplexer is connected to the information input of the allocation unit of the largest number, the output of which о is connected to the information input of the first register, the output of which is connected to the first input of the second AND element and to the second information input of the highest number allocation unit, the clock input of which is connected to the output of the first OR element, the address inputs of the second multiplexer are connected to the outputs of the second counter, the reset input of which combined with the reset inputs of the third register and group registers and connected to the output of the first element And, the second input of which is combined with the first input of the third element And and connected to the output In the second register, the second input of the third AND element is combined with the input of the third register entry and connected to the output of the second And element, the ϊth input of the OR element is combined with the reset input of the i-th group register and connected to the 1st output of the first multiplexer, the address inputs of which connected to the outputs of the third register, the output of the third element AND is the output of the device.