SU1088002A1 - Device for simulating queueing systems - Google Patents

Abstract

A DEVICE FOR MODELING MASS SERVICE SYSTEMS, containing an impulse generator, an output unit, a polling unit consisting of an R 5 flip-flop, an OR element, a delay element, and a group of delay elements whose inputs are connected to the B-RS trigger input, whose single input through the delay element is connected to the first input of the OR element, the second input of which is the reset input of the polling unit, and the cement output, or connected to the R input H5-TrI1Tera, the service enable signal generator, consisting of 5 options for successively connected x the first Tpirrepa, the first NID element, the first differentiating element, the first pulse expander and the first OR element, are connected in series to the second trigger, the second NI element, the second differentiating element and the second pulse expander, the output of which is connected to another input the first element OR, the outputs of the first and the second differentiating elements are connected respectively to the single inputs of the first and second flip-flops, the other inputs of the AND-NOT elements are combined and connected to the first clock B The LAMP of the pulse generator, zero 1 INPUT of the second trigger, is the Startup input of the device, the output of the first element OR is connected to the inputs of the delay elements of the polling unit group, the outputs of the first and second pulse extenders are connected respectively to the first and second inputs of the output unit, the shift unit consisting of a register shift, the first group of elements AND, the first group of elements OR, the first group of elements NOT, the second group of elements AND, the element OR, the element NOT, the group of delay elements, the second and the third group e is NOT, a tray of the third and fourth groups of AND elements, a second group of OR elements, where (L in the shift unit, the outputs of the delayed elements of the group are connected to the corresponding inputs of the parallel register of the shift register, the discharge outputs of which are connected to the corresponding inputs of the Both the first group, the inputs of the element are NOT the second group and the 1 inputs of the elements of the third group 00, the inputs of the elements NOT of the third group 00 and the first inputs of the elements of the third group are connected to the corresponding input of the element OR, the second to inputs elements of the second and third groups are connected to the outputs of the corresponding elements NOT replicas and the third group, and the outputs of the elements of the second and third groups are connected to the inputs of the corresponding element OR of the second group, the outputs of which are connected to the inputs of coherence delay elements rpjynn, the second inputs of the AND elements of the first group connected to the outputs of the corresponding delay element of the polling unit group, the output of the first

Description

And the first group is connected to the first BXoAfflv element. OR, with the input of the first apemenga NOT the first group or the first element OR of the first Group, the outputs of the NOT elements of the first group are connected to the first inputs of the corresponding elements AND the fourth group, the output of the Kth element AND of the first group (, n) is connected to the second input (K-1) -th element of the fourth group, the output of the M-th element And the first group (M in 2, | (-1) is also connected to the first element (Ml) -ro of the element OR the first (group, second input of the M- first element OR of the first group - to the input of the M-th element is NOT the first group, the output of which is connected to the second input of the M-th About the fourth group element, the output of the k-th element and the fourth group is connected to the k-th input of the element OR, the output of which is connected to the input of the element NOT connected to the zero input of the first trigger of the service enable signal generator and served the output unit, the output of the first bit of the shift register of the shift unit is connected to the input of the queued order.

the output of the last bit of the shift register of the shift block is connected to the input of the output unit waiting time, the second clock output of the pulse generator is connected to the clock input of the shift register bypass, the right shift input of which is connected to the output of the trigger of the polling unit, that, for the purpose of the Modeling systems class by simulating closed-end Mass Service systems with a finite number of sources, it also contains a quotation generator, a ban element and a reversible counter, The subtracting and summing inputs of which are connected respectively to the output of the second pulse expander of the service resolution resolver and the OUTPL1 of the first bit of the shift block shift register, the sequential recording input of which is connected to the generator output, the input of which is with the output of the prohibition element whose control input is control input device, and the information input is connected to the output of the reversible counter.

The invention relates to computing and can be implemented and simulated wiring processes in queuing systems (QS),

A specialized device for modeling flow of the demand and service processes is known, which contains a random time interval generator, a controlled pulse generator, an operating mode block, an AND scheme, a grip-o reptl.

Such a device is intended to simulate separately non-welded flows of applications with variable intensity of operation of the servicing device 15 with randomly aaKoHravf service, however, it does not allow to simulate the operation of the QS in the chain.

A known device for a simulated 20 QS, containing a shift register, a pulse generator, the first input of which is connected to the first input of the shift register, the second input of which is connected to the reception bus, the control unit, the polling unit, the output unit timeout sensor, driver waiting time limiting signals, a service enable signal generator, the first input of which and the first input of the control unit are connected respectively to the second and third inputs of the pulse generator, the outputs of the control unit Ensuring and generating timeout signaling signals are connected to the outputs of the waiting time sensor, the outlets of which are given to the first group of inputs of the register, the second group of inputs of which are connected to the outputs of the polling unit,

the input of which is connected to the first output of the service resolution signal generator, the second and third outputs of which are connected to the first and second output blocks, the third, fourth, fifth, sixth and seventh inputs of which are connected respectively to the second 19TH INPUT of the wait time limiter signal generator, - the second, third and fourth outputs of the shift register, the fifth one, the sixth of which is connected to the second inputs of the maker of the service enable and control signals, the second output and the third The input of which is connected respectively to the first input of the driver of the waiting time limits and one ring of the drive, the other outputs of which are connected to the outputs of the device, which sets and starts the inputs of which are connected respectively to the second input (1 driver of the waiting time limit signals and the third input of the service resolution enable generator C21, However, this device does not allow to simulate the operation of closed QS with a finite number of sources, which is due to characteristics of the incoming flow from the number of applications in the system, i.e. in line and on. service. It is known that the flow rate of the quotes in such QS varies in the process of functioning in accordance with the expression L (mn) D (1) where m is the total number of quota sources in the closed QS, L is the flux intensity of the quotes ; n is the number per vj located in the system. The purpose of the invention is to expand the class of simulated QS, the goal is achieved in that a device containing a pulse generator, an output unit, a polling unit consisting of an R5 flip-flop, an OR element, a delay element, and a group of delay elements whose inputs with the S-input of the RS-flip-flop, a single output of which is connected via the delay element to the first input of the OR element, the second input of which is the reset input of the polling unit, and the output to the OR element is connected to the K-INPUT Ss flip-flop This consists of serially connected first trigger, first NAND element, first differentiating element, first pulse expander, and first OR element of the second trigger connected in series, second IS-NOT element, second 24 rs differentiating element, and second pulse extender, the cat output is connected to the other input of the first element OR, the outputs of the first and second differentiating elements are connected respectively to the single inputs of the first and second triggers, other inputs of the elements AND-NOT combined and connected to the first clock Bboctvj: pulse generator, the zero input of the second trigger is the device start input, the output of the first element OR is connected to the inputs of the delay elements of the polling unit group, the outputs of the first and second pulse extenders are connected respectively to the first and second inputs of the output block, the shift block, consisting of the shift register, the first group of elements AND, the first group of elements OR, the nepBtrfi group of elements NOT, the second group of elements AND, the element OR, the element NOT, the group element The supports of the second and third groups HEj of the third and fourth groups of elements AND, the second group of elements OR in the shift block, the outputs of the group delay elements are connected to the corresponding inputs of the parallel register of the shift register, the bit outputs of which are connected respectively to the first inputs of the AND elements of the first group, the inputs of elements NOT the second group and the first inputs of elements AND the third group, the inputs of the elements NOT the third group and the first inputs of the elements AND the third, group are connected to the corresponding input of the element ORT, the second inputs of the elements of the second and third groups are connected to the outputs of the corresponding elements NOT of the second and third groups, and the outputs of the elements of the second and Tperbdi groups connect5 to the inputs of the corresponding element OR of the second group whose outputs are connected to the inputs of the corresponding delay elements of the groups , the second inputs of the AND elements of the first group are connected to the outputs of the corresponding delay element of the polling unit group, the output of the first AND element of the first group is connected to the first input of the OR element, to the input of the first element N E of the first group and BTOjSiiM input of the first element OR of the first group, the outputs of the elements of the NOT group of the first group are connected to the first inputs of the corresponding elements of the fourth group, the output of the K-th element AND of the first group (K 2, n) is connected to the second input} (K - 1) of the fourth group AND of the fourth group, the output of the Mth and the first group (M, nJ.) Is also connected to the first input (M-1) of the OR element of the first group, the second input of the Mth element OR the first group - to the input of the M-th element is NOT the first group whose output is connected; with the second input of the M-th element AND the fourth group The output of the K-th element of the fourth group is connected to the K-th input of the element OR) the output of the electrical connection is connected to the input of the element NOT connected to the output to the zero input / first t {R1GGer of the service enable signal generator and the input of the output unit that was discussed, the output of the first the shift register of the shift block is connected to the aa b1J input, queued, the output block, the output of the last bit of the shift register; the shift shaft is connected to the output time of the output block; the second clock output of the pulse generator Connected to the clock input of the shift register of the shift unit, the right shift input of which is connected to the trigger output of the polling unit, input generator, prohibition element and reversible counter, subtractor and summing input of which are connected to the output pulse generator and the first the shift of the shift shear block regaster, the input of which is supplied to the output ;: a generator of the demand, the input of which is connected to the output of the prohibition element, controlling whose input is L kltsim sound control input device and inforyadishny input coupled to the outputs of the counter reversivns. FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the shifts in FIG. 3; a poll block in FIG. 4; an output block; in fig. 5 is a diagram of a service enable signal generator. The device contains a block 1 shift,. generator 2 pulses, reversible counter 3, polling block 4, block 5 of input, generator 6 for wok, driver for servicing permission, prohibition element 8, triggering 9 and adjusting 10 inputs of the device (LSGWA "Shift block 1" "" represents The most recent variant of the shift register (Fig. 2) contains the first group of element AND 11, the first group of elements OR 12, the first group of elements NOT 13, the fourth 10 026 group of elements AND 14, the element OR 15, the element NOT 16, the group of elements 17 delays, the second group of elements OR 1.8, the second 19 and third 20 group of elements NOT, the second 21 and third and 22 riynny elements, shift register 23. Shift block 1 consists of three nodes / IOB I, II, III, Node 1 is a standard bi-directional shift register with serial and parallel information input. The circuit has serial input inputs, D + when shifting to the right and D-when shifting to the left, eight inputs of parallel input C -D8, clock counting input C, control inputs VI and V 2 for selecting the operating mode, input for setting OK, and eight outputs for each digit 1-8, Depending on the states of the installation inputs V 1 V2 and C node I can be work in different modes: sequentially entering from the shift axis; sequential entry with a shift to the left; parallel entry; storage; the settings in O. In the sequential transfer mode with information skvami, the logical zero level is fed to the right of the V1 input, and the level of the logical one is input to the V 2 input. Parallel information entry is carried out, the set inputs are in the state of logical unit, the Node G1 is designed to determine the priority bit of the standard shift register and has an almost homogeneous structure, and the node C1 is designed to quench the unit in the priority bit of the standard shift register without changing the state of the remaining bits of this register. The functional purpose of the output of the shift unit is the following: output of the wok supplied to the service ;, output of the element OR 15} output of the wok received by the service but wired; the presence of oisgroup for vsh or lack of a si nal about ending the service of a previously received application queued for servicing — output 1-g bit of the shift register ;;, the output signal of exceeding a fixed time limit for the application in queue, t, e, on this output, an increase in the applications from the queue occurs, since their service time has exceeded the limit value - the output of the 8th & r row of the standard shift register; the output signal of the absence of the sasi & OK in the queue is the output of the NOT element 16. The polling unit 4 (Fig. 3) is intended to perform a polling of the states of the rads of the standard shift register, sodermt group alemeyts 24 delays trigger 25, the element 26 zaakkn, element OR 27, the first trigger input is connected to the BuxoAt vi of the driver 7 of the enable signal Obspeak and its output is connected to the delay element 22, and to the input VI of the shift register 1. The output terminal 5 (Fig. 4) performs the pulse expansion function up to a predetermined value for each (each of the inputs. Expansion by means of the following: standard pulse 28. Pulse expansion. The functionality of the inputs and outputs 601 of the 5th year is as follows: first input input of the signal from the output of the imaging unit 7 about the absence of a request to the second queue second input of the input input of the output from the output 7 for the moments from the sleep of the second. Assignment of the remaining Bxoats to the analogous outputs of the shift block Functional diagram of the form 7 signal Alov of the service resolution (Fig. 5) contains differential 29, pulse expansion circuits of the pulse to a given value and the OR element 31, triggers 32, and IS-NOT 33 signals. The trigger input 9 ycTp tcTBa is connected to the first input of the second trigger 32. In the mode, moduls The van 311 of the QS at the installation input 10 (4 1G.1) is supplied with the logic level O, and when the simulation of the closed CMD is logically. The device works as follows. During the modulation of the opened QS from the installation input 10 of the device, the signal is fed to the input of the 8 bar element, banned yuschy passage momenta with the down counter 3 outputs, to the control input tions generator 6. In the simulation, closed QS is allowed direct ohozhdenie signals output from the down counter 3 to the control input of oscillator 6 yuschi requisition. From the output of the generator 6 for the woks on the Ix of the shear unit 1, there is a flow of pulses simulating the flow of the blanks to the CMD. The intensity of this flow in the process of modeling the open QS remains constant. When simulating a closed QS, the intensity of the impulse of pulses varies depending on the number of applications in the system, in accordance with formula (1). Information about the amount of v1Zh located at a time in the system is stored in a reversible lock. The device starts with the fact that the input 9 of the incoming Nmulse flow imitating the possibility of starting the application is sent to the scoop input 9. This signal is stored in the shaper 7. Also, a pulse is placed on the 1 shift unit (od 0+) from the generator 6. The alternating clock pulse from the generator 2 (ia imitating the current time) is the nociyinash signal; To form e 7 (fig. 5) passes the link of the second element 32, 33, 29 and the DA, is fed through the bridge to the reversible counter 3 and to the block 5 of the output. Osh (the same signal, d. OR element 32, triggers demand block 4, which outputs standard input V 1 of the standard resistor, and output signals 1-8 from logic inputs 1 to input elements of AND node II block 1 shift, Pr1 availability of a clock pulse From generator 2 to the input C in node I of block 1, the shift is performed with the sequential recording mode (s from the SC & KG1NL to the right, and from 1-8 to the node P the binary information in parallel code for the priority of 1 azr and standard shift register (e This will be the first in order, starting from the eighth, the bit containing the pommel unit.) The impulse (for 1No) is sent to the service via the OR 15 element. Thus, the service with the highest waiting time (discipline first came - first). Also, the pulses are received from first1: the standard register registers to the output unit 5 and to the reversible counter 3 and from the senior eight (output to 6th output 5). After the block, block 4 supplies the input of the VI standard register with the logic level (the logic level is constantly maintained at the input V2). In the node Shch.registr 1 shift occurs the following. The inputs 1–8 of node 111 are supplied respectively with binary information from outputs 1–8 of wapa II and exit no. 1–8 of w aa 1. As a result, the zlemeng groups (at the node W at the entrance of the register 9 1 – D8 in parallel The variable input is inserted in all bits of the information without changing the priority bit in the x-bit, in which the logical unit is zeroed, i.e. the logical unit of the stand-off bit is suppressed. If at the time of polling the shift register is thick, the signal is: OR 16 to shaper 7 with a COL pE 1o repeat of ifos In the presence of a psychic overshoot of a timed pulse, this signal passes the link of the first elements of the 32RD, 29, 30, enters through the output in the output block 5 and at the same time through the OR 32 element starts, block 4 polling.

II 111 1О O2 Thus, in the process of device rabbing, the pulses are continuously applied to the reversible counter 3: to the summing input - from the low-order bit of the standard shift register (the quantity of applications received for service) to the subtracting input from the formerseater 7 (number of served for wok). Therefore, at any moment in the reversible counter 3 there is information about the number of applications that are in the system / depending on which the flow rate of the application generator is changing. . The proposed device allows to simulate the functioning of closed and open SMEs. It can work with any input streams, and also allows varying the latch time range over a wide range due to a change in the clock frequency of the pulse generator.

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Claims (1)

DEVICE FOR MODELING MASS SERVICE SYSTEMS, comprising a pulse generator, an output unit, a polling unit, consisting of an R 5 trigger, an OR element, a delay element and a group of delay elements, the inputs of which are connected to the 6 input of the R5 trigger, a single input which through the delay element is connected to the first input of the OR element, the second input of which is the reset input of the polling unit, and the output of the OR element is connected to the R-input of the RS-trigger, a service enable signal conditioner, consisting of series-connected Vågå trigger, a first AND-NO element, first differentiating element, a first expander member and a first pulse OR. connected in series to the second trigger, the second AND-NOT element, the second differentiating element and the second pulse extender, the output of which is connected to another input of the first OR element, the outputs of the first and second differentiating elements are connected respectively to the unit inputs of the first and second triggers, other inputs of AND elements -NOT combined and connected to the first clock output g of the pulse generator, the zero input of the second trigger is the input of the device’s start, the output of the first element OR is connected to the input I will give delay elements for the group of the polling unit, the outputs of the first and second pulse expanders are connected respectively to the first and second inputs of the output unit, the shift unit, consisting of the shift register, the first group of AND elements, the first group of OR elements, the first group of NOT elements, the second group of elements AND, an OR element, an NOT element, a group of delay elements, a second and third group of NOT elements, a third and fourth group of AND elements, a second group of OR elements, and in the shift block, the outputs of the delay elements of the group are connected to the corresponding etstvuyushi <E inputs parallel're entering. shift shift, whose bit outputs are connected respectively to the first inputs of AND elements of the first group, the inputs of NOT elements, the second group and the first inputs of AND elements of the third group, the inputs of the NOT elements of the third group and the first inputs of the AND elements of the third group are connected to the corresponding ι input OR element, the second inputs of the AND elements of the second and third groups of SU 1088002 are connected to the outputs of the corresponding elements NOT of the second and third groups, and the outputs of the AND elements of the second and third groups are connected to the inputs of the corresponding OR Ora group whose outputs are connected to inputs of respective delay elements of groups, the second inputs of elements And the first group is connected to the outputs of the corresponding delay element of the group of the polling block, the output of the first element and the first group is connected to the first input of the element, OR, to the input of the first element NOT of the first group and the second input of the first element OR of the first group, the outputs of the elements of NOT the first group are connected with the first inputs of the corresponding elements AND of the fourth group, the output of the K-th element And the first group (K “2, η) is connected to the second input of the (K-1) -th element And the fourth group, the output of the M-th element And the first group (M = 2, u \ -1) is also connected e to the first input (M - 1) of the OR element of the first group, the second input of the Mth element OR of the first group - ₄ to the input of the Mth element NOT of the first group, the output of which is connected to the second input of the Mth element of the fourth group, the output of the K-th element of the fourth group is connected to the K-th input of the OR element, the output of which is connected to the input of the element NOT connected to the zero input of the first trigger of the driver of the service enable signal and the input of the served requests of the output unit, the output of the first bit of the shift register block shear connected to I the house of applications placed in the queue of the output unit, the output of the last bit of the shift register of the shift unit is connected to the timeout input of the output unit, the second clock output of the pulse generator is connected to the clock input of the shift register of the shift unit, the right shift input of which is connected to the output of the polling unit trigger , characterized in that, in order to expand the class of modeling systems by modeling closed queuing systems with a finite number of sources of applications, it additionally contains a generator p applications, the prohibition element and the reverse counter, subtracting and summing the inputs of which are connected respectively to the output of the second pulse expander of the driver of the service enable signal and the output of the first bit of the shift register of the shift block, the input of which is sequentially connected to the output of the generator of applications, the input of which is connected to the output of the element prohibition, the control input of which is the control input of the device, and the information input is connected to the output of the reversible counter. 12