SU1444892A1 - Programmable logic device - Google Patents

Description

(21) 4252426 / 24-24

(22) 05/29/87

(46) 12/15/88. Bul, № 46

(71) Kharkiv Aviation Institute. - Institute named after N. Zhukovsky

(72) V.Politenko, V.Ya. Zhikharev, G.N.Timonkin, V.S. Kharchenko, S.N.Tkachenk o and S.F.Tyurin

(53) 681.327.66 (088.8) (56) S. Baranov, A. Barkalov The use of programmable logic arrays in digital technology. - Foreign Radio Electronics, 1982, No. 6, p. 67-68.

USSR Author's Certificate No. 1267964, cl. G 11 C 17/00, iG 06 F 7/00, 1983.

(54) PROGRAMMABLE STOCKHOOD

(57) The invention relates to computing and can be used to calculate systems.

(L

Boolean functions. The aim of the invention is to improve the speed of the device in the recording mode. To achieve this goal, a device containing AND 1 elements, OR 5 elements, three groups of 2,3,4 D-flip-flops and two groups of 6.7 elements with Three output states, is entered

The invention relates to computing and can be used to compute systems of Boolean functions.

The aim of the invention is to improve the speed of the device during recording, due to the fact that the programming of the elements AND and OR of the device is performed simultaneously.

Functional diagram of the device shown in the drawing.

The symbols n, g, and t are used to denote the number of inputs, terms and outputs of the device, respectively.

The programmable logic device contains g p-input elements AND 1, the first 2, the second 3 and the third 4 groups of B-flip-flops, t elements OR 5, the first group of gn elements AND 6 with three output states, a group of gn elements AND -NON 7 with three output states, gt of two-input elements And 8, counter 9 with recalculation factor 2g + l, decoder 10, first 11 and second 12 RS-triggers, second group of t elements And 13 with three states mi output, the third RS-trigger 14, an additional element OR 15, information inputs 16 bit n, information outputs 17 bit t, input 18 reset, clock input 19, output 20 of the display of the programming elements OR, output 21 of the display of the programming of elements I.

The first group 2 of D-flip-flops is designed to receive and store information signals of programming and feed them to the control inputs second, the inputs of the corresponding elements AND with three states wipe the group of elements 13 with three states of the outputs. This made it possible to use for programming not only informational inputs, but also informational outputs, and to program the AND and OR elements simultaneously. 1 il.

move. The second group of 3 D-flip-flops is intended for receiving and storing information programming signals and supplying them to the control inputs of the corresponding AND-NOT elements with three output states. The third group of 4 D-flip-flops is intended to receive from the information outputs of the device and store the information signals of programming and feed them to the control inputs of the AND 8 elements of the second group. I

In the absence of an enable signal at the control (second) input, the outputs of the corresponding element with three output states are in a high-impedance state.

The counter 9 with a conversion factor of 2g + l is designed to form signals for controlling the decoder 10 and feed a pulse from its overflow output to the installation input of the second trigger 12 using counting signals from the clock input 19 of the device.

The decoder 10 has a 2g + t output (from zero to 2g-th) and is intended to generate synchronization signals for the first, second and third groups of 2-4 D-flip-flops (outputs from the first to 2§th), and the zero output is intended for install the third trigger 14,

The first RS flip-flop 11 is designed to form and feed a signal to the input 20 of the device after programming the D-triggers of the third group 4 according to the (g + l) -My pulse of the counter 9. At the same time, the installation of the 1I trigger occurs when the gth output changes degaifratora with About

 AND

on 1

The second RS flip-flop 12 is designed to form and feed a signal to the output 21 of the device at the end; The sprinting of the D-flip-flops of the first and second groups 2 and 3 through the (2g4-l) -My counting pulse of counter 9. At the same time, the trigger is set by the overflow signal of counter 9 with the conversion factor 2g-H.

The second group of elements And 13 with three states of output is intended to transfer informational outputs of the device to output signals from elements OR 5 according to the permission signal at their control inputs and to transfer their outputs and high impedance state when they are removed from their control ( second) the inputs of the enable signal, and the permissions of the signal come from the inverse output of the third trigger 14, I

Device input 18 is intended

to receive the D-flip-flop reset signal of the first 2, second 3 | the third 4 groups, the first 11, the second 12 and the third 14 RS-flip-flops and the counter 9. The device input 19 is designed to receive programming clock signals. Output 20 devices

, Is the second control output, indicating that the programming of the elements OR is completed, & 1 INPUT 21 of the device is the first control output, indicating that the programming of the AND elements and, therefore, the device as a whole is finished.

A programmable logic device can operate in two modes: programming and computing,

In the programming (or recording) mode, the device operates as follows,

In the initial state, the D-triggers of the first - third groups 2-4, ElS-triggers 1.2 514 and counter 9 are reset to the input 18 of the device. The control inputs of the groups of elements And 6.7 with three output states are given signals O, and their outputs are in a high impedance state,

On the nepEOi.y pulse arriving at the device input 19, the counter 9 with the conversion factor 2g-fl goes to the first state and the signal 1 appears at the zero output of the decoder 10, the Third RS flip-flop 14 is set to state 1, and its inverse output is set to the signal O, therefore on the control. The inputs t of the AND 1 3 elements with three output states are also set to 0 levels O, and their outputs are brought to the high-impedance state. On the second clock pulse, the information inputs 16 of the device are supplied with a combination of logical programming signals of the first n D-flip-flops from the first group of 2 D-flip-flops, and the information outputs 17 of the device are supplied with a combination of logic signals of the first 0 t-D-flip-flops from the third group 4 D-flip-flops, which are entered into the corresponding D-flip-flops on the leading edge of the signal at the first output of the decoder 10. On the third 5 clock pulse, the logical inputs programming signals of the first p D-flip-flops from the second group 3 D-flip-flop, and at 0 information outputs 17 of the device, a combination of logic signals of programming the second t D-flip-flops from the third group of 4 D-flip-flops is fed, which is entered into 2. (the leading edge of the signal at the second output; decoder 10; Then, the programming and ramming process proceeds similarly. On the () th pulse at the clock 0 input 19, the first trigger 11 is set to state 1 at the installation input, to which the signal is applied 1 s (gtl) -ro out and the decoder 10 at the output 20 of the device 5 usta- navlivaets signal 1, which indicates the end of programming elements OR

According to (2g + l) -My pulse at input 19, the second trigger 12 sets g to state 1 at the installation input to which signal 1 is sent from the overflow output of counter 9, therefore at output 21 of the device

55

Signal 1 is set, which indicates the end of the programming of the AND elements and output signals. The signal 1 from the output of the trigger 12 at the first input of the element OR 15 embraces the third trigger 14,

tact unlike 2g +

cycles

therefore, the control inputs t of the elements with three output states without inversion receive a signal 1 from the inverse output of the trigger, and signals from the output t of the elements G1 5 5 are sent to the information outputs 17 of the device. In the next cycle the device is ready to perform calculations.

Thus, the programming of the device ends in 2g + l

gt n

the prototype due to the simultaneous programming of the D-flip-flops of the first 2 (second 3 in odd cycles) and the third 4 groups of P-triggers,

In the computation mode, the predicted device operates similarly to the prototype.

On the information inputs 16 mouth-. The characteristics of the input vector logical signals are supplied, the i-th bit of which () is fed to the information inputs i + (k-l) n | () elements from the gn group of elements AND 6 and AND-NOT 7 with three exit states. If the i-th bit of the k-ro conjunctive term has a direct value of the variable i, then the control input of the corresponding element AND 6 of the group gn of elements is given from the output of the corresponding trigger of the first group 2 of D-flip-flops signal 1, and The input of the corresponding element IS-NOT 7 from the group gn of elements is supplied from the output of the corresponding D-flip-flop of the second group of 3 D-flip-flops, signal O. If the 1st bit of the k-ro conjunctive term has the inverse of the variable i, then the corresponding element And 6 filed t output corresponding its D-flip-flop of the first group of flip-flops D-2 signal and to the control input of the corresponding AND-NO element 7 fed from the output of the respective D-flip-flop

second group of 3 D-flip-flops signal

n I ti I

If the i-th bit of the k-ro conjunctive term has an indifferent value of the variable, then the control inputs of the corresponding elements AND 6 and NAND 7 are supplied from the outputs of the corresponding D-flip-flops first 2 and second

444892 swarm of

ten

ts

20

25

3 groups of U-triggers signals

i.e. the outputs of both elements with three output states without inversion and with inversion are in a high-impedance state, which is perceived by the i-M input k-rb of the n-input element And 1 logical unit-i.

Thus, the state of each n element from the groups gn of elements AND 6 and AND-NOT 7, corresponding to the k-th element of AND 1, encodes the k-th term of a certain system of Boolean functions. And if the input vector hits this term, then the output of the corresponding element I 1 sets signal 1, since in this case signals 1 will be set at all its n inputs. Therefore, the outputs g of elements I 1 will be only signals I, short of conjunctive terms of g terms (1,5g62) are covered by the input signal.

In the gt group of elements And 8, t output functions are formed, and the output signal of the corresponding D-flip-flop of the third group of 4 flip-flops, equal to 1, indicates that the term of the same name is in the given function, and the signal O indicates that the term of the same name is not included in this function.

At the outputs t of the elements OR 5, a combination of logical signals appears, witnessing the value t of logical functions on a given set of input signals, which through the open elements I I3 arrives at the information outputs 17 of the device.

A new programming cycle begins with the supply of a reset pulse to the input 18 of the device.

45.:

Claims (1)

Invention Formula Programmable logic device containing g p-input elements AND (n is the number of information inputs of the device, l-igtf-Z), t elements OR (t number of information outputs of the device) I first, second and third pears 0 trig 55 gera, first elements And with the three states of the VYHKY group of elements of the NAND with three sosg - yki mk output, gt of the two-input elements AND, the counter n the decoder, and thirty 35 50 The D inputs i + (kl) of the P-flip-flops of the first and second groups, the first inputs of the corresponding AND elements with the three output states of the first group and the first inputs of AND-NOT elements with three output states (1 1bp} 1) are iM the information input of the device, the outputs of the P-flip-flops of the first group are connected to the second inputs of the corresponding elements AND with three states of the output of the first group, and the outputs of the D-flip-flops of the second group - with the second inputs of the corresponding elements AND-NOT outputs whose outputs are connected to the outputs of the corresponding And with three output states of the first group, the C inputs (k-On + ij-x D-flip-flops of the first group are connected to the k-th odd output of the decoder, and the C-inputs of the same D-flip-flops of the second group with k- m even output of the decoder, the outputs of the C (kl) n + -X elements And with three states of the output of the first group are connected to the inputs of the k-ro n-6 of the I element, the output of which is connected to the first inputs of kf (jl) g3- x two-input elements And (), the second inputs of which are connected to the outputs of the corresponding D-flip-flops of the third group, and the outputs - to the k-th input jx of the elements OR, Discount counter outputs are connected to inputs of the decoder, and the count input of the counter is a clock input ET devices from: In order to increase the device's speed in recording mode, the first, second and third RS-triggers, an additional element OR, and the second group of elements AND with three output states, the first inputs of which are connected, are introduced into it. with the outputs of the corresponding 10 elements OR, and the second inputs with the inverse output of the third RS flip-flop, whose S-input is connected. not with a zero output of the decoder and R-input - with the output of an additional 15 of the OR element, the output of the j-ro element AND with three output states of the second group is connected to the D-inputs fk + Cj-1) gj-x D-flip-flops of the third group and is the corresponding information output of the device, p- th output of the decoder () is connected to the C inputs (pl) t + j1-x D-flip-flops of the third group S-inputs of the first and second RS-flip-flops are connected respectively to the g-th output of the decoder and the output of the overflow counter, the output of the first RS trigger is the output of the programming indication of the elements of the OR device, the output of the second RS flip-flop is connected to the first in house additional element and OR is an output display device and programming elements, R-inputs of D and RS-triggers 35 and the second input of the additional element OR are a device reset input.