SU951711A1 - Pulse train frequency digital divider - Google Patents

Description

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The invention relates to the field of electronic digital division of the pulse frequency and can be used, for example, to build frequency dividers with a division factor of 2.

A digital frequency divider of the following pulses is known with a division factor not equal to 2, which contains triggers and AND elements, in which, by means of feedback, part of steady states 1 is eliminated.

The disadvantage of the described device is reduced speed.

The closest in technical essence to the invention is a pulse frequency divider containing a main frequency divider and an additional trigger, the synchronizing inputs of which are combined, the output of the main frequency divider is connected to the I-input of the additional trigger, inverse you-.

the course of which is connected to (the input of the main frequency divider.

The disadvantages of this device are a decrease in speed with large division factors and a limited range of variation of the division factor.

The purpose of the invention is to increase speed while simultaneously expanding the range of variation of the division factor.

The goal is achieved by the fact that a digital pulse frequency divider containing dividers (a 5th frequency clock and a trigger, the synchronizing inputs of which are combined, and the output of one of the bits of the frequency divider connected to the trigger setup input) is entered into the digital trigger frequency divider.

20 block, the first input of which is connected to the control bus, the second input - with the trigger output, the nth input - with the output of the first bit of the frequency divider, and the remaining inputs - with the corresponding bit outputs of the frequency divider, the setup input of the first bit of which connected to the output of the logic unit, with the output of the first bit of the frequency divider connected to the setup input of the trigger. The drawing shows a block diagram of the device. The device contains a frequency divider 1, trigger 2, logic unit 3 in the particular case consisting of elements 4 and 5 AND-NOT. The device works as follows. . When at least one input of element 5 contains a logical zero, it does not affect the operation of divider 1. If there are logical units at all inputs of element 5, it confirms the logical unit at the output of the first bit, thus closing the century-, divider 1 positive reverse communication Both control inputs must have a logical one. In the preceding cycle of operation of the device, the trigger 2 by the logical zero of the first bit is set to the state of the logical unit and saves it in the feedback closure cycle, because, due to the delay in the first bit, its output logic zero is removed after switching level at the dynamic counting output (or dynamic input of setting 0) of the trigger. The next input pulse does not change the state of divider 1, since its first bit is blocked from the output of element 5, but changes the trigger trigger 2, which through element 5 removes the unit setting signal of the first bit, preparing it and the whole divider 1 to receiving subsequent input pulses. Due to the delay in trigger 2 and element 5, the unit setting signal is first removed in a row after the switching level is set at its dynamic counting input, therefore the state of the first discharge does not change. Thus, one input pulse is skipped, which means an increase in the total division factor by 1. This increment of the division factor occurs three times: when logical bits are present at the output of the bits dividing 14 l 1 from the fourth to the n-th inclusive, then the logical one the discharge thrice (with a logical zero at the outputs of the second and / or third bits) causes a logical zero at the output of element 5 and a corresponding skip of the next input pulse. As a result, the device has a division ratio of 2 ° + 3. For the general case, logic unit 3 is able to close positive feedback for any output code of divider 1. Each time after this, one input pulse is skipped, and the corresponding period of the first bit increases by one period of input pulses (this is the increment of one half-period), the other remains unchanged, because a positive feedback acts only on one static input of the 1st bit state installation. If divider 1. is an ordinary binary counter having a division factor of 2, then when the input pulse passes, the period of the first discharge increases 1.5 times, the maximum division factor for the general case of block 3 is 1.5 times the division ratio of the counter, as each period of the first digit is incremented. In the general case, divisor 1 can have any division factor not equal to 2, and then its maximum relative increment is less than 0.5 division factor of divider 1 if the half period with a logic level 1 exceeds half the period of the first digit. In order to achieve a relative increment above 0.5, a second loop of positive feedback is needed: with the help of the second logic block and an additional trigger. One of its variants is for the static input of the zero-point installation, with additional passes of the input pulses, which provide a dAH signal. the increment of the division factor corresponds to the extension of the same number of half-cycles of the first bit with a level of logical zero. Another option of positive feedback is to cover a group of older bits of the main frequency divider with it, observing the same basic principles as with coverage from the first bit and older. If the low-order bit is number 1, then the outputs of the i-ro bit or i-ro and any number of higher bits are connected to the inputs of the second logic block, and the output is connected to the static input of the unit (or zero) i-ro bit , the i-ro output of the bit is connected to the static unit installation input (or zero) of the second trigger, its dynamic count input or the dynamic input of the O (or 1) installation is connected to the dynamic count input-i-g6 of the discharge, the output of the second additional trigger is connected .to the input of the second combinational logic circuit s. The second feedback loop skips the output pulses (il) -ro of the bit and allows you to achieve a total division factor of 1, 52, 25 split factor divider 1, If the first feedback loop does not cover the first bit, then the second loop can cover more minor bits. When using a TTL trigger 2 and controlling it at the counting input, its internal delays can cause faults in the frequency divider. To avoid them, it is necessary between the output of trigger 2 and the input of logic unit 3 to include a delay element, such as an inverter, or instead of a dynamic counting input to use a dynamic setup input of trigger 2.

Trigger 2 unambiguously controls the feedback — it closes or opens it; therefore, for any logic block 3 structure, signals from its inputs should not pass to its output bypassing the control connection with trigger 2, which means that its output is connected to the input of one element AND, as in this device, or to the common input of several AND elements included in logical block 3. The remaining inputs of these elements are connected to the outputs of divider 1 either directly or through intermediate logic elements (AND, OR, ), however d There should be no connection with the outputs of the divider 1 bypassing the elements AND, the common input of which is connected to the output of the trigger -.

517116

The invention allows control of the division ratio by an external signal. Two variants of control inputs are shown in the drawing.

5 In the absence of an input pulse skip, trigger 2 briefly switches once in two periods of the first discharge, which causes additional consumption from the power supply. It can be avoided in two ways: by introducing a small delay of pulses arriving at the dynamic counting input (or the zero setting input) trigger 2 or by introducing into the circuit a direct connection of an additional logic unit.

The proposed device has a high speed and a wider range of variation of the dividing coefficient.

In addition, not only universal 1-K triggers can be used to implement the invention, but also any other types of triggers with a counting input.

Claims (2)

1. Lainov M.L., Kachaluba B.C., Ryzhkov D.V. Digital frequency dividers on logic elements. M., Energie, 1975, p. 66, fig. 3.136. 2 .. In the same place, with, 7, fig. 3.17. HU