SU1298902A1 - Synchronous frequency divider with 12:1 countdown - Google Patents

Abstract

The invention relates to a pulse technique and can be used in high-speed frequency division paths, such as frequency synthesizers. The aim of the invention is to increase the symmetry of the output signal. The device contains an input bus 1, tri1-hera 2 - 5 1K-type. In order to achieve this goal, an AND 6 element is introduced into the device. The device provides for dividing the frequency with division factors into three, six and twelve. The operation of the device is explained by the timing diagrams given in the description of the invention. 2 Il. (L iT i Code 7 - rf

Description

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The invention relates to a pulse technique and can be used in

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high-speed frequency division paths, for example, frequency synthesizers.

The purpose of the invention is to increase the symmetry of the output signal.

Figure 1 shows an electrical functional diagram of a synchronous frequency divider by twelve; 2 shows timing diagrams for his work.

Synchronous frequency divider for twelve contains an input bus 1 connected to clock inputs of the first 2, second 3, third 4 and fourth 5 triggers, each of which is 1K-type, the K-input of the first trigger 2 is connected to the bus logical one. nits, and the direct output is from the 1 input of the second trigger 3, the K input of which is connected to the bus, a logical unit, and the direct output is connected to the 1st K input of the third trigger 4, the inverse output of the second trigger 3 is connected with 1 input of the first trigger 2; The 1st K-inputs of the fourth trigger 5 are connected to the output of an AND 6 element, the first and second inputs of which are connected to the direct outputs of the first 2 and third 4, respectively, triggers, the output of the fourth trigger 5 is connected to the output bus 7.

Synchronous frequency divider for twelve works as follows. The bus 1 receives the input pulses (figa). Suppose that in the initial state all the triggers are in the zero state. Then, by dropping the first input pulse, trigger 2 switches to one state (FIG. 2b), and by dropping the second input pulse, trigger 3 switches to one state (FIG. 2b), and trigger 2 goes to zero, because trigger 2 is at that moment in the unit state and at its I- and K-inputs there is a logic level, one, g trigger 3 is in the zero state and on its I- and K-inputs there is also a level of logical one. By dropping the third input pulse to the output of the trigger 3, the logic zero level from the output of the trigger 2 is recorded, while the trigger 4 is switched to one state (Fig. 2d).

Next, the fourth clock pulse to the one state switch

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Trigger 2 and at the same time at the output of the element And 6 appears the level of the logical unit (the duration of one period of the input pulses). By dropping the fifth input pulse, trigger 2 returns to its initial state and a logic zero level appears at the output of AND 6 (fig. 2e). At the same time (at the time of the drop of the p input pulse) the level of the logical unit from the output of element 6 enters the I and K inputs of the trigger 5 and it switches to one state (Fig. 2e). The trigger 3 is also switched to one state (Fig. 2b). At the instant of decay of the sixth input pulse, the triggers 3 and 4 switch to the initial (zero) state (Fig. 2c, d). When this state of the trigger 5 does not change, since its I and K inputs are at a logic zero level. By dropping the seventh input pulse into one state, trigger 2 is switched. By dropping the eighth input pulse, trigger 2 is switched to zero, and trigger 3 is switched to one. By dropping the ninth input pulse, trigger 3 switches to the zero state, and trigger 4 switches to one. The trigger of the second pulse is switched off by the tenth input pulse to the one state, and the front of its second pulse appears at the output of element 6 (fig.2d). The trigger of the eleventh input pulse triggers to the zero state, the trigger 4 retains its previous single state because its I- and K-inputs at this moment are the levels of logical zero; the level of the logical unit acts on the I and K inputs of the trigger 5, which switches the decay of the eleventh clock pulse to the zero state (Fig. 2e). By dropping the twelfth clock pulse, all device triggers return to their original (zero) state.

Thus, at the outputs of the flip-flops 4 and 5 there are symmetric pulses, while providing a division factor of six and twelve, respectively. At the outputs of the flip-flops 2 and 3 there are pulses whose duration is equal to the duration of the period of the input frequency, thus providing a division factor of three.

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Claims (1)

Invention Formula A synchronous frequency divider for twelve, containing four flip-flops, each of which is 1K-type, the clock inputs of which are connected to the input bus, the K-input of the first trigger connected to the bus of the logical unit, the direct output - with the 1st input of the second the trigger, the direct output of which is connected to the I and K inputs of the third trigger, and the output bus, which is connected to the direct output of the fourth trigger aJ-lTLTLrin J inJ-lJ lJ J lJ-lJ Jl at A ger whose 1 input is connected to its K input, characterized in that, in order to increase the symmetry of the output signal, an I element is entered into it, the first and second inputs of which are connected to a straight 5K outputs of the first and third triggers, respectively. with the house of the fourth trigger, the 1 input of the first trigger is connected to the inverse output of the second trigger, the K input of which is connected to the bus of the logical unit. J ™ 1 Ch. .. ™. „.. T