SU1338065A1 - Pulse sequence frequency divider - Google Patents

Abstract

The invention can be used in devices of automation and computing, in frequency synthesizers. The invention provides an extension of the functional potential of the Divider to the pulse frequency by forming symmetrical output pulses and obtaining variable division factors. The divider contains triggers 1 and 2, the AND-HE element 3, the input bus 4, to which the clock pulses are applied, pin 5 of the control, with which the division coefficients are changed. When logic level is applied to bus 5, element 3 is blocked. At the same time, the zero cycle of trigger 1 by zero output from element 3 is excluded from the work cycle. 15 As a result, at the output of trigger 1 and 2, pulse sequences are formed, the period of which will be two and four, respectively times the period of the input frequency. 2 Il. i (L with from 00 about 05 JV

Description

1133

The invention relates to a pulse technique and can be used in automation and computing devices, in frequency synthesizers.

The purpose of the invention is to expand the functionality by ensuring the symmetry of the output pulses and obtaining 1 and 1 variable division factors.

Figure 1 shows the structural diagram of the device; 2 shows timing diagrams for his work.

Pulse frequency divider

owl contains the first I and second 2 triggers, the AND-HE element 3, the input bus A, which receives the clock pulses, 1MINU 5 of the control, which is used to change the division factors, the outputs of the first and second triggers I and 2 are connected to the first and second inputs of the li-HE 3 element, a third: the input of which is connected to the input bus A and to the clock input of the first trigger 1, the fourth input to the bus 5 of the control; the output of the NAND element 3 is connected to the reset input of the first trigger 1, the forward output of which is connected to the clock input of the second trigger 2, the outputs of the first 1 and second 2 triggers are connected to the first and second output pins 6 and 7, respectively.

The pulse frequency divider operates as follows.

Suppose that in the initial state the triggers 1 and 2 are set to zero, and to the bus 5, the unit is given a single logical level. Vhona pulse sequence with bus 4 enters the clock input of the trigger 1 and the third input of the element 3 (figure 2 a). The change in the states of the triggers occurs along a slice (trailing edge) of the pulses. The trigger trigger 1 triggered by the first impulse, it switches to a single state (Fig. 2b). The state of the flip-flop 2 remains zero, and at the output of the element 3 there is a single logic level. The trigger 1 returns to its initial state with the next pulse at its clock input, while the pulse 1 at the output of trigger 1 switches to trigger state 2 (Fig. 2c). The third input pulse causes switching to the trigte unit 1 state 1 (Fig. 2b). Exit status

Q

five

0

five

0

35

Q

45

50

55

the trigger 2 and the element 3 are not changed, and the three inputs of the element 3 are set to 1 logical levels. On the leading edge of the fourth input pulse, all four inputs of element 3 are set to a single logic level, element 3 switches (figure 2 d) and the signal of zero logic level from its output zeroes trigger I (figure 2 b). The trigger 2 also switches to the initial state through a cut of the pulse c, the output of the trigger 1 (Fig. 2c). Resetting triggers 1 and 2 triggers switching to the initial state of element 3 (Fig. 2 g). By the cut of the fourth input pulse, trigger 1 is again switched to one state (Fig. 2b), while state of trigger 2 does not change. The fifth input pulse causes the trigger I (fig.2 b) to switch to the initial state and the trigger 2 to the single state (fig 2 c).

In the future, the cycle of operation of the device is repeated.

As can be seen from the timing diagram (Fig. 2), at the outputs of the flip-flops 1 and 2, pulse sequences are formed whose period. respectively, 1.5 and 3 times the period of the input frequency,

I

When a zero logic level is applied to the bus 5, the element 3 is blocked, the device’s zero cycle of the trigger 1 signal from the output of the element 3 is excluded from the cycle of the device. In this case, at the outputs of the trigger 1 and 2, pulse sequences are formed, the period of which 2 and 4 times the input frequency period.

Claims (1)

Invention Formula A pulse frequency divider containing the first trigger, the clock input of which is connected to the input bus, the output to the first input of the NAND element, the second input of which is connected to the output of the second trigger, characterized in that in order to extend the functionality by ensuring the symmetry of the output pulses and obtaining variable division factors, the third and fourth inputs of the NAND element are connected respectively to the input bus and to the control bus, the output is with the reset input of the first trigger, the direct output of which is connected to the clock input of the second trigger. Editor A.Makovska Compiled by A.Sokolov Tehred I.Popovich Proofreader G ,. Reshetnik Order 4145/56 Circulation 90.1Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk iab., d. 4/5 Production and printing company, Uzhgorod, st. Design, And