SU1243128A1 - Pulse repetition frequency divider - Google Patents

Abstract

The invention relates to computing and is intended to synchronously divide the frequency of the input pulses by 2.5 and 5. The purpose of the invention is to improve the speed and stability of the device. The divider contains triggers 1 and 2 G-type, trigger 1 1K-type, input and output buses. The achievement of this goal contributes to the introduction. triggering a 1K-type trigger 4, an AND-NOT 5 element and the formation of new connections between the elements of the device. 2 Il. U 00 to 00

Description

one

The invention relates to computing and is intended to synchronously divide the frequency of the input pulses by 2.5 and 5.

The purpose of the invention is to increase speed and stability. FIG. 1 shows an electrical structural frequency divider; in fig. 2 - time diagrams that show his work.

Frequency divider. following impulses soderzkit. triggers 1 and 2 G-type, triggers 3 and 4 1K-type, element AND-NOT 5, while the C-inputs of all Triggers are connected to the input bus 6, the direct output of the first trigger 1 is connected in I) the second trigger input 2 and the S- and K-inputs tert: its trigger 3, the direct output of which is connected to the S-input of the first trigger 1, the inverse output of the second trigger 2 is connected to the first input of the first trigger .1, and the direct the output of the second trigger 2 is connected to the first input of the element AND-HE 5 and with the SI and K inputs of the fourth trigger 4, the direct output of which is connected to 5 - input the house of the second trigger 2 and the second input element AND-NOT 5, the inverse output of the fourth trigger 4 is connected to the 1 input of the third trigger 3, the output bus 7 is connected to the output of the element AND-HE 5.

The frequency divider works as follows. I

At the initial moment triggers 1-3

are in the unit state, and the trigger 4 is in the zero state. Bus 6 receives, for example, a symmetrical signal. Then, the leading edge of the first pulse of the input frequency (Fig. 2c.) At the time tl, the trigger 1 switches to the zero state (Fig. 2b); at time t2, the trailing edge of the first input pulse triggers 4 switches to one state (Fig. 2i), thereby enabling the flip-flop of trigger 2, and at time t3, the leading edge of the second input pulse triggers 2 to zero state (Fig. 2b), the zero level from the output of which, arriving at the S input of the trigger 4, prohibits the switching of the latter to the zero state. At time t4, the triggers 1 and 2 are in the zero state; the zero levels from the outputs of which arrive at the S-inputs of the triggers 3 and 4

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their switching by the (, -outputs, at the time t5 before} the first edge of the third input pulse, trigger 1 switches to the one state, this triggers the unlocking of the trigger 3, and at the time t6, the falling edge of the third input pulse triggers to the zero state (Fig. 2i, since this

the moment at its 1-input is the zero level, and at the K-input it is the unit level. The zero level from the output of trit – gera 3, entering the S input of trigger I, blocks its switching to the zero state via the C input. At time t7, the leading edge of the fourth input pulse is triggered by a trigger 2 (Fig. 2b), the unlocking

the trigger 4, which at the time t8, the trailing edge of the fourth pulse switches to the zero state (Fig. 2). At time t9, the triggers 3 and 4 are at zero.

state and block the switching of the flip-flops 1 and 2 by the input pulses on the S-inputs. At the moment tlO, the trailing edge of the p of the input pulse trigger 3 switches to a single

state (fig. 2 g), since

this moment on its I and K-inputs there are unit levels and triggers 1-3 are in a single state, and trigger 4 is in the zero state. Thus, the proposed device returned to its original state, after which the division cycle is repeated.

Claims (1)

Formula isobteni A pulse frequency divider containing three triggers, the C input of the first of which is connected to the input bus, the direct output to the information input of the second trigger, the inverse output of which is connected to the information input of the first trigger, and , with efficient) increase in speed and stability of operation, the element AND-NOT and the fourth trigger are introduced into it, the first and second triggers are D-type, the third and fourth are 1K-type, while the C-inputs of the second, the third and fourth triggers are connected with the input bus, the forward output of the first trigger is connected to the S and K inputs of the third trigger. The direct output of which is connected to the S-input of the first trigger. The direct output of the second trigger is connected to the first input of the NAND element, the output of which is connected to the output bus, as well as to the S-, 1st K-inputs of the four Editor L. Gratillo Compiled by A. Sokolov Tehred I. Veres Proofreader M. Maksimishinets Order 3718/57 Circulation 816 Subscription INPUTS USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, 4 of the trigger, the direct output of which is connected to the second input of the NAND element and S is the input of the second trigger, the inverse output with the G is the input of the third trigger. FIG. 2