SU1358080A1 - Apparatus for extrapolating time interval - Google Patents

Abstract

The invention can be used in the pulse, computing and other areas of electronic equipment. The purpose of the invention is to expand the functionality by allowing the second time interval to be multiplied in duration to the first, while at the same time increasing the reliability of operation by simplifying the device and eliminating the effects of the competitions. To do this, a trigger 5, a second element 2NE-IL 10, a third inverter 12, a reversing counter 14, and a single pulse generator 15 are additionally introduced into the device. In addition, the device contains a generator 1, a divider 2 frequencies, triggers 3 and 4, elements AND 6 and 7, elements OR 8, 2 NO-ШШ 9, inverters 11 and 13. Terminal 16 receives a Start signal, terminal 17 receives a signal Stop, at terminal 18 - a logical 1 signal, at terminal 19 - a signal Enable operation. The output signal is taken from terminal 20. Various extrapolation coefficients can be obtained by varying the counting frequency of the reversing counter 14. 2 Il. from 9 (L 170

Description

one

The invention relates to a pulse technique.

 The purpose of the invention is to expand the functionality of the possibility of counting the second time interval, which is a multiple of the duration of the first one, while simultaneously ensuring the reliability of its operation (in particular, by eliminating the appearance of performances and simplifying the device) Figure 1 shows the functional diagram of the device; 2, time diagrams of his work.

The extrapolation device is temporarily connected to the bus

The first interval contains a generator 1, a divider 2 frequencies, triggers 3-5, elements AND 6 and 7, element OR 8, elements 2НЕ-OR 9 and 10, inverters 11-13, a reversible counter 14, a driver 15 single pulses. Terminal 16 receives a Start signal, terminal 17 a Stop signal, terminal 18 a logical 1 signal,

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The device works as follows.

In the initial state at terminal 19, the zero signal. A single signal at the output of the inverter 11 sets the trigger 3 to the zero state, and a single signal at the output of the element 2HE-9 9 - a reversible counter 14

to terminal 19, the signal for resolution is 25 and trigger 5 is in the zero state. Edibota. The output signal is taken from terminal 20.

The output of the generator 1 is connected to a frequency divider 2, one of the outputs of which is connected to the input of the second element 6, the second input of which is connected to the output of the first trigger 3, in which one of the inputs is connected to the Start terminal 16 and the second connected to the output of the first inverter 11, the second trigger 4 is connected by the input to the terminal 17 Stop, the output is connected to the input of the second element And 7, and the first element. 2NE-OR 9 is connected by input with terminal 19 Work enable, and the output is connected to the second inverter 13.

The third inverter 12 is connected to the output of the second input of the first element 2NE-OR 9, the second input of which is connected to the input of the first inverter 11, the output connected to the first. the input of the first trigger 3, the third input of which is connected to the ground bus, and the fourth is connected to the first And 7 element in the course of the second element, the second input of which is connected to the second output of the frequency divider, and the output is connected to the input of the OR element 8, the second

A small signal at the output of element 2НЭ-ШШ 9 gives a zero signal at the output of the inverter 13, and at the output of element 2Е-OR 10 - a single signal,

30 which sets trigger 4 to the zero state. The zero signal at the output 21 of the trigger 3 prohibits the transmission of the signal by the element And 6, and the zero signal at the output 22 of the trigger 4 prohibits the transmission of the signal by the element 7. 7. The zero signal at the code 23 of the trigger 5 prohibits the generator of 15 single pulses, and the output 20. unit sig.40 cash is generated. The device is ready for operation.

After a single signal is applied to terminal 19, the device is allowed to operate, but it remains in the initial state until it arrives at terminal 16

45 single start signal, which sets the trigger, 3 to the single state, and through the inverter 12 and the element 2NE1 9, confirmation of the zero states of the trigger 5

50 and the reversible counter 14. A single signal at the output 21 of the flip-flop 3 enables the operation of the And 6 element and enables the reversing counter 14 to be counted in the forward direction. Output element

the input of which is connected to the output of the first 55 is formed by the first part of the clock element AND 6, and the output is connected to the output pulses arriving at the clock at the first input of the reversible counter input of the reversible counter 14. ka 14, the second input of which is connected to terminal output of the first trigger 3, the third 17 stop signal, which is switching 80802

the input of the counter 14 is connected to the input of the third trigger 5 and the output of the first element 2NE-OR, and the output is connected to the second input of the third trigger 5, the third input of which is connected to the trigger of the second trigger 4, and the output is connected to the input of the imager 15 single pulses, the output which is connected to the input of the second element 2NE- OR 10, the second input of which is connected to the output of the second inverter 13, and the output is connected to the second input of the second trigger 4, the third input koI111I

The device works as follows.

In the initial state at terminal 19, the zero signal. A single signal at the output of the inverter 11 sets the trigger 3 to the zero state, and a single signal at the output of the element 2HE-9 9 - a reversible counter 14

A small signal at the output of element 2НЭ-ШШ 9 gives a zero signal at the output of the inverter 13, and at the output of element 2Е-OR 10 - a single signal,

which sets trigger 4 to the zero state. The zero signal at the output 21 of the trigger 3 prohibits the transmission of the signal by element 6, and the zero signal at the output of the 22 trigger 4 prohibits the transmission of the signal by the element 7. The zero signal at code 23 of the trigger 5 prohibits the generator of 15 single pulses, and at the output 20. the device is formed unit sig. The device is ready for operation.

After a single signal is applied to terminal 19, the device is allowed to operate, but it remains in the initial state until it arrives at terminal 16

single start signal, which sets the trigger, 3 to the single state, and through the inverter 12 and the element 2Е-Ш1И 9 confirmation of the zero states of the trigger 5

and a reversible counter 14. A single signal at the output 21 of the flip-flop 3 enables operation of the element 6 and enables the counting of the reversible counter 14 in the forward direction. Output element

31358080.4

A trigger 5 is triggered to one state, is given after the Stop signal switches the trigger 3 to the zero state and enables the operation of the And 7 element.

time twice as long as the time between the signals P

Now, at output 24 of the LH B element, the second part of the clock pulses is formed (in Fig. 2 these are lower frequency pulses), and at the expense of the reversible 1} counter, the counts are made in the opposite direction.

After zeroing the reversible counter and further overflowing it (at the output of 24 low-frequency pulses one more than the low-frequency Stop (extrapolation coefficient is two). Thus, by changing the counting frequency of the reverse counter, different extrapolation coefficients can be obtained.

Claims (1)

Invention Formula A time interval extrapolation device containing a generator, an output, which is connected to a divider ) at the clock input of the trigger 5 at the frequency of 15, the first element I, the first blunt a single signal, switching the trigger, one of the inputs of which connects it to a single state, is terminated with the Start terminal, and the second approach. 23 a single signal appears, causing a zero output signal It is connected to the code of the first inverter, the second trigger connected by the input 20 devices. This zero signal, 20 having passed through the 2E-OR 10 element, becomes single and switches trigger 4 to the zero state, which leads to the inhibition of clock pulses, at output 24 of the element OR 8, and to the removal of the D-input of trigger 5 of a single signal. Since the front of the pulse switching the trigger 5 to the single state has already ended, such a removal with the terminal Stop, and the output connected to the input of the second element AND, the first element 2NE-OR, connected to the input with the terminal Work enable, and the output connected to the second inverter 25, differing in order to expand the functionality. at the same time increasing its reliability, the second element is introduced into the device a single signal from the D-input trigger-30 2NE-1111, element OR, reversive ° pa 5 leads, to its unstable counter, the third trigger, to form a single switch, those. Here, the occurrence of single pulses and a third inverter, connected to the output of the second element 2E-OR, is connected to the output In this way,. after the initial first input, the second input of which is connected to the input pulse at output 20 by the device of the first inverter, and the input to all its elements, except for trigger 5, returned to their original state. Being in the single state, the trigger 5 cannot already be switched to the single state, and the single pulse shaper 15 emits only one pulse after the appearance of a single signal at the output 23. Thus, the holding of the trigger 5 in the single 45 I element is connected to the input of the state it is possible longer than the element OR, the second input the first input of the first trigger, the third input of which is connected to the ground bus, and the fourth is connected to the first 40 input of the second element, the second input of which is connected to the second output of the frequency divider, the first output of which is connected to the first input of the first element, and the output is contributes to the absence of the device output spurious pulses. The setting (Uvka trigger 5 to the zero state occurs at the beginning of the next cycle of the device operation after the arrival of the Start signal. As can be seen from FIG. 2, due to the fact that the clock frequency of the countdown is two times lower than the direct counting, the pulse duration at the output 22 of the trigger 4 is twice as large as the pulse duration at the output 21 of the trigger 3, i.e. the output signal is given after the stop signal through time twice as long as between signals Start and Stop (the extrapolation coefficient is two). Thus, by changing the frequency of the reverse counting of the reversive counter, one can obtain different extrapolation coefficients. Invention Formula A time interval extrapolation device containing a generator, an output, which is connected to a divider frequency, the first element And, the first trigger, one of the inputs of which is connected to the Start terminal, and the second under It is connected to the code of the first inverter, the second trigger connected by the input with the terminal Stop, and the output connected to the input of the second element AND, the first element 2NE-OR, connected to the input with the terminal Work enable, and the output connected to the second inverter, different in order to expand the functional, the second input of which is connected to the input of the first inverter, and the input from the 45th element AND is connected to the input of the OR element, the second input of which the first input of the first trigger, the third input of which is connected to the ground bus, and the fourth is connected to the first 40 input of the second element And the second input of which is connected to the second output of the frequency divider, the first output of which is connected to the first input of the first element And, and the output is connected to the output of the second element And, and the output is connected to the first input of the reversible counter, the second input 50 which is connected to the output of the first trigger, the third input is connected to the first input of the third trigger and the output of the first element 2NE-OR, and the output is connected to the second output of the third 55 flip-flops, the third input of which is connected to, the second output of the second flip-flop, and the output is connected to the input of the driver of single pulse pulses, the output of which is connected to the input of the second pulse. 2E-IPI element, the second output to the second input of the second trigger, the third connected to the input of the second inlet whose input is connected to the tffepTopa bus, and the first output connected to the logical 1 Editor V.Danko Compiled by G. Bršski Tehred M. Dvdk Proofreader S. Cherni Order 6008/56 Circulation 900 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 2