SU1503061A1 - Pulse shaper - Google Patents

Abstract

The invention relates to devices for generating pulses corresponding to the leading and trailing edges of a convertible periodic pulse of a rectangular shape, and can be used in radio measuring devices. The purpose of the invention is to increase the accuracy and reliability of the former. For this, three elements AND 6-8, four elements OR 11-14 and six triggers 16-21 are entered into it. In addition, a pulse generator 1, elements AND 2-5, a frequency divider 9, element OR 10, trigger 15, input bus 22, output bus 24, tire 25 of zero potential. This ensures the appearance of the leading edge of the pulse on the output bus 24 with a possible delay relative to the front of the input pulse on the bus 22 by no more than half the period of the pulse generator signals, which improves the accuracy due to the absence of delay by delay blocks compared to the known driver. In addition, by ensuring the switching of the triggers only at the moments of arrival of the pulses of the pulse generator 1, the possibility of malfunctions is excluded and thus the reliability of the device is improved. 2 Il.

Description

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three elements AND 6-8, four elements OR 11-14 and six triggers 16-21, In addition, the generator includes 1 pulse generator, elements AND 2-5, frequency divider 9, element OR 10, trigger 15, input bus 22, the output bus 24, the tire 25 zero potential. This ensures the appearance of the leading edge of the pulse on the output 10 bus 24 with a possible delay relative to the front of the input pulse.

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On bus 22, it is not more than half the period of the signal generator pulse generator, which improves accuracy due to the absence of delay by delay blocks compared to the known driver. In addition, by ensuring the switching of the triggers only at the moments of the arrival of the pulses of the pulse generator 1, the possibility of failures is excluded and thus the reliability of operation of the device is increased. 2 Il.

The invention relates to devices for generating pulses corresponding to the leading and trailing edges of a rectangular periodic pulse to be converted, and can be used in radio devices.

The aim of the invention is to improve the accuracy and reliability of the device.

The goal is achieved by generating pulses along the fronts of the input signal with a possible delay of no more than half a period of the signal of the pulse generator, which ensures the accuracy of the device.

 Reliability is achieved by eliminating the use of delay blocks, each of which contains several consecutively connected logic elements, as well as by switching all the triggers only by pulses of the pulse generator.

Figure 1 shows the functionality of the pulse shaper circuit; n in FIG. 2 are timing diagrams explaining his work.

The pulse shaper contains a generator of 1 pulses, from the first to the seventh elements AND 2-8, the frequency divider 9, the first to the fifth elements OR 10-14, the first to the seventh triggers 15-21, the input bus 22, the pin 23 of the installation the output state of the pulse generator 24, the zero potential bus 25 is returned to the initial state.

The pulse shaper operates as follows.

On the setup bus 23, a pulse signal is supplied to the initial state, setting the frequency divider 9, the first to seventh triggers 15-21 to the initial state, in which low-level (logical O) signals are set at their outputs.

The input bus 22 receives a square-shaped signal (FIG. 2a). The pulse generator 1 generates a signal like a square wave (FIG. 26).

The formation of the pulse corresponding to the leading edge of the input signal (Fig.2A), is as follows.

The outputs of the third element And 4 act signals from the input bus 22 (Fig.2A), from the output of the generator 1 pulses (Fig.2B) and the inverse output of the fourth trigger 18 (Fig.2B). At the output of the third element And 4 a signal is formed (Fig. 2d), corresponding to the pulses from the output of the generator of the 1 pulses. Vkodnaya signal of the third, the element And 4 through the second element OR 11 enters the inputs of the fourth and fifth elements And 5 and 6 and the counting input of the second trigger 16. The inverse output of the third trigger 17 operates a logical signal 1 (FIG. 2h), which enters to the input of the fourth element And 5. At the output of the fourth element And 5 a signal is formed (Fig.2i), as a result of simultaneous influence of the signals (Fig.2g, h). The output signal of the fourth element And 5 (figs, 2i), the first trigger 15 is set to one state on the direct output (fig.2o).

The second trigger 16, to the counting input of which the output signal of the third element I 4 arrives (fig.2g), on the rear (falling) front of the first pulse of this signal is set to one state on the forward output (fig, 2d). At the output of the fifth element And 6, a signal is generated (Fig. 2g), by which the third trigger 17 is set to the one state (Fig. 2m) and to the zero state on the inverse output (Fig. 2z).

Simultaneously with the installation of the first trigger 15 in the single state, the sixth trigger 20 is established in the single state (Fig. 2n). The output signal of the sixth trigger 20 and the output signal of the pulse generator 1 is fed to the inputs of the first element 2, the output of which (FIG. 2 p) is fed to the counting input of the frequency divider 9.

By the falling edge of the second pulse of the output signal of the third element I 4 (FIG. 2d), the second trigger 16 is set to the zero state on the forward output (FIG. 2d) and to one state on the inverse output (FIG. 2e). On the back (falling) pulse front from the direct output of the second flip-flop 16, the fourth flip-flop 18 switches to the zero state on the inverse output (Fig. 2c). Therefore, the signal of the pulse generator 1 stops through the third element A.

In the frequency divider 9, there is an increase in the period of its input signal, for example, 4 times, as shown in FIG. 2. As a result, a pulse is formed at the output of the frequency divider 9 (FIG. 2d), at the rear (falling) front of which the sixth trigger 20 is set to zero (FIG. 2n). Therefore, the passage of the signal from the pulse generator 1 through the first element 2 to the counting input of the frequency divider 9 is stopped.

The pulse from the output of the frequency divider 9 (Fig. 2c) through the fifth element OR 14 enters the counting input from the seventh flip-flop 21. On the falling edge of this pulse, the seventh flip-flop 21 is set to one state (Fig. 2t) and the output signal is fed to the second element FROM, to the other entrance of which

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em impulse signal generator 1 pulses. Therefore, at the output of the second element I 3, a pulse is formed (Fig. 2y), which through the first element OR 10 sets the first trigger 15 (Fig. 2e) and the third trigger 17 (Fig. 2m) to the zero state. On the back (falling) front of the output signal of the second element And 3 through the fifth element OR 14 the seventh trigger. 21 is reset to its original zero state (Figure 2t).

Thus, at the direct output of the first trigger 15, i.e. At the output 24, a pulse is formed (Fig. 2o) corresponding to the leading (rising) front of the pulse from the input bus 22 with a duration determined by the frequency division factor of the frequency divider 9.

The formation of a pulse corresponding to the trailing edge of the input signal (Fig.2A), is as follows.

On the back (falling) edge of the signal from the input bus 22 (Fig. 2a, the fifth flip-flop 19 switches to the one state (Fig. 2k). The output signal of the fifth flip-flop 19 through the third miii 12 sets the fourth flip-flop 18 to the single state at the inverse output (Fig. 2c). At the same time, the signal from the output of the fifth flip-flop 19 is fed to the input of the seventh element 8, to another input of which the output signal of the pulse generator 1 is received (Fig. 26). At the output of the 7th element 8 the signal ( figl), which through the second element VDI 11 enters the inputs of the fourth 5 and the fifth 6 elements And on the counting input of the second trigger 16. Since a single signal acts on the other input of the fourth element And 5 (fig.2z), a pulse is formed at its output (fig.2i), on which the first The trigger 15 and the sixth trigger 20 are set to one (FIG. 2o, p). Setting the sixth trigger 20 to one state ensures the passage of the signal from the pulse generator 1 (FIG. 26) through the first element 2 (Figure 2p) to the counting input divider frequency 9.

On the back / (falling) front of the signal (first pulse) of the seventh element And 8 (Fig.2l) second trigger

16 switches to a single state on the forward output (FIG. 2e) and to a zero state on an inverse output (FIG. 2e). The impulse from the direct output of the second trigger 16 (figd) is fed to the input of the fifth element And 6, to the other input of which the signal comes from the output of the seventh element And 8 (fig.2l) through the second element OR 11 At the output of the fifth element AND 6, a pulse is formed (FIG. 2g), according to which the third trigger 17 is set to one state on the forward output (figure 2m) and to the zero state on the inverse output (figure 2h).

Along the trailing edge of the second pulse of the seventh element signal of the AND 8 (Fig. 2L) in the mountain, the trigger 16 switches to the zero (initial) state on the forward output (Fig. 2d) and to the unit state on the inverse output (Fig. 2e) . A single signal from the inverse output of the second trigger 16 (Fig. 2e) is fed to the input of the sixth element And 7, on the other input of which a single signal acts from the direct output of the third trigger 17 (Fig. 2m). At the output of the sixth element And 7, a signal is generated (FIG. 2n), by which the fifth trigger 19 is set to the zero state on the forward output (FIG. 2k), as a result of which the signal of the pulse generator 1 is stopped through the seventh And element 8 (Fig.2l).

In the frequency divider 9, the frequency of the signal arriving at its counting input, for example, 4 times, is divided, and a pulse is formed in the code (Fig. 2c). On the back (falling) front of this pulse, the sixth flip-flop 20 switches to the zero state (Fig. 2p), which stops the signal to the counting input of the frequency divider 9, and the seventh flip-flop 21 switches to the single state through the fifth ISH1 14 element (Fig .2t). The output signal of the seventh trigger 21 is fed to the input of the second element And 3, on the other input of which a signal from the output of the generator 1 pulses. In Rezul1) Tate, at the output of the second element I 3, a pulse is formed (fig. 2y), through which the first 15 and third 17 triggers are set to the zero state by the first element OR 10.

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my exit (Fig.2o, m). The sixth element And 7 is closed (FIG. 2n). On the rear (falling) front of the output pulse of the second element I 3 (fig. 2y), through the fifth element OR 14, the seventh trigger 21 switches to the zero state (fig. 2t).

At the direct output of the first trigger 15, i.e. At output 24, a second pulse (Fig. 2o) is formed, corresponding to the back (falling) edge of the pulse with input bus 22, with a duration determined by the frequency division factor of frequency divider 9.

Thus, at the output 24, pulses are formed, one of which corresponds to the leading (rising) front, the other pulse corresponding to the falling (falling) front of the rectangular signal from the input bus 22.

The pulse durations on the input bus 24 are determined by the division factor of the frequency divider 9 and can differ from each other by no more than half the pulse signal of the pulse generator 1, which is caused by the non-synchronism of the output signal of the pulse generator 1 and the signal from the input bus 22.

The appearance of the leading edge of the pulse on the output bus 24 is determined only by the moment of arrival of the first pulse from the output of the pulse generator 1. Therefore, the accuracy of the pulse former is due to the absence of delay by delay blocks in the known device.

In addition, by ensuring the switching of the triggers at the moment the pulses of the pulse generator 1 are increased, the reliability of the proposed device is improved compared to the known one, in which due to the delay spread of the delay blocks, malfunctions are possible.

Claims (1)

Invention Formula A pulse shaper containing the first, second, third and fourth elements AND, a pulse generator, the output of which is connected to the first input of the first element AND, the output of which is connected to the counting input of a frequency divider, the setup input of which has been reset to the first input of the first element OR and the setup bus to the initial state of the pulse former, the output of the first element OR is connected to the installation input to the zero state of the first trigger, the output of the second element AND is connected to the second input of the first OR element, characterized in that, in order to improve the accuracy and reliability of the former The second, third, fourth, fifth, sixth and seventh triggers, the fifth, sixth and seventh elements of AND, the second, third, fourth and fifth elements of OR are introduced into it, and the output of the pulse generator is connected to the first input of the third element AND , the output of which is connected to the first input of the second OR element, the output of which is connected to the first inputs of the fourth and fifth AND elements and the counting input of the second trigger, the setting input to the zero state of which is connected to the first input of the third OR element and the installation bus to the initial the pulse driver, the direct output of the second is connected to the second input of the fifth element I, the output of which is connected to the installation input in the unit state of the third trigger, the inverse output of which is connected to the second input quarter And, and the direct output - with the first input of the sixth element And, the second input of which is connected to the inverse output of the second trigger, the installation input in the unit state of which is connected to the bus of the zero potential and the installation inputs in the single state of the fourth, n - that and the seventh flip-flop, the counting input of the fourth flip-flop is connected to the direct output of the second flip-flop, the inverse output of the fourth flip-flop is connected to the second input of the third element, And the input to the zero input with Q 5 0 5 Q Q e five the fourth flip-flop state is connected to the output of the third OR element, the second input of which is connected to the direct output of the fifth flip-flop and the first input of the seventh AND element, the output of which is connected to the second input of the second OR element, the sixth element AND output is connected to the first input of the fourth OR element , the second input of which is connected to the installation bus to the initial state of the pulse generator, the input bus of the pulse generator is connected to the third input of the third element AND, the output of the fourth element OR is connected to the input setting to the zero state of the fifth trigger, the counting input of which is connected to the third input of the third element And, the second input of the seventh element And connected to the first input of the first element And and the first input of the second element And, the output of the fourth element And connected to the inputs of the installation in a single the state of the first and sixth flip-flops, the output of the frequency divider is connected to the first input of the fifth OR element and to the counting input of the sixth flip-flop, the direct output of which is connected to the second input of the first AND element, and the second element AND Inen with the second input of the fifth OR element, the output of which is connected to the counting input of the seventh trigger, the first input of the first OR element is connected to the inputs for setting the sixth and seventh triggers to the zero state, the direct output of the seventh trigger is And, the input installation in the zero state of the third trigger is connected to the output of the first, element N This OR, direct output of the first trigger is the output of the pulse former. FIG, g