SU1473076A1 - Pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for processing and generating pulse signals. The purpose of the invention is the extension of functionality, achieved by providing a pulse selection on the decline of the input signal and a series of pulses without pulses formed on the front and on the fall of the input signal. The shaper contains the key 1 with the memory of the control signal, RS - trigger 6, bus 7 clock pulses, information bus 8, three output buses 9-11. The introduction of an EXCLUSIVE OR 2 element, an inverter 3, two AND 4, 5 elements and two output buses 12, 13 allows the functionality of the former to be expanded: in addition to generating a pulse on the front of the input signal, a decay pulse can be distinguished, as well as a series without separable pulses. 2 Il.

Description

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The invention relates to a pulse technique and can be used in systems for processing and generating pulse signals.

The purpose of the invention is to expand the functionality due to the provision of a pulse on the input signal decay, a series of pulses formed on the front and a drop of the input signal, and a series of pulses without separable pulses.

Figure 1 shows an electrical functional diagram of a driver; 2 shows temporary diagrams of his work.

The pulse shaper contains a key 1 with a memory of the control signal, an element KSKLYUCHDEE OR 2, an inverter 3, two elements AND 4 and 5, an RS trigger 6, a bus 7 clock pulses, a control bus 8 and five output buses 9-13, and bus 8 control is connected to the first input element EXCLUSIVE NII 2, the input of the inverter 3 and the first input of the element 4, the output of which is connected to the bus 11 and the S-BXO- house of the trigger 6, the second input to the bus 9, the first input of the element 5 and the first output of the key 1, the second output of which is connected to the bus 10, the information input - with the bus 7 cycles pulses, and the control input - with the output of the EXCLUSIVE OR 2 element, the second input of which is connected to the reverse output of the RS flip-flop 6, the direct output of which is connected to the bus 12, and the R-input to the bus 13 and the output of the AND element 5, the second input of which is connected to the output of the inverter 3.

The pulse shaper operates as follows.

After supplying power, the device must be reset. Since it is known that it is necessary to force the sequential elements into one of the stable states after applying the supply voltage to them, additional. the reset input of the trigger 6 and the reset bus, by means of which the installation of the trigger 6 in O after supplying the supply voltage, is not shown in the functional diagram of the device. In the initial state, the bus 7 receives pulses of the clock frequency, and on buses 8, 9, A13 there are levels O. In accordance with I111I

level

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0 5 0 5 0

five

0

at the control key input 1, the clock pulses from the information input of the key 1 pass to its second output and are formed on bus 10.

The shaper operation is explained in timing diagrams that show signals at the following points of the flow chart: on bus 7 (a), on bus 8 (b), on the control input of switch 1 (c), on the second output of switch I, and on bus 10 ( d), on the first output of the key I and the bus 9 (d), at the output of the element I 4 and the bus 11 (e), at the direct output of the trigger 6 and bus 12 (g), at the inverse output of the trigger 6 (h) and output element And 5 and the bus 13 (i).

At the moment of formation on the bus 8 of the front of the control pulse at the outputs of the EXCLUSIVE OR 2. element and inverter 3 the O level is established. If the front of the control pulse is formed on the bus 8 during the action of the pulses on the tires 7 and 10, then the pulse on the bus 10 remains Its duration does not form on the tire 9 either, which is due to the properties. key with control signal memorization. Since the level O is set at the control input 1, the next clock frequency pulse passes to its first output, is formed on bus 9 (and does not form

on the bus 10) and goes to the exit ele1. , :

And 4, at the first input of which there is a level 1 from the bus 8. From the output of the element I 4 this impulse goes to the bus 11 and the installation input to 1 trigger 6, after which the trigger 6 is set to 1. On the bus 12 a pulse front is formed at the output of the item EXCLUSIVE OR

2 and the control key input 1 is set to level 1. In spite of the fact that during a pulse on tires 7 and 9 on the control key input

1, the voltage level changes from 6 to 1, the pulse on bus 9 maintains its duration and does not form on bus 10, which is due to the property of the key with memory

In accordance with

control signal

level 1 set at the entrance

control key 1, subsequent clock pulses pass from the information input of key 1 to its second output and are formed on bus 10.

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At the moment of forming on the bus 8 the decay of the control impulse on the outputs of the EXCLUSIVE OR 2 and inverter 3 elements are set respectively. About and 1. If the descent is controlled, the impulse is formed on the bus 8 during the impulses on the tires 7 and 10 , the pulse on bus 10 retains its duration and is not formed on bus 9, which is due to the key property with memorization of the control signal. Since the level O is set at the control input I, the next clock pulse passes to its first output, is formed on bus 9 (and is not formed on bus 10) and arrives at the output of element 5, the first input of which has a level of 1 sec. the output of the inverter 3. From the output of the element 5, this impulse goes to the bus 13 and the reset input of the trigger 6, whereupon the trigger 6 is set to O, the bus 12 forms a pulse decay, and the output of the EXCLUSIVE OR element and the control input of the key 1 is set to level 1 Level change Driving the control key 1 does not affect the pulses generated at that time on tires 9 and 13. In accordance with level 1., set at the control input of key 1, the next clock pulses often pass from the information input of key 1 to its second output and are formed on the bus 10. In this case, the device returns to the original state.

Thus, as a result of the cycle of operation of the device initiated by the arrival of the control pulse on the bus 8, a sequence of pulses of the clock frequency is formed on bus 0, without containing the pulses generated by the rhythm and decay of the control pulse, on bus 9, two pulses are formed with parameters clock pulses, with the first pulse

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the front impulses, and the second impulse - on the decay of the control impulse; on the bus 11, the impulse with the parameters of the clock frequency pulses is generated on the front of the control impulse; on the bus 12, a pulse is formed that corresponds to the control impulse and is synchronized along the front and in the slots of the clock frequency, On the bus 13, a pulse with the parameters of the clock frequency pulses is generated by the decay of the control pulse.

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Claims (1)

Invention A pulse shaper comprising a control signal storing key whose information input is connected to a clock bus, a control bus, an RS flip-flop, a direct output and an S input of which are connected respectively to the first and second output buses, the third output bus that is different the fact that, in order to expand the functionality due to the impulse implantation of the decay of the input signal, the series of pulses formed on the front and decay of the input signal, and the series of impulses without impulses, input and output waveforms, the fourth and fifth output buses, two AND elements, an inverter and an EXCLUSIVE OR element, the first input of which is connected to the first input of the first AND element, the input of the inverter and the control bus, the second input is inverse output RS-flip-flop, and the output -.c with the control input of the key with the storage of the control signal, the first output of which is connected to the third output bus, the second input of the first And element and the first input of the second And element, and the second output with the fourth output bus out one bus is connected to the output of the first element I, the R-input of the trigger is connected with the fifth output bus and the output of the second element I, the second input of which is connected to the output of the inverter.