SU1653144A1 - Pulse driver - Google Patents

Description

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with

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The invention relates to a pulse technique and can be used in systems for processing and generating pulse signals.

The purpose of the invention is to reduce the delay of the output signals.

FIG. 1 shows the functional electrical circuit of the device; in fig. 2 - time diagrams for his work.

The pulse shaper contains an EXCLUSIVE OR element 1, an inverter 2,, a switch 3 and 4 with a control signal, trigger 5, an information bus 6, a clock bus 7, and output bus bars 8-12, the bus 6 connected to the first the input of the EXCLUSIVE or 1 element and the control input of the key 4, the input of the Mode 2 of which is connected to the output of the EXCLUSIVE OR 1 element and the control input of the key 3, the information input - with the output of the inverter 2 and the information input of the key 3, the first output - 2 stroke - with the R-input of the trigger 5 and the bus 10, and the second output - with the bus 12 and with the S-input of the trigger 5, the direct output of which is connected to the bus 11, and the inverse output to the second input 3 of the EXCLUSIVE OR element, the outputs of the key 3 are connected to the corresponding buses 8 and 9, the input of the inverter is connected to the bus 7 clock pulses.

The device works as follows 3 times.

I

After power supply

The impulse terminal must be reset. In the CIL, the requirement of forcing the sequential elements into one of the stable states after supplying them with a supply voltage, an additional reset input at trigger 5 and a reset bus, by means of which the trigger 5 is inserted into O when the device is turned on. the functional diagram of FIG. 1 not shown. In the initial 5 state, the clock 7 arrives on the bus 7, on the bus 6 there is a level O, and the trigger 5 is set to 0. At the input of the Key 4 mode and the input of the control of the key 3, there are 1 levels, as a result of which the clock pulses the input of the key 4, its output is not passed, and the same clock pulses arriving at the information input of the key 3 are inverted by the key 3, are passed to its second output and are formed on the bus 9. On the tires 8, 10,

11 and 12 in this mode are levels O.

The operation of the device is illustrated by the timing diagrams of FIG. 2, which show signals at the following points of the functional diagram: on bus 7 (a), at the output of the inverter 2 (b), on bus 6 (c), at the output of the EXCLUSIVE OR element 1 (d), on the first (e) and the second (e) outputs of the key 4, on the forward (g) and inverse (g) outputs of the trigger 5, on the first (and) and second (k) outputs of the key 3.

On the leading edge of the impulse arriving at the bus 6, at the control input of the key 4 and the output of the EXCLUSIVE OR 1 element, levels 1 and O are set, respectively. In the event that the leading edge of the impulse on bus 6 is formed during operation. pulses on tires 7 and 9, then a pulse on tire 9 retains the duration of a pulse of tire 7, and on tires 8, 10, 11 and 12, no pulses are generated, which is due to the properties of keys 3 and 4. The next clock pulse passes to the second key output 4 and the first output of the key 3. In this case, the trigger 5 is set to 1 m, the leading edge of the pulse is formed on the bus 11, on the tires

12 and 8 are separated by a pulse, and at the output of the EXCLUSIVE OR 1 element, a level 1 is set, under the action of which further operation of key 4 is prevented and carried out through key 3, the subsequent clock pulses are transmitted from bus 7 to bus

9. In spite of the fact that during the operation of the pulses on buses 7, 12 and 8 at the input of Key Mode 4 and the control input of Key 3, the voltage level changes from 0 a 1, the pulses on tires 12 and 8 remain the duration of the bus pulse 7, and on the tires 10 and 9, the pulses are not formed, due to the properties of the keys 3 and 4.

On the falling edge of the pulse arriving at the bus 6, at the control input of the key 4 and at the output of the EXCLUSIVE OR 1 element - O levels are set. In the event that the falling edge of the pulse on bus 6 is formed during pulses on lines 7 and 9, a pulse at bus 9 maintains the pulse duration of bus 1, and on buses 8, 10 and 12, shortened pulses are not generated. The next clock pulse passes to the first outputs of the keys 3 and 4. At this, the trigger 5 is set to O, the tires 8 and 10 are given a pulse, the back edge of the pulse is formed on the bus 12, and the output level EXCLUSIVE OR 1 is set to 1 , under the action of which further operation of key 4 is prohibited and carried out via key 3, the transmission of subsequent clock pulses from bus 7 to bus 9. This completes the cycle of operation of the device and returns it to its original state.

Claims (1)

Invention Formula Pulse generator containing an inverter, clock bus, information bus connected to the first input of the element EXPEL five 0 five NOR OR, the second input of which is connected to the inverse output of the trigger, and the output - to the control input of the key with the control signal memorization, the first output of which is connected to the first output bus, and the second output - to the second output bus, R-input of the trigger is connected to the third an output bus, a direct output with a fourth output bus, and an S-input with a fifth output bus, characterized in that, in order to reduce the delay of the output signals, an additional key with a control signal is inserted into it, the control input of which is connected with in formation bus, mode input - with the output of the EXCLUSIVE OR element, the first and second outputs are connected to the third and fifth output buses, respectively, and the information input is connected to the information input of the main key, which stores the control signal and the output of the inverter, which input is connected to the clock pulse bus .