SU1285581A2 - Device for synchronizing pulses - Google Patents

Abstract

The invention relates to computing and can be used. used to assign asynchronous pulses to clock pulses. The purpose of the invention is to increase the reliability of the device in operation. The device contains a trigger 1, a generator of 2 pulses, counters 3 and 4 pulses and elements And 5-7. The introduction of a single pulse generator 10, the element OR 11, and the formation of new functional connections enable one to achieve the set goal. 2 Il.

Description

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The invention relates to computing, can be used to bind asynchronous pulses to clock pulses, and is an improvement to the device by the author. St. No. 1190501.

The purpose of the invention is to increase the reliability of the device in operation by forcing the formation of a pulse on the output bus of the device at the moment of the presence of a desynchronization signal.

FIG. 1 shows a block diagram of a device for synchronizing pulses; in fig. 2 - timing diagrams explaining the operation of the device.

A device for synchronizing pulses contains a trigger 1, a pulse generator 2, a first 3 and a second 4 pulse counters, a first 5, a second 6 and a third 7 AND elements, a synchronization bus 8, an output bus 9 of the device, a 10 single pulse generator, an OR OR element .

The input of the trigger 1 is connected to the first output of the first counter of 3 pulses, and the direct and inverse outputs are connected to the first inputs of the first 5 and second 6 And elements, respectively, and the output of the first And 5 element is connected to the counting input of the second counter of 4 pulses. The sync bus 8 is connected to the second input of the second element 6, the output of which is connected to the zero input of the first counter of 3 pulses, the counting input of which is connected to the output of the generator of the 3 pulses, and the second output connected to the second input of the first element 5 of the first input of the third element And 7, the output of which is connected to the reset input of trigger I, the inverse output of which is connected to the zero input of the second counter 4 pulses, the output of which is connected to the second input of the third element AND 7. The first input of the generator 10 is single and pulses coupled to the output of the second AND gate 6, a second input connected to the output of the generator 2 and the pulse generator output 10 is connected to the single-pulse to a first input of the OR gate 11, the second input of which is connected to the first output of the first counter 3 pulses, and the output

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element OR 1 1 is connected to the bus 9 of the device.

The device for synchronizing pulses works as follows.

Pulse counter 3 is a serially connected binary-decimal counters. From the first output of the counter of 3 pulses, pulses (FIG. 2 a) arrive at the counting input of trigger 1, the frequency of which is equal to the frequency of the pulses fed to the synchronization bus 8 (FIG. 2 b ),

With the arrival of each pulse at the counting input of the trigger 1, pulses are generated at its forward (FIG. 2) and inverse (FIG. 2 g) outputs, the duration of which is determined by a counter of 4 pulses and pulses from the second output of the counters of 3 pulses.

With the arrival of a pulse from the counter

3 impulses set the trigger 1 and through the open element And 5 (Fig. 2d) on the counting input of the counter

4 pulses are received from the second input of the counter 3; pulses. Suppose that the second input of the pulse counter 4 pulses is connected to the second input of the pulse counter of the element And 7 (Fig. 2e). Then at the output of the element And 7 we have a pulse (Fig. 2g) 5 by which the resetting of the trigger 1, and then the counter of 4 pulses, respectively.

If the pulse at the inverse output of trigger 1 (Fig. 2d) does not overlap the pulse arriving: on the synchronization bus 8 (Fig. 2b), then a pulse appears at the output of element 7, which zeroes the counter of 3 pulses. The next pulse, which arrives at the counting trigger input, is synchronized with the pulse, which arrives at the synchronization bus 8.

Changing the frequency of the pulses at the second output of the counter of 3 pulses, as well as changing the connection of the outputs of the bits of the counter of 4 pulses to the input of the And 7 element, allows you to pre-set the pin pulse accuracy.

at the appearance of a pulse at the output of the second element I 6, which indicates the pulses are out of sync on the synchronization bus 8 and on the first output of the first counter of 3 pulses, an ablation occurs

the first counter of 3 pulses, as well as the launch of the generator of 10 single pulses. At the same time through the element OR 11 to the output bus 9 of the device receives a pulse, the duration of which is equal to the following period; pulses at the output of the generator 2 pulses.

A generator of 10 single pulses provides a stable pulse duration to the output bus 9 for various pulse widths at the output of the I 6 element.

Thus, the loss of a pulse at the first output of the first counter of 3 pulses as a result of its zeroing does not lead to a disturbance of the sequence of pulses on the output bus 9 of the device. In addition, each pulse on the bus 8 synchronization

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corresponds to a synchronized pulse on the output bus 9.

Claims (1)

Invention Formula Device for synchronizing pulses auth. St. No. 1190501, t - it is distinctively that, in order to increase reliability, a single-pulse generator and an OR element are entered into it, the first input of a single pulse generator connected to the output of the second element And, the second input connected to the output of a pulse generator, and the output a single pulse generator is connected to the first input of the OR element, the second input of which is connected to the first output of the first pulse counter, and the output of the OR element is connected to the output bus of the device.