SU1363432A1 - Frequency-phase discriminator - Google Patents

Abstract

This invention relates to radio engineering and enhances noise immunity. The device contains inputs 1 and 2, four single-oscillators 3 and 4, 14 and 20, six I-NE 5.6, 15.16, 21 and 22, inverters 7 and 8, four trigger 9, 10, 17 and 18, four electrodes And 11-13 and 19, outputs 23 and 24. The device has two operating modes: frequency comparison mode and phase comparison mode. The transition from the 1st mode to the 2nd mode occurs automatically when the frequencies of the input sequences converge. 3 il. (L ig. 1

Description

The invention relates to radio engineering and can be used in devices for automatic frequency and phase control.

The purpose of the invention is to improve noise immunity.

Fig. 1 shows the electrical structural scheme of the frequency-phase discriminator; Fig. 2 shows the dependence of the fill factors on the first and second outputs; figure 3 - movement of the working point on the static phase characteristic.

The frequency-phase discriminator of the 5th and the fourth flip-flops 9 and 10, holds the first and second inputs 1 and 2, which ensures high accuracy of the first and second single-oscillators 3 and 4, the first and third elements AND-HE 5 and 6, the first and second the inverters 7 and 8, the trips in the zone of small phase mismatches, and failures are eliminated, when only one of these triggers is set to the zero state, and at the output of the other one there will be false information for the whole 21G period.

the third and fourth triggers 9 and 10, the first, the second and the third elements And 11 - 13, the third one-shot 14, the fifth and sixth elements AND-NOT 15 and 16, the first and second triggers 17 and 18, the fourth element And 19, the fourth one-shot 20, second and quarter elements AND-NOT 21 and 22, first and second outputs 23 and 24.

The frequency-phase discriminator works as follows.

The frequency-phase discriminator has two modes of operation: the mode of comparison of frequencies and the mode of comparison of phases. The transition from the mode of comparison of frequencies to the mode of comparison of phases occurs automatically when the frequencies of the input pulse sequences approach each other.

In the initial state, all the triggers are in the zero state. We assume that the pulse is sequential. On input 1, ahead of the pulse sequence on input 2. A pulse from input 1 formed by the first one-shot 3, the falling edge through the first inverter 7 sets the third trigger 9 into a single state and high potential from its direct output through the first element 11 prepares the third one-shot 14 to start and enters the first output 23 of the frequency-phase discriminator through the fifth and second elements AND-NOT 15 and 21, Impulse from the input 2, formed by the second single-oscillator 4s falling front through the second inverter In mouth navlivaet fourth flip-flop 10 is also a single state and with a high potential

its direct output through the first element And 11 triggers the third single-oscillator 14, which forms a short, pulse, which blocks the flow of high potential from the direct output of the fourth trigger 10 through the third element And 13 and interrupts the flow of high potential from the direct output the third trigger 9 through the second element I 12 to the first output of the discriminator. At the same time, the pulse of the third one-shot 14, acting on the inputs of the zero setting of the third and fourth triggers 9 and 10, ensures high accuracy

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work in the area of small phase diss; Clans are eliminated when only one of these triggers is set to the zero state, and at the output of the other of them there will be false information for the whole 21G period.

At the end of the pulse at the output of the third one-shot 14 from the second and third elements 12 and 13, the prohibition on passing signals from the main outputs of the third and fourth triggers 9 and 10 to the first and second outputs 23 and 24 is removed and the frequency-phase discriminator is ready to measure the phase error the next pair of inputs.

As a result, at the first output 23 of the frequency-phase discriminator there is a sequence of positive pulses, the duration of which exactly corresponds to the phase mismatch between the pulsed

Q sequences arriving at the first and second inputs 1 and 2 of the frequency-phase discriminator. This corresponds to the dependence of the filling factor of the pulse period J of the Sequence K at the first output 23 of the frequency-phase discriminator in the range of phase mismatches at the inputs 2 i (or in general, n2T-ig (n + 1) 2T, where n 0, ± 1, ± 2, ... (figure 2).

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If the pulse sequence on the first input 1 lags behind the pulse sequence on the second input 2, then the quarter trigger 10 will be triggered first, and return to the initial state after the third trigger 9 triggers. As a result, on the second output 24 there will be a sequence of positive pulses31

The coefficients whose duration exactly corresponds to the phase mismatch between the pulse sequences arriving at the second and first inputs 2 and 1 of the frequency-phase disc of the minator. In Fig. 2, this corresponds to the dependence of the filling factor of the pulse sequence period on the second output 24 of the frequency-phase discriminator in the range of phase mismatches at the inputs O S (-P 2 and (or in general, n2 i cf (n-1) 2 ir, where, +1, +2, +, ..) .. In the case of an increase in the frequency of the pulses arriving at the first input 1, the inverse trigger of the first trigger 17 sets the logical zero level, which through the second AND-21 element sets the logical level units on the first exit 23 and through the fourth and sixth the elements AND-NOT 22 and 16 sets the logic zero level at the second output 24, which corresponds to the discriminator's mode at its first output 23. Similarly, if the frequency of the pulses at the second input 2 increases, the logic level is set to the inverse output of the second trigger 18 zero, which through the fourth element IS-NOT 22 establishes the level of the logical unit on the second run 24 and through the fifth and fourth elements AND-NOT 15 and 22 sets the level of the logical zero on the first run 23, which corresponds to Modes saturation discriminator by its second outlet 24. In both cases, the operation proceeds to the comparison mode.

In the case of an increased pulse frequency at the first input 1 above the pulse frequency at the second input 2, a condition arises in which between two pulses at the second input 2 there are two pulses at the first input 1.- The first pulse at the first input 1 , formed by the first single-vibrator 3, through the first inverter-7 sets the third trigger 9 to one state, which allows i passing the second pulse of the first one-oscillator 3 through the first AND-NOT element 5. The second pulse on the first input 1, forms Rowan one first vibrator 3 through the leading edge

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The first element AND-NOT 5 sets the first trigger 17 to the single state, which leads to the appearance of the logic unit level at the first output 23 and the logic level zero at the second start 24, and after the fourth element And 19 prepares the fourth one-shot 20 for launch. As a result, the first and second outputs 23 and 24 become insensitive to changes in the state of the third and fourth triggers 9 and 10. When the sign of the frequency detuning changes, i.e. when the pulse frequency on the second input 2 becomes higher than the pulse frequency on the first input 1, between two pulses on the first input 1 there appear two 20 pulses on the second input 2. The first pulse on the second input 2 formed by the BTopbiM one-shot 4, protect - it is the front to set the fourth trigger 10 to one state,

25 which allows the second single vibrator 4 to pass through the third element AND – NOT 6. The second pulse through the second input 2, formed by the second single vibrator 4, through the third element. AND – NO 6 sets the second trigger 18 to the one state, which through the fourth element AND 19 causes the appearance of a short pulse at the output of the fourth one-shot 20 and zeroing the first and second triggers 17 and 18. At their inverse outputs, there appear levels of a logical unit that translate the frequency-phase discriminate p from the saturation zone in the phase comparing mode.

Similarly, the discriminator works with saturation on the second output 24.

Phase mode is characterized by -45 on the inverse outputs of the first and second triggers 17 and 18 levels of the logical unit. When the phases of the pulse sequences are equal in the first and second inputs 1 and 2, the gQ third and quarter triggers 9 and 10 are simultaneously set to one, the third one-shot 14 produces a short pulse that blocks the second and third elements from the second and third gates. passing high potentials from direct outputs of the third and fourth triggers 9 and 10 to the first and second outputs 23 and 24, and at the same time sets

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the third and fourth triggers 9 and 10 are in the zero state. As a result, there will be no signals at the first and second outputs 23 and 24, which n corresponds to a zero phase mismatch of the input pulse sequences.

The described operation modes of the frequency-phase discriminator correspond to the movement of the operating point according to the static phase characteristic shown in Fig. 3, where the frequency-phase discriminator is saturated at the first output 23 at point A, reaches point B and leaves the saturation zone not to the point О through point A, as it usually goes) and to the nearest point n2 1, where, i1, ± 2, + ... minimal phase mismatch. In this case, this is the point 2n1 | . This increases the speed of the discriminator. High accuracy of work in the zone of small phase mismatches, i.e. at points P 2 ir, where n 0, +1, +2, + ... and the elimination of failures when only one phase trigger is set to the zero state is achieved using the third one-shot 14 in the zeroing circuit and the fourth trigger 9 and 10.

Claims (1)

Invention Formula A frequency-phase discriminator containing a series-connected first one-way fiber, whose input is the first input of the frequency-phase discriminator, and the first AND-NO element, the first trigger, the installation input to which it is connected to the output of the first AND-NO element, and the second an IS-NOT element, the first input of which is connected to the inverse input of the first trigger, serially connected to the second one-oscillator, the input of which is the second input of the frequency-phase discriminator and the third IS-NE element, the second three the generator, the installation input in the unit state of which is connected to the output of the third NAND element, and the fourth NAND element, the first input of which is connected to the inverse output five 0 five 0 five 0 five 0 The house of the second trigger, characterized in that, in order to improve the noise immunity, the first And and the third single vibrators, the second And, the third input connected in series, the first input of which is connected to the inverse run of the third single vibrator, and the fifth And -NON, the output of which is connected to the second input of the second NAND element, the output of which is the first output of the frequency-phase discriminator, the third AND element serially connected, the first input of which is connected to the inverse output the third one-shot, and the sixth element IS-NOT, the output of which is connected to the second input of the fourth element IS-NOT, the output of which is the second output of the frequency-phase discriminator, the fourth element AND connected in series, the first and second inputs of which are connected to the direct outputs , the first and second triggers, and a quarter one-shot, the inverse output of which is connected to the inputs of the installation in the zero state of the first and second triggers, as well as the first and second inverters and the third and quarter triggers, with The input of the first inverter is connected to the output of the first one-shot, and the output is connected to the counter input of the third flip-flop, the output of which is connected to the first input of the first element I and the other input of the second element AND whose output is connected to another input of the first element NAND, the second the inverter is connected to the second one-shot code and the output is connected to the fourth trigger input, the output of which is connected to the second input of the first element And the second input of the third element And, the output of which is connected to the second input of the third unit About the NAND element, while the installation inputs of the third and fourth triggers are connected to the inverse output of the third one-shot, and the second inputs of the fifth and sixth elements AND-NAND are connected to the inverse, outputs of the second and first triggers, respectively. tt ii -2jr i / r,  Fig.Z Editor I. Segl Nick Compiled by E. Borisov Tehred M. Khodanich Proofreader A.Obruchar Order 6378/52 Circulation 900 Subscription BNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4