SU1231604A1 - Pulse repetition frequency divider - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in radio technology using in-phase and quadrature channels. The purpose of the invention is to expand the functionality achieved by providing a predetermined phase shift of the output pulses relative to the reference while maintaining a duty cycle of two. The frequency divider contains a pulse generator 1, triggers 2, 8, 9, logical elements, (LE) AND-NO 3.4 and 5, a pulse counter 6, a decoder 7, a division factor setting unit 10, an output bus 11. To achieve the set Target signal bus 12, second pulse counter 13, fourth trigger 14, phase key 15, phase discriminator 16, LE I 17 and switch 18 are entered into the frequency divider. 3 Il. i (L N3 CO O) o 4 FIG. t

Description

The invention relates to a pulse technique and can be used in a radio technique using an in-phase and quadrature channel .5

 The purpose of the invention is to expand the functionality of the frequency divider by providing a predetermined phase shift of the output pulses relative to the reference while maintaining the 11 rt borehole with the first phase input equal to two of the discriminator 16, the second input of the second trigger of the third trigger 9, Control input - with the first outputs of the second counter 13 pulses, the second output of which is connected to the counting input of the fourth trigger 14, the course of which is connected to the first input of the phase manipulator 15, the second input of which is connected n with the output of the second flip-flop 8, the output - with output shi

FIG. 1 shows the electrical structure of the proposed frequency divider; in fig. 2 and 3 are the time diagrams that show its operation when the frequency of the pulses of the reference signal is more and less than the frequency of the output pulses.

The pulse frequency divider contains a pulse generator 1, the output of which is connected to the first input of the first trigger 2, the second bypass of which is connected to the output of the first AND-NOT 3 element, to the first input of the second AND-NOT 4 element, whose second input is connected with the output of the third element IS-NOT 5 and with the third input of the first trigger 2, the output of which is connected to the counting input of the first counter of 6 pulses and the first input of the first group of inputs of the decoder 7, the remaining inputs of the first group of inputs of which are connected to the corresponding The signals of the first counter 6 pulses, the installation input of which is connected to the output of the second element AND-NOT 4 and the counting input of the second trigger 8, the first inputs of the first 3 and third 5 elements AND-NOT are connected respectively to the first and second outputs of the decoder 7, the second inputs of the first 3 and the third 5 elements AND-NOT are connected respectively to the first and second outputs of the third flip-flop 9, the first input of which is connected to the third output of the decoder 7, the dividing ratio setting unit 10, the output bus 11, the reference signal bus 12, the second counter 13 imp pulses, fourth trigger 14, phase handler 15, phase discriminator 16, element 17 and switch 18, the output group of which is connected to the second group of inputs of the decoder 7, the group of inputs to the corresponding outputs of the division factor setting unit 10, output

11 rt with the first input of the phase discriminator 16, the second input of the second trigger of the third trigger 9, Control input with the first outputs of the second counter 13 pulses, the second output of which is connected to the counting input of the fourth trigger 14, the output of which is connected to the first input of the phase manipulator torus 15, the second input of which is connected to the output of the second trigger 8, the output from the output bus

connected to the bus 12 of the reference signal, the first output with the first input of the second counter 13 pulses, the second input of which is connected with the output of the element And 17, the first input of which is connected with the second output of the phase discriminator 16, the second with the output of the second element And -NOT 4.

The pulse frequency divider operates in the following way.

The pulse sequence from the generator 1 output goes to the frequency divider formed by trigger 2 and counter 6. The output signals of this frequency divider go to the first group of inputs of the decoder 7, the second group of inputs through which switch 18 receives the code from the outputs of unit 10. The value of this code can change twice under the action of the signal arriving at its control input from the first outputs of the counter 13. At the output of the trigger 8 there is always a pulse whose duty cycle is equal to two. This impulse through the manipulator 15, for example, the element PERFORMING OR, is fed to the bus 11.

At a certain constant division factor N, the output signal of the pulse-following frequency divider (Fig. 2a) and the external reference signal (Fig. 2b) continuously flow to the inputs of the discriminator 16. Due to some difference in the frequency of these signals, the phase shift M exceeds the threshold value, for example 180, and at time t discriminator 16 is triggered, allowing receipt of pulses from the trigger input 8 coinciding in time through the element 17 to the second input of counter 13 (Fig. 2d) with the fronts of its output pulses.

The first impulse received at the second input of the counter 13 (Fig. 2e) causes the appearance of a signal at the control input of the switch 18 (). In this case, a code combination is shifted to the second group of inputs of the decoder 7 and to the input of the trigger 9, shifted by one bit towards the lower bits, which corresponds to the coefficient

divisions equal to 2 (with Ni) or -J- (with oddM).

As a result, the output pulses of the pulse frequency divider from time t have a duration approximately two times shorter than the initial one. However, after forming one such shortened pulse, the next pulse through element I 17 to the second input of counter 13 (Fig. 2e) comes from trigger input 8, the state of counter 13 changes, the initial input voltage level is set at control input of switch 18 (Fig. 2e), the second code group of inputs of the decoder 7 is supplied with the original code combination corresponding to the specified division factor N, and all subsequent output. The frequency divider pulses again have an initial duration. As a result, the phase shift jumps by about 90 ° and, if after that the value of H is in the range from 0 to 180, the discriminator 16 is reset to prohibit the input of the counter 13 of the input pulses of the trigger B to the second input, while The first input of the counter 13 is given a signal to install it to the original connection.

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If after the change in the phase shift H by 90 °, the value of H is outside the interval from 0 to 180 ° (Fig. 3), the further operation of the pulse frequency divider is as follows

Since the discriminator 16 is still in the state opposite to the initial state, the counter 13 continues to receive pulses from the input of the trigger 8 (Fig. 3d) and with the second input of the counter 13 of the third pulse starting from the time t (FIG. Zy) a pulse appears at the second output of the counter 13. This pulse (its leading edge) trigger 14

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55 florists are transferred to the opposite state, the group of inputs is with the corresponding outputs of the block for setting the division factor, the output is with the second input of the third trigger, which controls

that causes a change

180 phase of the output signal of the manipulator 15 (Fig. Over). Thereafter

the value of H is in the required range from 0 to 180 °, therefore, the discriminator 16 (Fig. 3b) and the counter 13 (Fig. 3b) are reset to the initial state.

The trigger 14 and, in turn, the manipulator 15 is not forcibly set in the initial state, and further the pulse frequency divider operates as described. Above until the phase shift η again falls outside the limits from 0 to 180.

Claims (1)

Invention Formula 15 20 25 thirty A pulse frequency divider containing a pulse generator, the output of which is connected to the first input of the first trigger, the second input of which is connected to the output of the first NAND element, to the first input of the second NAND element, the second input of which is connected to the output of the third AND element NOT with the third input of the first trigger, the output of which is connected to the counting input of the first pulse counter and the first input of the first group of inputs of the decoder, the remaining inputs of the first group of inputs of which are connected to the corresponding outputs The first pulse counter, whose installation input is connected to the output of the second NAND element and the counting input of the second flip-flop, the first inputs of the first and third AND-NES elements are connected respectively to the first and second outputs of the decoder, the second inputs of the first and third I-NO elements are connected respectively, with the first and second outputs of the third trigger, the first input of which is connected to tre-. the output of the decoder, the unit for setting the division factor and the output bus, characterized in that, in order to expand the functional capabilities by providing a predetermined phase shift of the output pulses relative to the reference, while maintaining a duty cycle equal to two, a reference signal bus 50 is inserted into it , the second pulse counter, the fourth trigger, the phase manipulator, the phase discriminator, the AND element and the switch, the output group of which is connected to the second group of inputs 40 input - with the first output of the second pulse counter, the second output of which is connected to the counting input of the fourth trigger, the output of which is connected, to the first input of the phase switch, the second input of which is connected to the output of the second trigger, output to the output bus and the first input of the phase discriminator second entrance expensively connected to the length of the reference signal, the first output - to the first input of the second pulse counter, the second input of which is connected to the output of the element I, the first input of which is connected to the second output of the phase discriminator, and the second input to the output of the second element NOT. a 5 C d e f llp Compiler A.Sokolov Editor A.Revin Tehred I.Popoich Proofreader L.Pilipenko Order 2660/57 Circulation 816 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 fig.Z