SU1287268A1 - Pulse sequence discriminator - Google Patents

Abstract

The invention 1 relates to a pulse technique and can be used in receiving devices of information-logic systems. The purpose of the invention is to expand the functionality of the device. The pulse sequence selector contains 1 clock; pulses, pulse counter 2, IK triggers 4 and 5, and element 7. The introduction of pulse counter 3, IK trigger 6, elements 8-10, and the formation of new functional connections enable the selection of the pulse sequence in duration. 1 interval between the series of pulses and the detection of discontinuities in the series. 2 Il.

Description

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The invention relates to a pulse technique and can be used in receivers of information logic systems for providing reception of information transmitted by a serial bipolar code.

The purpose of the invention is expansion. functionality due to the possibility of selecting a pulse sequence by duration, the interval between the series of pulses, the detection of gaps in the series.

Fig. 1 shows the structural electrical circuit of the proposed pulse sequence selector j in Fig. 2 — timing diagrams; which explain the operation of the device.

The pulse sequence selector contains a generator of 1 clock pulsesJ counters 2 and 3 pulses, 1K-flip-flops A-6., Elements AND 7-10 o The output of the generator 1 clock pulses is connected to the counting input of the first counter 2, the second counter 3, the control input the first 1K trigger AS, the output of which is connected to the first input of the first element I 7, the second input of which is connected to the input bus and the R input of the first counter 2, and the K input of the first 1K trigger 4 is connected to the first output of the first counter 2 TT. The 1 input is with the second output, and the K-code is with the third output, and the output of the first element I 7 is connected to the control input of the second and third, 1K flip-flops 5 and 6 and the R input of the second counter 3, the first output of which is connected with the first input of the fourth element And 10, the second output with the first input of the second element And 8, the third output with the R input of the second 1K flip-flop Sj and the fourth output with the V. input of the third 1K flip-flop 6, the inverse output of which is connected to 1 the input of the second 1K-trngger 5 and the first input of the third element I 9, the second input of which is connected to the direct output the house of the second 1K-flip-flop 5, the second input of the second element And 8 and the K-input of the third 1K-flip-flop 6, and the output of the second element And 8 is connected to the S-input of the third 1K-flip-flop 6, the output of the third element And 9 is connected to the counting input the first counter 2 and the second input kvadto20

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element 10, the code of which is the output bus

The device works as follows.

5 In the initial state, at the second input of the element AND 7 and R input of the counter 2 connected to the input of the device, there are no pulses, i.e. high potential flows. Subsequently, at the first output PD of the counter 2, connected to the K input of the trigger 4, a high potential and clock pulses from the generator 1 clock pulse output (Fig. 2a) to the counting inputs of the counters 2 and 3 and the trigger control input 4, the latter is set to O. From the forward output of trigger 4, the low-level potential (fig.2d) 5a enters the first input of element 7 and the output of element 7 connected to the control inputs of triggers 5 and 6 and the R input of counter 3, low potential The operation of counter 3 and signals from the third output p, trigger 5, and from the fourth output Uj trigger 6 is set to the state O, and therefore at the first inputs of the elements 8 and 9 and the K input of trigger 6 connected to the forward output of the trigger 5, the low-level potential, at the second input of the element AND 9 and the 1-input of the trigger 5 (Fig. 2g) connected to the inverse output of the trigger, 6, the potential is high, as the first inputs of the elements And 8 and 9 are low-level, then at the output of the element And 9 connected to the first input of the element And 10

40 and the enable input of the counter 2, the potential of the low level (Fig.2i) and also there are no signals at the output of the element And 8 connected to the 1-input trigger 6 and the output

45 element And 10 (fig.2n), which is the output of the device. The first inputs of the And 10 and 8 elements are connected respectively with the first PD and the second n outputs of the counter 3. Since the 50 count 2 is set to O, then on its second Hj and the third n outputs, combined with the 1 input and the input Installation in the On trigger 4 potentials low level. Unused inputs of the elements are connected to the common power rail.

When a pulse of a sequence arrives at the input of the proposed device, the negative field is p30

3

(fig.26), the operation of counter 2 is resolved. If the duration of the input pulse T "p. TO (where is the period of the clock pulses), then the second output of counter 2 does not show a signal (fig. 2b) and at the end of T the device will return to initial state. When the next input pulse arrives, counter 2 starts working again. If the duration of the second pulse, then after HJ cycles after the start of the input pulse, the second output of counter 2 (Fig. 2b) causes a high level signal and the next clock cycle trigger 4 will be set to state 1 (Fig.2d). If T „2 HgTo, then through Uj ticks on the third inset of counter 2 (Fig. 2d), the signal is received, the trigger 4 is set to the state O and at the end of the second input pulse of the device will return to its initial state I. 7 there will be no signal, i.e. pulses with duration less and more HjTo are not accepted for processing.

With the beginning of the third (Fig.26) input pulse, counter 2 is working again and if T ", then the second output from wired switch 2 turns on the clock signal and the next trigger 4 will be set to 1. If Tj, j P2To then at the end of the input pulse, the counter 2 is reset, and at both inputs of the element 7 there will be a high level until the next clock appears, which sets the trigger 4 to O (on its K input the high level signal is set to O counter 2).

When high level signals appear at both inputs of the element 7, a high level signal also appears at its output (Fig. 2e), with the leading edge of which counter 3 will be reset, trigger 5 will be set to 1, since The 1-input has a high level potential, and the state of trigger 6 does not change, since its I- and K-inputs have low-level potentials. At the same time, on both inputs of an AND 9 element at a TC, the potentials are high and the signal from its output will prohibit the operation of counter 2 and an element E 10 will open.

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the signal at the output of the element And 7, the counter 3 starts counting from the initial state and on the first clock pulse the signal at the first output of the counter 3 arrives at the second input of the element And 10, respectively, the signal at the output of the element And 10 appears (Fig .2n) which is the output of the device.

10 After several cycles, the signal at the second output of the counter 3 (Fig. 2k) arrives at the first input of the And 8 element, since at its second input there is a high level potential, then

15 shows a signal at the S-input of trigger 6, according to which it is set to state 1 (FIG. 2h). In this case, at the 1-input of the trigger 5 and the second input of the element And 9 will be, the potential of the low

0 level, respectively, the potential of the low level will be at the output of the element And 9, connected to the second input of the element And 10 and the input of the resolution of the counting counter 2. If before the arrival of the signal from the first output of the 3, the input pulse appears,

the duration of which is n, 1 T „: n2To then a signal is produced at the output of the element I 7, the leading edge of which

0, the counter 3 is set to the initial state, the trigger 6 is set to the state O, since at its K input there is a high level potential, and the state of the trigger 5 does not change and

J device will work as described. If there is no next impulse in the pulse train, i.e. the interval between pulses will be larger than the CR signal by the third output of counter 3 (fig.2l), the trigger 5 will be set to O and only the counter 3 will reset the signal corresponding to the input pulse of a predetermined duration signal from the output of the element 7 7, and The triggering of triggers 6 and 5 will not change, since there are low-level potentials at their I- and K-inputs. In the initial state

the device. will be returned only if there is a specified interval (GI) with a series of pulses, i.e. when on the second output of the counter 3 according to the VITS signal setting the trigger

5 6 to the initial state (fig.2m).

Claims (1)

Invention Formula A pulse sequence selector containing a clock pulse generator, the output of which is connected to the counting input of the first pulse counter, the first output of which is connected to the K input of the first IK trigger, the direct output of which is connected to the first BxofCy of the first element I, the second input of which is connected to the input bus and to the R inputs of the first pulse counter, and the output with a clock input of the second 1K trigger, characterized in that, in order to expand its functionality, a second pulse counter is introduced into it, the third 1K-tr gger, second, third and fourth AND gates, prichem.vyhod clock generator connected to the clock input of the first flip-flop and 1K counting input of the second counter pulses, the second output of the first counting-20 house of the counting resolution of the first pulse counter is connected to the 1st input of the pulses and the second input of the fourth to the first trigger, and the third output from that element whose output is in the R input of the first trigger, The output bus is the output of the device — the first element I is connected to the L-inlet. 25 | isi111111sht1111i1111111I11111111111111111Sh1shsh || 11p fft el the house of the second pulse counter and the clock input of the third trigger, and the first output of the second pulse counter is connected to the first input of the fourth element And, the second code is connected to the first input of the second element And, the third output to the R input of the second 1K flip-flop, and the fourth output from R -the input of the third 1K-flip-flop, the inverse output of which is connected to the 1-input of the second 1K-flip-flop and the first input of the third element And, the second input of which is connected to the direct OUTPUT of the second 1K-flip-flop, the second input of the second element And and the K-input of the third 1K -trigger a, and the output of the second element And is connected to the S-input of the third 1K-flip-flop, and the output of the third element And is connected to the input