SU1255957A1 - Phase shifter - Google Patents

Abstract

The invention relates to radio engineering. It can be used to create devices of exact discrete delay, for example, in receivers of radionavigation systems. The aim of the invention is to improve the reliability of the device. In the device containing the reference generator 1, the generator 2 of the pulse sequence; Tei, the switch 3, the block 4, the time reference, the reversible counter 5, the second switch 6, the element AND 7, the element OR 8, the buffer register 9, trigger 10 new connections. The operability of the device does not depend on the magnitude of the minimum delay elements. This increases the reliability of its operation, allows its use in devices where the requirements for reliability of operation are particularly high, for example, in synchronizers. 1 il. s (l

Description

one

The invention relates to radio engineering and can be found used when creating devices, accurate discrete delay, for example, in receivers of radionavigation systems.

The purpose of the invention is to increase the nuisance of operation of the digital phase shifter by ensuring its operability regardless of the minimum amount of delay of its elements.

The drawing shows a block diagram of the proposed device.

The phase shifter consists of a successively connected reference oscillator, generator 2 pulse sequences, the first switch 3, the output of which is the output of the phase shifter and is also connected to the first input of the time locking unit 4, the second input of which is the forward input of the reversible counter 5 t control inputs phase shifting. The information inputs of the first switch 3 are connected to the corresponding information inputs of the second switch 6, connected in series with the AND 7 element, the OR 8 element and the buffer register 9. The control inputs of the first switch 3 are connected to the outputs of the buffer register 9, whose information inputs are connected to the outputs of the reversible counter 5 and the control inputs of the second switch 6. The output of the temporary anchor block 4 is connected to the second input of the reversing counter 5 and through trigger 10 to the second input of the element 7. 7. th input of the OR gate 8 is connected to the input of the initial setup phase shifter and the second input flip-flop 10 - with output phase shifter.

The device works as follows.

When you turn on the yoke of the phase shifter until the arrival of the control signals at the second input of the element OR 8, a pulse signal is applied: initial setting. This signal: its front edge sets the buffer register 9 to the same state as the reversible counter 5. Due to this, the same codes are provided on the control inputs of the first switch 3 and the second switch 6. Pulse sequences appear at the switch outputs.

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Moreover, the sequence at the output of the second switch 6 by appropriately connecting the information inputs of the first switch 3 and the second switch 6 to the outputs of the sequence generator 2 is delayed. To obtain, for example, a 2T delay, it is necessary to connect the first information 10 input of the first switch 3 with the third, second with the fourth, the third with the first and the fourth with the second information inputs of the second switch - 6.

15. Let a control signal at the interval t - t, accompanied by a control signal Plus at the first input of the reversible counter 5, arrive at the second input of block 4 of temporal locking. A drop in this signal causes an edge of signal at the output of block 4 of temporal locking at time t,. As the signal of the time locking unit 4 decays, the reversing 25 counter 5 changes its state by one, and a resolving potential appears at the output of the trigger 10.

Suppose that the output of the second switch 6 is received by a sequence of the fourth type, and since at this moment the state of the counter 5 changes, after that the output of the switch 6 receives the sequence of the first type (the number of the pulse sequence is determined by the number of discrete time shifts relative to the pulses of the sequence received for the first) t The presence of a resolving potential from trigger 10 ensures the passage of the first pulse through the element AND 7, the element OR 8 to the control input b at the time tj records the code of the reversible counter 5 into the buffer register 9. Due to this, the output of the phase shifter begins to pass through the third type sequence, and the front of its first pulse returns to its original state 10. of block 4 of temporary binding, a control signal is received, accompanied by a control signal of Minus at the first input of the reversing counter 5. In this manner, a signal appears at the output of the block of temporary binding; There is a reversal count state35

45

50

chick.5 minus one. The fall of the signal at the output of the time reference block leads to the appearance of the resolving potential at the output of the trigger 10.

Changing the state of the reversible counter 5 ensures that the fourth sequence passes to the output of the second switch 6. The front of the first pulse of this sequence along the specified circuit provides a change in the state of the buffer register 9. From this moment on, the second sequence passes to the output of the phase shifter. The front of its first pulse returns to its initial state trigger 10.

Thus, the switching time in the phase shifter should not exceed the value

,

(one)

The value, in this case, is determined by the ratio

where is the time delay of each block with its corresponding number. In the proposed device, in order to ensure operability, it is necessary to observe the condition (1), the fulfillment of which is determined only by the speed of the elements used, i.e. only the choice of element base. The operability of the device does not depend on the magnitude of the minimum delay of elements. This increases the reliability of his work, allows its use in devices where reliability requirements

Editor O. Bugir Order 4818/45

Compiled by V.Shubin Tehred M.Hodanich

Corrector

Circulation 728 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5

Production and printing company, Uzhgorod, Projecto st., 4

Sharing is especially high, for example in time savers, synchronizers.

Claims (1)

Invention Formula Phaser containing serially connected reference generator, pulse sequence generator, whose outputs are connected to the information inputs of the first switch, the output of which is the device output and connected to the first input of the time-lag unit, the second input of which is the first input of the reversible counter entrances of the phase protection device,, and the output of the temporary anchor block is connected to the second input of the reversing a counter, characterized in that, in order to increase reliability, a second switch, the first input of the AND element, the first 1 st input the OR element and the buffer register, and the output of the temporary anchor block through  The trigger I input is connected to the second input of the I element, the information inputs of the second switch are connected to the corresponding outputs of the pulse sequence generator, the output of the reversible counter is connected to the control inputs of the second switch, and through the information inputs of the buffer register to the control inputs of the first switch, A trigger input is connected to the output of the phase shifter, and the second input of the OR element is the input of the initial setting of the phase shifter. Proofreader A. Obruchar