SU1225009A1 - Synchronous frequency divider with 10:1 countdown - Google Patents

Abstract

The invention relates to Qi $ 5th technique and can be used in the construction of chronizers, digital frequency synthesizers, etc. The purpose of the invention is to expand the functionality. The device contains 1K triggers 1-A, element 5, reset bus 6, clock bus 7 and output bus 8. Introduction to the device of the AND element and the formation of new connections between its elements makes it possible to obtain a transfer signal and a zero initial state and reduce the number of connections required to reset the device. 2 Il.

Description

The invention relates to digital technology and can be used in the construction of chronizators, digital frequency synthesizers, electronic clocks, etc.

The purpose of the invention is to enhance the functionality by obtaining a transfer signal and a zero source Vo state, while reducing the number of links required to reset the device.

FIG. 1 shows a functional diagram of the synchronous frequency divider by 10; in fig. 2 - time diagrams of the device, where a - input clock pulses on the clock bus; - signal Q f at the forward output Q of the first 1K flip-flop; o is the C 2 signal at the forward output Q „of the second IK flip-flop; (d) signal Qj at the direct output Q 5 of the third 1K flip-flop; signal Q on the forward Q input of the fourth 1K flip-flop; 6 - transfer signal at the device output.

Synchronous frequency divider by 10 contains even 1K-flip-flop 1-4 and item 5 I, reset bus 6, clock bus 7. The counting inputs of all 1K-flip-flops are connected to the clock bus 7 of the device, the inverse output of the second 1K flip-flop 2 connected to the K-input of the third 1K flip-flop 3, the inverse output of which is connected to I and K-: the inputs of the fourth III-flip-flop 4, the first and second inputs of the element 5 And are connected respectively to the direct output of the third 3 and the inverse output of the fourth 4 1K- the trigger, and the run - with the output bus 8 of the device, with the direct output of the fourth 1K-tr ggera 4 is connected to the 1-input of the first flip-flop 1K. 1, the direct output of which is connected to the 1-input of the third 1K-flip-flop 3, the direct output of which is connected to the K-input of the first 1K-flip-flop 1, the inverse output of which is connected to the 1-input of the second IK flip-flop 2 K- the input of which is connected to the direct output of the fourth 1K flip-flop 4.

With the indicated connection scheme of the elements, the logical equations of the I and K inputs of all 1K triggers are the frequency divider by 10 following

i (Q4;,;,; 14

K, Q ,; .K, Qi; TO,

By impulse reset on bus 6 reset all 1K-triggers device

reset to their original zero state. In this case, the states of the outputs are equal (Fig. 2 when)

Q, Q, Q,.

Based on the logical equations for the I and K inputs of the device, the state of the inputs is as follows

ten

T P T P 1. -h x 2 And

 H.

T p p

J-5 1, - and,

K, Q,

V n n 1

. 4j I 4-43- I

Ha FIG. 1 and 2, it is assumed that the IK triggers are switched to the opposite state by a negative signal difference at the counting input.

On the first clock pulse, the first 1K-trigger 1 does not change its state (as in the initial state when it has 1,), the second 1K-trigger 2 switches to the state of logical unity 1 (as when,), the third The 1K-trigger 3 will not change its state (since when, and the first clock pulse only confirms its zero state), the fourth 1K-trigger 4 will switch to the opposite, one, state (as when), and outputs (diagrams on, fig. 2 at) become equal

Qj, Q,. Input states change

  one,

  K,

As a result, after the second clock pulse, the device enters the second state (Fig. 2 at), characterized by the following values of the outputs and inputs

  Q,

I,

t i-) i,

55

to to V 1. V f Z 9 4

On the third clock pulse, the device will switch to the third connection (Fig. 2 at);

l 11ch1. 1 P n P 1

1 Z 3 4

Considering the operation of the synchronous frequency divider by 10 in the same way further, we obtain all its states for all 1.

On the ninth clock pulse, the device enters a ninth state in which

   Q,.

and coincidence of the signals occurs

Q 1

at the inputs of the element 5, at the output of which (on the output bus 8) the transfer signal is generated

P Q, Q 1,

the level of logic 1 which is held for the entire ninth cycle of the device. At the tenth input clock pulse, the device returns to the initial state (Fig. 2, at), the match is broken, and on bus 8 a negative differential of the P-transfer signal is generated, under the action of which the other frequency divider connected by bus 8 switches to its next state.

Using the proposed synchronous frequency divider by 10 will allow you to get a device with a small number of elements and circuit connections, in which, thanks to element 5, it can be used to increase the frequency division factor rf other frequency dividers, and

094

The proposed connection scheme Qj of the inputs and 1 and Kj of the inputs of the 1K-flip-flops can be used by the 1K-flip-flops having only the R inputs of setting the flip-flops to the zero state, since in the initial state all the 1K-triggers can be in the zero state in contrast to the known device where it is necessary to install triggers in both the zero and one states.

Claims (1)

Invention Formula A synchronous frequency divider by 10, containing four 1K-flip-flops, the counting inputs of each of which are connected to the clock bus of the device, the inverse output of the second IK-flip-flop is connected to the K-input of the third 1K-flip-flop, the inverse output of which is connected to I and K- the inputs of the fourth IK flip-flop, characterized in that, in order to expand the functionality by providing the possibility of obtaining a transfer signal and a zero initial state of the device, an AND element is entered into it, the first and second inputs of which are connected respectively with the direct output of the third and inverse output of the fourth 1K-flip-flops, and the output of the element I is the transfer output of the device, while the direct output of the fourth 1K-flip-flop is connected to the K-input of the second 1K-flip-flop and with the 1-input of the first 1K-flip-flop The direct output of which is connected to the Y-input of the third 1K-flip-flop, the direct output of which is connected to the K-input of the first 1K-flip-flop, the inverse output of which is connected to the 1-input of the second IK-flip-flop. 0123 56789 FIG. 2 Compiled by S. Klevtsov Editor I. Segl nick Tehred O. Sopke Order 1964/58 Circulation 816 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch PPP Patent, Uzhgorod, st. Project, 4 Proofreader M. Demchik Subscription