SU1370782A1 - Pulse repetition rate divider - Google Patents

Abstract

The invention can be used in the construction of frequency synthesizers and allows you to expand the functionality of the device. A frequency splitter contains N bits, each of which includes 1K triggers 1-1, 2-1, 1-2, 2-2 and 1-3, 2-3. The introduction of the resistor 5 and in each bit of the elements OR-NE 3-1, 3-2, 3-3, the elements AND-NOT 4-1, 4-2, 4-3 and the formation of new functional connections provide control of the division factor and increasing it by submitting a control code. In addition, the device has a regular structure, which allows its use in microelectronic technology. 1 il. $ C /)

Description

8-1

8-2

Sv

8-3

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The invention relates to a pulse technique and can be used in the construction of frequency synthesizers.

The purpose of the invention is to expand the functionality by providing control of the division factor.

The drawing shows an electrical functional diagram of the pulse frequency divider.

The device contains N bits (in this case) consisting of the first and second 1K-flip-flops (respectively for the first bit 1-1 and 2-1, for the second bit 1-2 and 2-2 and for the third bit 1-3 and 2-3); in each bit, the direct and inverse outputs of the first 1K flip-flop 1-1, 1-2 and 1-3 are connected respectively to the T and K inputs of the second 1K flip-flop 2-1, 2-2 and 2-3 To-inputs of which are connected to the first input of the element OR-NOT 3-1, 3-2 and 3-3; in each bit, the output of the NAND element 4-1, 4-2 and 4-3 is connected via a resistor 5 to the power bus and directly to the I and K inputs of the first 1K trigger 1-1 of the first bit; Each N-bit has a sync input, i.e. C-inputs of the first and second 1K-flip-flops connected to the bus 6 clock pulses; the first input of the NE-4-1, 4-2 and 4-3 element is connected to the corresponding bit 7-1, 7-2 and 7-3 of the dividing ratio code bus; the second input is connected to the I- and K-inputs of the first 1K- trigger 1-2, 1-3 of the subsequent discharge and with the output of the element OR — NOT 3–1, 3–2, and 3–3, the second input of which is connected to the direct output of the second 1K flip-flop 2-1, 2-2 and 2–3 and the corresponding discharge levels of 8–1, 8–2, and 8–3 of the output bus.

The device works as follows.

In each discharge with the appearance of a pulse on bus 6, the first 1K-trngger 1-1, 1-2 and 1-3 are switched to the opposite state only if there is a level of logical unit at its I- and K-inputs; while at the output of the second 1K flip-flop 2-1, 2-2 and 2-3, operating in the D-flip-flop mode, a logic level is set corresponding to the state of the first 1K flip-flop 1-1, 1-2

R

0

five

and 1-3. With the help of the element OR-NOT 3-1, 3-2 and 3-3, a transfer signal is generated, which ensures the operation of the subsequent discharge.

Regardless of the number of bits of the pulse frequency divider, an OR-NOT high bit element for a period of output pulses has at its output a single state only once, the second element from the high one – two times, etc. The appearance of single signals at both inputs of any of the elements AND-NOT 4-1, 4-2 and 4-3, the outputs of which form MOUNTING OR, prohibits the switching of the first IK-trigger 1-1. The number of such prohibitions is determined by the code on bits 7-1, 7-2, and 7-3 of the bus of the dividing ratio code 0, which gives an increase in the ratio (the division factor, which, with zero

ij

the code value is 2, an amount equal to 1, 2 ..., 2 -1.

Claims (1)

This device provides an increase in the division ratio by supplying a control code; it has a regular structure, which allows its use in microelectronic technology. 0 claims A pulse frequency divider containing N serially connected bits, the synchronization inputs of which are connected to the clock pulse bus and each of which contains two 1K-flip-flops, the direct and inverse triggers of the first of which are connected respectively to the I- and K-inputs of the second 1K- a trigger, characterized in that, in order to expand its functionality, a resistor is inserted into it and in each of the N-bits an OR-NOT element and an AND-NOT element, the first input of which is connected to the corresponding bit of the coefficient code d laziness, the second input - to the output of OR-NO element and I- and K inputs Q of the first 1K-trigger of the subsequent discharge, output - with the I- and K-inputs of the first 1K-trigger of the first discharge and through a resistor with a power bus, with the first 5, the input element OR is NOT connected to the K input of the second TC trigger, the direct output of which is connected to the second input of the element OR NOT and the corresponding output of the output bus. five 0 five