SU1188883A1 - Counting device with check - Google Patents

Abstract

1. ACCOUNT CONTROL DEVICE, containing the input bus, a binary n-bit counter, two AND elements, the OR element, a pulse selector for duration, n-bit one-shot, n-1 logic unit and an additional one-shot whose input is connected with the input bus and with the counting input of the binary p-bit counter, the direct output of each bit of which is connected to the first input of the corresponding one, its bit single-oscillator, the direct outputs from the first through n-1 bit single-oscillators are connected respectively to the first inputs of ne pvogo on p-1st logic blocks, the second inputs of which are connected respectively to direct outputs from the second to the nth discharge one-oscillators, the outputs of logic blocks connected to the corresponding inputs of the OR element, the output of which is connected to the input of the pulse selector by duration, pr My output of the one-shot one-shot is connected to the first input of the first element I, characterized in that, for the purpose of simplification, the inverse outputs of the bits of the binary n-bit counter are connected respectively to the second inputs of the bits one novibrators, the second inputs from the first to the nth digit single-oscillators are connected respectively to the third inputs from the first to the nth logical blocks, the fourth inputs of which are connected respectively to the inverse outputs from the second to the nth digit single-vibrators, the direct input of the first bit the one-shot one-shot is connected to the first input of the second element I, the inverse outputs of the first bit and the additional one-shot are connected respectively to (L the second inputs of the first and second elements I, the outputs of which are connected to additional Additional inputs of the OR element. 2. The device according to claim 1, characterized in that each logic unit contains an AND-OR element and an AND-NIA first, second inputs and an output of which are connected respectively to the first, third inputs 00 00 00 00 00 logical blocks and to the first input the first AND structure of the AND-OR element, the second input of the first AND structure, the first, second, third inputs of the second AND structure and the output of which are connected to the second, fourth, third, first inputs and output of the logic unit, respectively.

Description

The invention relates to automation and computing and can be used in digital devices that require the rapid detection of binary meter failures during their operation.

The purpose of the invention is to simplify the counting device with control by eliminating a number of design features.

The drawing shows a diagram of a three-digit counting device with a control.

In the drawing: input 1, binary three-bit counter 2, bit one-shot 3-1-3-3, additional one-shot 4, elements 5 and 6 AND, logical blocks 7-1 and 7-2, element 8 OR, selector 9 pulses in duration. Each of the logical blocks 7-1 and 7-2 contains the element 10 AND-OR and the element 11 AND-NOT. The input of an additional one-shot 4 is connected to an input 1 and to a counting input of a binary three-bit counter 2, the direct outputs of the first to third bits of which are connected respectively to the first inputs of the discharge one-shot 3-1-3-3, the direct outputs of the discharge one-shot 3-1 and 3-2 are connected respectively to the first inputs of logic blocks 7-1 and 7-2, the second inputs of which are connected respectively to the direct outputs of the discharge one-shot 3-2 and 3-3 outputs of logic blocks 7-1 and 7- 2 are connected respectively with the first and second input element 8 OR, the output of which is connected to the input of the selector 9 pulses in duration, the direct output of the additional one-vibrator 4 is connected to the first input of the element b I. The inverse outputs of the first to third bits of the binary counter 2 are connected respectively to the second inputs of the single-discharge one-vibrators 3 -1 and 3-3, the second inputs of the bit single-shot 3-1 and 3-2 are connected respectively to the third inputs of logic blocks 7-1 and 7-2, the fourth inputs of which are connected respectively to the inverse inputs of the bit single-shot 3-2 and 3 -3, pr m The first input of the one-shot discharge 3-1 is connected to the first input of element 5 I, the inverse outputs of the discharge single-shot 3-1 and additional one-shot 4 are connected respectively to the second inputs of the elements 6 and 5 And whose outputs are connected to the additional inputs of the element 8 OR. In each logical block 7-1 and 7-2, the first, second inputs and output of element 1 AND-NOT are connected respectively to the first, third inputs of the logical block and to the first input of the first structure AND element 10 AND-OR, the second input of the first structure AND, the first, second, third inputs of the second structure And and the output of which is connected respectively to the second, fourth, third, first inputs and output of the logic unit.

Counter 2 operates in summing mode. When the K th bit of counter 2 is in the "O (or" 1) position, its forward and inverse outputs are respectively of the "O and" 1 (or vice versa) signal. When the state of the K-th digit of the counter 2 changes at one of the inputs of the corresponding one-shot one-shot 3, the signal "O changes to signal" 1, with the result that at its forward and inverse outputs appears "single and" zero pulses. After that, the one-shot 3 again occupies the initial state (on the direct output - "O, on the inverse -" 1). In the absence of pulses on the forward and inverse outputs of the one-oscillator 4, respectively, there are signals "O and 1. When the leading edge of the counting pulse arrives at the input bus 1, the discharge of counter 2 begins to change its state, on the forward and inverse outputs of the oscillator 4 The "single and" zero pulses appear, respectively. Duration Ta. pulses generated by single vibrators 4: 3-1-3-3, exceeds the time Tv. transients in counter 2. At the output of the selector 9, an error pulse appears

5 of counter 2, if a pulse arrives at the input of the selector 9, the duration T of which is greater than or equal to That T „-T„.

The counter with control works as follows.

0By error (failure) shunt

counter 2 means the following types of faults: there was no counting pulse, and the first discharge of counter 2 changed its state (a); the counting pulse was, and the first discharge of counter 2 did not change its state (b) for the Kth bit, the transition from “1 to” O did not take place, but despite this (), the bit changed its state ( at); for the Kth bit, there was a transition from "1 to" O, but, despite this (), the Q time did not change its state (d).

The discovery of a failure of species (a) - (d) is a sufficient condition for the detection of any kind of failure of a summing binary counter. So, for example, if in the absence of a counting pulse, the second discharge of counter 2 changes its state from "1 to" 0, and the first discharge and third discharge of counter 2 does not change its state, then a failure of the counter is detected from —for detection (of the cumulative form (c) (since it can be considered for the first bit, and for the second

0 bit 2 K-1) and the type (g).

A failure of form (a) is detected as follows. There was no counting pulse (i.e., the “1” signal is present on the inverse output of the one-vibrator 4)

The bit has changed its state (i.e., a single pulse at the direct output of the one-shot 3). From the output of the element 5 And through the element 8 OR to the input of the selector 9 receives a pulse of duration t and

(since Tu and To), at the output of the selector 9, the signal of the counter 2 appears.

A failure of type (b) is detected as follows. The counting pulse was (i.e., a single pulse appeared at the forward output of the one-shot 4), and the first discharge of counter 2 did not change its state (i.e. a signal is present at the inverse output of the one-shot 3-1). From the output of the element bI, through the element 8 OR to the input of the selector 9 a pulse of duration T "arrives, and at the output of the selector 9 a counter 2 signal appears.

A failure of form (a) is detected as follows. Let be . For the first bit, the transition from "1 to" O did not take place (i.e., the first bit either did not change its state at all, and this corresponds to the signal "O at the direct output of the 3-1 one-shot, or the first bit went from state “O to state” 1, but at the inverse output of the first bit of counter 2, respectively, the signal “O, i.e., the output of element 11 of IS-NOT of block 7-1 occurs practically all the time

The signal "1, a (K4-1)" and the bit has changed its state (i.e. a single pulse appears at the direct output of the one-shot 3-2). At the output of element 10 AND-OR, a pulse with a duration longer than or equal to T0 appears, as a result, at the output of the selector 9, the signal of counter 2 appears.

A failure of type (b) is detected as follows. Let be . Let the first bit

counter 2 has moved from "1 to" O (i.e., the inverse output of the first discharge of counter 2 generates a signal 1, and a single pulse appears at the forward output of the one-vibrator 3-1), and the second discharge of the counter has not changed its state (on the inverse output of the one-shot 3-2 signal "1" is present). At the output of element 10 AND-OR, a pulse with a duration greater than or equal to T0 appears, as a result, at the output of the selector 9 a signal

counter 2.

The proposed device detects all possible types of summing binary counter failures.

Claims (2)

1. ACCOUNT DEVICE WITH CONTROLLER containing an input bus, a binary η-bit counter, two AND elements, an OR element, a pulse selector in duration, η-bit single-vibrators, η – 1 logic unit and an additional single-vibrator, the input of which is connected to the input bus and to the binary binary η -digit counter, the direct output of each discharge of which is connected to the first input of the corresponding one-shot bit, the direct outputs from the first to η – 1 bit one-shots are connected respectively to the first inputs from the first to η — first logical blocks kov, the second inputs of which are connected respectively to the direct outputs from the second to the fifth digit single-vibrators, the outputs of the logic blocks are connected to the corresponding inputs of the OR element, the output of which is connected to the input of the pulse selector in duration, the direct output of the additional single-vibrator is connected to the first input of the first element And characterized in that, in order to simplify, the inverse outputs of the digits of the binary η-bit counter are connected respectively to the second inputs of the discharge single-vibrators, the second inputs to the first of the nth nth bit single vibrators are respectively connected to the third inputs from the first to the nth logic blocks, the fourth inputs of which are connected respectively with the inverse outputs from the second to the nth bit single vibrators, the direct input of the first bit single vibrator is connected to the first input of the second AND element , the inverse outputs of the first bit and additional © single-vibrators are connected respectively to the second inputs of the first and second AND elements, the outputs of which are connected to the additional inputs of the OR element. 2. The device according to π. 1, characterized in that each logic block contains an AND — OR element and AND — NOT the first, second inputs and the output of which are connected respectively to the first, third inputs of the logic block and the first input of the first structure AND of the AND — OR element, the second input of the first structure And, the first, second, third inputs of the second structure And and the output of which are connected respectively to the second, fourth, third, first inputs and the output of the logical block. SU „., 1188883