RU2503993C1 - Programmable logic device - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device includes groups of D flip-flops, function calculating units, a counter, a decoder, conjunction units, conjunction value units, wherein the function calculating units, conjunction units and conjunction value units are based on 2·2NOT-AND-OR elements which execute the function

EFFECT: reducing hardware costs when designing circuits for logic functions with a large number of variables.

4 dwg, 8 tbl

Description

The invention relates to computer technology and can be used to calculate logical functions in fault-tolerant equipment.

Known programmable logic device containing g n-input elements AND (n - the number of information inputs of the device, 2≅g≅2 ⁿ ), t elements OR (t - the number of information outputs of the device), the first, second and third groups of D-flip-flops, the first group of AND elements with three output states, the group of AND-NOT elements with three output states, g · t two-input AND elements, a counter and a decoder, the first, second and third RS triggers, an additional OR element and the second group of AND elements with three states exit (ed. St. USSR No. 1444892, class G 11C 17/00, G06F 7/00, 1988).

The disadvantages of the known device are the low speed of the calculation of logical functions in the presence of failures and high hardware costs for the implementation of logical function systems due to the use of standard logical bases.

, а старший неинверсный разряд этих входов является соответствующим n-м неинверсным входом группы 2n·m входов парафазных входных переменных, выходы элементов ИЛИ группы m(n-1) элементов ИЛИ подключены к соответствующим i-м инверсным входам парафазных входных переменных соответствующего из m блоков вычисления функций

, а старший инверсный разряд этих входов является соответствующим n-м инверсным входам группы 2n·m входов парафазных входных переменных, входы сброса блоков вычисления функций являются входом сброса устройства, входы синхронизации блоков вычисления функций являются входом синхронизации устройства, дополнительные входы сброса блоков вычисления функций являются группой m входов дополнительного сброса устройства, входы реконфигурации m блоков вычисления функций являются группой m входов реконфигурации блоков вычисления функций при отказах, входы типа реконфигурации m блоков вычисления функции при отказах являются группой m входов типа реконфигурации блоков вычисления функций при отказах, выходы неинверсного значения функции блоков вычисления функций являются соответствующими разрядами группы m выходов значений функции устройства, выходы инверсного значения функции блоков вычисления функций являются соответствующими разрядами группы m выходов инверсных значений функций устройства, выходы готовности результатов вычислений блоков вычисления функций являются группой m выходов готовности результатов вычисления функций устройства, каждый блок вычисления функций содержит группу 4·2ⁿ элементов И с тремя состояниями на выходе, два D-триггера, Т-триггер, RS-триггер фиксации импульса, пять элементов ИЛИ, три элемента И, четыре инвертора, n групп элементов 2·2НЕ-И-ИЛИ (в каждую i-ю группу входит 2^n-1 элементов,

), элемент задержки, дополнительную группу элементов И с тремя состояниями на выходе, причем входы управления нечетных элементов И с тремя состояниями на выходе из группы 4·2ⁿ элементов И с тремя состояниями на выходе подключены к неинверсному выходу Т-триггера, инверсный выход которого подключен ко входам управления четырех элементов И с тремя состояниями на выходе из группы 4·2ⁿ элементов И с тремя состояниями на выходе, информационные выходы которых являются соответствующими разрядами входов настройки блока, информационные входы нечетных элементов И с тремя состояниями на выходе из первой половины группы 4·2ⁿ элементов И с тремя состояниями на выходе подключены к соответствующим j-м элементам второй половины входов настройки,

, информационные входы нечетных элементов И с тремя состояниями на выходе из второй половины 4·2ⁿ элементов И с тремя состояниями на выходе подключены к соответствующим М разрядам первой половины входов настройки,

, выходы нечетных элементов И с тремя состояниями на выходе группы 4·2ⁿ элементов И с тремя состояниями на выходе объединены с выходами соответствующих четных элементов И с тремя состояниями на выходе и подключены к соответствующим нечетным входам соответствующего элемента 2·2НЕ-И-ИЛИ первой группы из n групп элементов 2·2НЕ-И-ИЛИ (по две пары нечетный - четный элемент И с тремя состояниями выхода на каждый элемент 2·2НЕ-И-ИЛИ, четные входы элементов 2·2НЕ-И-ИЛИ каждой S-й группы,

, элементов 2·2НЕ-И-ИЛИ являются соответствующими разрядами входов парафазных входных переменных блока (второй вход каждого элемента 2·2НЕ-И-ИЛИ S-й группы является входом X_S, четвертый -

), выходы элементов 2·2НЕ-И-ИЛИ S-й группы,

, где n - число входных переменных, подключены к соответствующим нечетным входам элементов 2·2НЕ-И-ИЛИ S+1 группы, причем к каждому элементу 2·2НЕ-И-ИЛИ в группы

подключены выходы двух элементов i-1 групп, выход единственного элемента 2·2НЕ-И-ИЛИ последней n-й группы из n групп элементов 2·2НЕ-И-ИЛИ подключен к информационному входу первого D-триггера, второй вход этого элемента подключен к выходу первого элемента ИЛИ, а четвертый вход этого элемента 2·2НЕ-И-ИЛИ n-й группы подключен к выходу второго элемента ИЛИ, первые входы первого и второго элементов ИЛИ подключены к выходам первого и второго элементов И соответственно, второй вход первого элемента ИЛИ подключен к объединенным выходам первого и второго элементов И с тремя состояниями на выходе дополнительной группы элементов И с тремя состояниями при выходе, второй вход второго элемента ИЛИ подключен к объединенным выходам третьего и четвертого элементов И с тремя состояниями на выходе дополнительной группы элементов И с тремя состояниями на выходе, вторые входы первого и второго элементов И, входы второго и четвертого инвертора являются видом реконфигурации блока при отказах, первый вход первого элемента И и вход первого инвертора являются входом типа реконфигурации блока при отказах, выход первого инвертора подключен к первому входу второго элемента И, вход обнуления первого D-триггера и первый вход четвертого элемента ИЛИ являются входом сброса блока, входы синхронизации первого и второго D-триггеров, счетный вход Т-триггера, вход элемента задержки являются входом синхронизации блока, выход второго инвертора подключен ко второму входу четвертого элемента ИЛИ, третий вход которого является входом дополнительного сброса блока, выход четвертого элемента ИЛИ подключен ко входам обнуления второго D-триггера, RS-триггера фиксации импульса и Т-триггера, выход первого D-триггера подключен к информационному входу второго D-триггера и первому входу третьего элемента ИЛИ, второй вход которого подключен к выходу второго D-триггера, выход третьего элемента ИЛИ является выходом значения функции блока и подключен ко входу третьего инвертора и первому входу пятого элемента ИЛИ, выход третьего инвертора является выходом инверсного значения функции блока, выход четвертого инвертора подключен ко второму входу пятого элемента ИЛИ, третий вход которого подключен ко входу третьего элемента И, выход пятого элемента ИЛИ является выходом готовности результатов вычисления функций блока, первый вход третьего элемента И подключен к выходу RS-триггера функции импульса, а второй вход третьего элемента И подключен к инверсному выходу Т-триггера, который также подключен ко входам управления нечетных элементов И с тремя состояниями на выходе дополнительной группы элементов с тремя состояниями на выходе, ко входам управления четных элементов которой подключен неинверсный выход Т-триггера, информационные входы первого и четвертого элементов И с тремя состояниями на выходе являются n-м инверсным входом х_n парафазных входных переменных блока, а информационные входы второго и третьего элементов И с тремя состояниями на выходе дополнительной группы элементов И с тремя состояниями на выходе являются n-м инверсным входом

парафазных входных переменных блока (патент РФ №2146840 от 20.03.2000, кл. G11C 17/00, G06F 7/00). Данное устройство принято за прототип.The closest device of the same purpose to the claimed invention in terms of features is a programmable logic device containing the first, second, and third groups of D-flip-flops of m · 2 ^{n each} (n is the number of input variables, m is the number of output functions), and the third group is D -triggers of 2 (n-1) m, group m (n-1) AND elements, counter, group m · 2 ⁿ AND elements with three output states, decoder, group m (n-1) OR elements, second group m · 2 ⁿ elements and a tri-state output and calculation functions of m blocks, and in The reset input of the D-flip-flops of the first, second and third groups of the counter is the input of the device reset, the counter input of the counter is the programming input of the device, and the information outputs of the counter are connected to the information inputs of the decoder, the non-inverse outputs of the D-flip-flops of the second group are connected to the control inputs of the corresponding elements tri-state output groups of m · 2 ⁿ elements and a tri-state output, a noninverted outputs of D-flip-flops of the third group are connected to respective second inputs of the AND c ppy m · 2 ⁿ elements, and the control inputs of the elements of the second group of m · 2 ⁿ elements and a tri-state output connected to the inverted outputs of the respective D-flip-flops of the second group D-flip-flops, and the data inputs of the elements of the second group of m · 2 ⁿ elements and with three states at the output are the corresponding expansion inputs of the corresponding group of m groups of expansion inputs, the outputs of the elements And with three states at the output are combined and connected to the settings inputs of the corresponding of the m function calculation blocks, the first output the decoder is connected to the synchronization inputs of the D-triggers of the first group, the second output of the decoder is connected to the synchronization inputs of the D-triggers of the second group, the third output of the decoder is connected to the synchronization inputs of the D-triggers of the third group, the fourth output of the decoder is the output of the end of programming the device, the information inputs are D- the triggers of the first and second groups are the corresponding expansion inputs of the corresponding of m groups of expansion inputs, the information inputs of the D-triggers of the third group are 2 (n-1) expansion inputs of the corresponding of m groups of expansion inputs, the first inputs of elements AND of the group m (n-1) elements AND are the corresponding of n-1 non-inverse inputs of the group 2n · m inputs of paraphase input variables (2m bits for each block of function calculation), the first inputs of OR elements of group m (m-1) elements of OR are corresponding from n-1 inverse inputs of group 2n · m inputs of paraphase input variables (2m bits for each of m blocks of function calculation), outputs of elements AND of group m (n-1 ) elements And are connected to the corresponding i-th and inverse inputs of paraphase input variables corresponding to m function calculation blocks

and the senior non-inverse discharge of these inputs is the corresponding nth non-inverse input of the group of 2n · m inputs of paraphase input variables, the outputs of the OR elements of the group of m (n-1) elements OR are connected to the corresponding i-inverse inputs of the paraphase input variables of the corresponding m blocks function calculations

and the senior inverse discharge of these inputs corresponds to the nth inverse inputs of the group of 2n · m inputs of paraphase input variables, the reset inputs of the function calculation blocks are the device reset input, the synchronization inputs of the function calculation blocks are the device synchronization input, the additional reset inputs of the function calculation blocks are a group of m inputs of additional device reset, inputs of reconfiguration of m function calculation blocks are a group of m inputs of reconfiguration of function calculation blocks at failure ah, the inputs of the reconfiguration type of m function calculation blocks for failures are a group of m inputs of the reconfiguration type of function calculation blocks for failures, the outputs of a non-inverse function value of the function calculation blocks are the corresponding bits of the group m of the outputs of the device function values, the outputs of the inverse value of the function of the function calculation blocks are the corresponding bits groups of m outputs of inverse values of device functions, outputs of the readiness of the results of calculations of function calculation blocks are d m outputs readiness results computing device functions, each calculation unit functions comprises a group 4 · 2 ⁿ elements and a tri-state output, two D-flip-flop, T flip-flop, RS-trigger pulse fixation five elements or three elements and, four inverters, n groups of elements 2 · 2NE-AND-OR (each i-th group includes 2 ^n-1 elements,

), a delay element, an additional group of AND elements with three states at the output, and the control inputs of odd AND elements with three states at the output of the group of 4 · 2 ⁿ AND elements with three states at the output are connected to the non-inverse output of the T-trigger, whose inverse output is connected to the control inputs of four elements And with three states at the output of a group of 4 · 2 ⁿ elements And with three states at the output, the information outputs of which are the corresponding bits of the settings block inputs, the information inputs are odd of AND elements with three states at the output of the first half of the group of 4 · 2 ⁿ AND elements with three states at the output are connected to the corresponding jth elements of the second half of the settings inputs,

, the information inputs of odd elements AND with three states at the output from the second half of 4 · 2 ⁿ elements AND with three states at the output are connected to the corresponding M bits of the first half of the settings inputs,

, the outputs of the odd elements AND with three states at the output of a group of 4 · 2 ⁿ elements AND with three states at the output are combined with the outputs of the corresponding even elements AND with three states at the output and connected to the corresponding odd inputs of the corresponding element 2 · 2НЕ-AND-OR groups of n groups of 2 · 2HE-AND-OR elements (two odd pairs - even AND element with three output states for each 2 · 2HE-AND-OR element, even inputs of 2 · 2HE-AND-OR elements of each Sth groups

, 2 · 2НЕ-AND-OR elements are the corresponding bits of the inputs of the paraphase input variables of the block (the second input of each 2 · 2НЕ-AND-OR element of the Sth group is the input X _S , the fourth

), the outputs of the elements 2 · 2NE-AND-OR S-th group,

, where n is the number of input variables, connected to the corresponding odd inputs of elements of 2 · 2НЕ-AND-OR S + 1 groups, and to each element 2 · 2НЕ-AND-OR in groups

the outputs of two elements of i-1 groups are connected, the output of a single element of 2 · 2HE-AND-OR of the last n-th group of n groups of elements of 2 · 2HE-AND-OR is connected to the information input of the first D-trigger, the second input of this element is connected to the output of the first OR element, and the fourth input of this element 2 · 2NE-AND-OR of the nth group is connected to the output of the second OR element, the first inputs of the first and second OR elements are connected to the outputs of the first and second AND elements, respectively, the second input of the first OR element connected to the combined outputs of the first and second about AND elements with three states at the output of an additional group of AND elements with three states at the output, the second input of the second OR element is connected to the combined outputs of the third and fourth elements AND with three states at the output of an additional group of elements AND with three states at the output, second inputs of the first and the second element And, the inputs of the second and fourth inverter are a type of reconfiguration of the unit in case of failure, the first input of the first element And and the input of the first inverter are an input of the type of reconfiguration of the unit in case of failure zh, the output of the first inverter is connected to the first input of the second element AND, the input of zeroing of the first D-trigger and the first input of the fourth element OR are the block reset input, the synchronization inputs of the first and second D-triggers, the counting input of the T-trigger, the input of the delay element are the input block synchronization, the output of the second inverter is connected to the second input of the fourth OR element, the third input of which is the input of the additional reset of the block, the output of the fourth OR element is connected to the zeroing inputs of the second D-trigger, RS-trigger Era of fixing the pulse and the T-trigger, the output of the first D-trigger is connected to the information input of the second D-trigger and the first input of the third OR element, the second input of which is connected to the output of the second D-trigger, the output of the third OR is the output of the value of the block function and connected to the input of the third inverter and the first input of the fifth OR element, the output of the third inverter is the output of the inverse value of the block function, the output of the fourth inverter is connected to the second input of the fifth OR element, the third input of which is connected to the input of the third element AND, the output of the fifth element OR is the readiness output of the calculation of the block functions, the first input of the third element And is connected to the output of the RS-trigger of the pulse function, and the second input of the third element And is connected to the inverse output of the T-trigger, which is also connected to the inputs control of odd elements And with three states at the output of an additional group of elements with three states at the output, to the control inputs of even elements of which a non-inverse T-trigger output is connected, information inputs s first and fourth elements and a tri-state output are n-th inverse input x _n paraphase input block variables, and the data inputs of the second and third elements and a tri-state output further group of elements and a tri-state output are n-m inverse input

paraphase input variables of the block (RF patent No. 2146840 from 03.20.2000, class G11C 17/00, G06F 7/00). This device is taken as a prototype.

A disadvantage of the known device adopted for the prototype is the high hardware costs for the implementation of logical functions of a large number of variables.

This is due to the following circumstances. The technical means of the prototype are focused on the implementation of logical functions in perfect disjunctive normal form (SDNF). In this regard, each function calculation unit must have 2 ⁿ tuning inputs for setting all possible function constitutions of n variables, although some of them can be repeated in other functions of the function system. For the implementation of each block of function calculation in the prototype, 2 ⁿ -1 element is required, which leads to the impossibility of such an implementation even for small n - of the order of 8 ... 10. Currently, in programmable logic integrated circuits (FPGAs), the transition to function calculation blocks (LUT) of 6 variables has only just begun, mainly blocks 4, 5 of variables are used.

The objective of the invention is to reduce hardware costs for the implementation of logical function systems of a large number of variables.

, где k=int log₂(n),(n=2^k), в первой группе n/2 элементов, в каждой группе элементов в два раза меньше, чем в предыдущей, в последней - один элемент, то есть имеется "пирамидальное" соединение элементов, причем выходы нечетных элементов нечетных групп подключены к первым входам соответствующих элементов следующей четной группы элементов 2·2НЕ-И-ИЛИ двум элементам нечетной группы соответствует один элемент четной группы, выходы четных элементов первой группы элементов 2·2НЕ-И-ИЛИ подключены к четвертым входам следующей четной группы элементов 2·2НЕ-И-ИЛИ дополнительно введены k-1 групп первых D-триггеров количеством n, где n - разрядность вычисляемых логических функций, k - число вычисляемых конъюнкций в системе из m функций, k-1 групп вторых D-триггеров количеством n, k-1 групп третьих D-триггеров количеством n, группа k блоков конъюнкций, группа k блоков значений конъюнкций, причем информационные входы D-триггеров k-1 групп первых D-триггеров, вторых D-триггеров, третьих D-триггеров подключены к соответствующим разрядам входов данных, входы сброса D-триггеров k-1 групп первых D-триггеров, вторых D-триггеров, третьих объединены и подключены ко входу сброса устройства, входы синхронизации D-триггеров k-1 групп первых D-триггеров подключены к соответствующим k-1 выходам дешифратора для k-1 групп первых D-триггеров, входы синхронизации D-триггеров k-1 групп вторых D-триггеров подключены к соответствующим k-1 выходам дешифратора для k-1 групп вторых D-триггеров, входы синхронизации D-триггеров k-1 групп третьих D-триггеров подключены к соответствующим k-1 выходам дешифратора для k-1 групп третьих D-триггеров, выходы группы первых D-триггеров подключены к первой группе входов первого блока конъюнкций, выходы группы вторых D-триггеров подключены ко второй группе входов первого блока конъюнкций, третьи группы входов всех блоков конъюнкций подключены ко входу переменных устройства, выходы k-1 групп первых D-триггеров подключены к первым группам входов соответствующих k-1 блоков конъюнкций, выходы k-1 групп вторых D-триггеров подключены ко вторым группам входов соответствующих k-1 блоков конъюнкций, выходы блоков конъюнкций подключены ко входам соответствующих блоков значений конъюнкций, выходы блоков значений конъюнкций подключены к соответствующим входам конъюнкций каждого блока вычисления функций, выходы k-1 групп третьих D-триггеров подключены к соответствующим входам функций блоков значений конъюнкций, причем нечетные входы первой группы элементов 2·2НЕ-И-ИЛИ подключены к соответствующим входам первой группы входов блока вычисления функций, четные входы первой группы элементов 2·2НЕ-И-ИЛИ подключены к соответствующим входам второй группы входов блока вычисления функций, выходы нечетных элементов нечетных групп элементов 22·2НЕ-И-ИЛИ, реализующих функцию

, подключены к третьим входам соответствующих элементов второй группы элементов 2·2НЕ-И-ИЛИ, реализующих функцию

, выходы четных элементов первой группы элементов 2·2НЕ-И-ИЛИ подключены ко вторым входам второй группы элементов 2·2НЕ-И-ИЛИ, выходы предпоследней группы элементов 2·2НЕ-И-ИЛИ содержат два элемента 2·2НЕ-И-ИЛИ и выход первого элемента предпоследней группы подключен к первому и второму входам единственного элемента последней группы, а выход второго элемента предпоследней группы подключен к третьему и четвертому входам единственного элемента последней группы, выход которого является выходом блока вычисления функций, при этом каждый i-ый блок конъюнкций содержит n групп значений разрядов, каждый из которых содержит 6 элементов 2·2НЕ-И-ИЛИ, причем входы первых трех элементов объединены, вход первого элемента подключен к соответствующему i-му входу третьей группы входов блока конъюнкций и к первым двум входам четвертого элемента, вход второго элемента подключен к соответствующему i-му входу первой группы входов блока конъюнкций и к третьему и четвертому входам четвертого элемента, вход третьего элемента подключен к соответствующему i-му входу второй группы входов блока конъюнкций и ко второму входу шестого элемента, выход которого является i-м выходом i-го блока конъюнкций, выход первого элемента подключен к первому и третьему входам пятого элемента, выход второго элемента подключен ко второму и четвертому входам пятого элемента, выход третьего элемента подключен к третьему входу шестого элемента, выход четвертого элемента подключен к первому входу шестого элемента, а выход пятого элемента подключен к четвертому входу шестого элемента, третья группа входов каждого блока конъюнкций является входами переменных устройства, при этом каждый i-ый блок значений конъюнкций содержит k групп n-1 элементов 2·2НЕ-И-ИЛИ, где k=int log₂(n), (n=2^k), то есть имеется "пирамидальное" соединение элементов, и дополнительный элемент, причем первый и второй входы первой группы элементов 2·2НЕ-И-ИЛИ подключены к соответствующим нечетным входам блока значений конъюнкций, третий и четвертый входы первой группы элементов 2·2НЕ-И-ИЛИ подключены к соответствующим нечетным входам блока значений конъюнкций, выходы нечетных элементов первой группы элементов 2·2НЕ-И-ИЛИ подключены к нечетным входам второй группы элементов 2·2НЕ-И-ИЛИ, выходы четных элементов нечетной группы элементов 2·2НЕ-И-ИЛИ, реализующих функцию

, подключены к четным входам четной группы элементов 2·2НЕ-И-ИЛИ, реализующих функцию

, выходы предпоследней группы элементов 2·2НЕ-И-ИЛИ содержат два элемента 2·2НЕ-И-ИЛИ и выход первого элемента предпоследней группы подключен к первому и второму входам единственного элемента последней группы, а выход второго элемента предпоследней группы подключен к третьему и четвертому входам единственного элемента последней группы, выход которого подключен ко всем входам дополнительного элемента, выход которого является выходом блока значений конъюнкций.The problem was solved due to the fact that in the well-known programmable logic device containing the first, second and third groups of D-flip-flops of quantity n, where n is the bit capacity of the calculated logical functions, the group m of function calculation blocks, where m is the number of calculated logical functions, a counter, a decoder, and the information inputs of D-flip-flops from the groups of D-flip-flops are connected to the corresponding bits of the data inputs, the reset inputs of all D-flip-flops of all the groups of D-flip-flops and the counter reset input are combined and connected to the input with device rollout, the counter output is connected to the decoder input, the first decoder output is connected to the synchronization inputs of D-flip-flops of the first group of D-flip-flops, the second decoder output is connected to the synchronization inputs of D-flip-flops of the second group of D-flip-flops, the third decoder output is connected to the synchronization inputs of D -triggers of the third group of D-flip-flops, the outputs of the group m of function calculation blocks are the device outputs, each function calculation block contains k groups of n-1 elements 2 · 2НЕ-AND-OR, implementing the function

, where k = int log ₂ (n), (n = 2 ^k ), in the first group there are n / 2 elements, in each group of elements there are two times less than in the previous one, in the last one element, that is, there is a “pyramidal "a connection of elements, the outputs of the odd elements of odd groups connected to the first inputs of the corresponding elements of the next even group of elements 2 · 2HE-AND-OR two elements of the odd group correspond to one element of the even group, the outputs of the even elements of the first group of elements 2 · 2HE-AND-OR connected to the fourth inputs of the next even group of elements 2 · 2НЕ-И- LI additionally introduced k-1 groups of the first D-triggers of number n, where n is the bit depth of the calculated logical functions, k is the number of calculated conjunctions in the system of m functions, k-1 groups of the second D-triggers with the number n, k-1 groups of the third D -triggers of n number, a group of k conjunction blocks, a group of k conjunction value blocks, the information inputs of D-triggers of k-1 groups of the first D-flip-flops, second D-flip-flops, third D-flip-flops are connected to the corresponding bits of the data inputs, reset inputs D -triggers of k-1 groups of the first D-triggers, second D-triggers Third, combined and connected to the reset input of the device, synchronization inputs of D-flip-flops of k-1 groups of the first D-flip-flops are connected to the corresponding k-1 decoder outputs for k-1 groups of the first D-flip-flops, synchronization inputs of D-flip-flops k-1 groups of second D-flip-flops are connected to the corresponding k-1 decoder outputs for k-1 groups of second D-flip-flops, synchronization inputs of D-flip-flops of k-1 groups of third D-flip-flops are connected to the corresponding k-1 decoder outputs for k-1 groups of third D-flip-flops, the outputs of the group of the first D-flip-flops are connected to ne the first group of inputs of the first conjunction block, the outputs of the group of second D-triggers are connected to the second group of inputs of the first conjunction block, the third groups of inputs of all conjunction blocks are connected to the input of the device variables, the outputs k-1 of the groups of the first D-triggers are connected to the first input groups of the corresponding k -1 conjunction blocks, outputs of k-1 groups of second D-flip-flops connected to second groups of inputs of the corresponding k-1 conjunction blocks, outputs of conjunction blocks connected to inputs of the corresponding blocks of conjunction values, outputs of conjunction values are connected to the corresponding inputs of the conjunctions of each function calculation block, the outputs of k-1 groups of third D-flip-flops are connected to the corresponding inputs of the functions of the blocks of conjunction values, and the odd inputs of the first group of 2 · 2HE-AND-OR elements are connected to the corresponding inputs of the first group the inputs of the function calculation block, the even inputs of the first group of elements 2 · 2NE-AND-OR are connected to the corresponding inputs of the second group of inputs of the block of calculation of functions, the outputs of the odd elements of the odd groups of elements 22 · 2 NON-AND-OR implementing a function

connected to the third inputs of the corresponding elements of the second group of elements 2 · 2NE-AND-OR, implementing the function

, the outputs of the even elements of the first group of elements 2 · 2HE-AND-OR are connected to the second inputs of the second group of elements 2 · 2HE-AND-OR, the outputs of the penultimate group of elements 2 · 2HE-AND-OR contain two elements 2 · 2NE-AND-OR and the output of the first element of the penultimate group is connected to the first and second inputs of the only element of the last group, and the output of the second element of the penultimate group is connected to the third and fourth inputs of the only element of the last group, the output of which is the output of the function calculation block, with each i-th block conjunction contains n groups of values of digits, each of which contains 6 elements 2 · 2NE-AND-OR, and the inputs of the first three elements are combined, the input of the first element is connected to the corresponding i-th input of the third group of inputs of the conjunction block and to the first two inputs of the fourth element , the input of the second element is connected to the corresponding i-th input of the first group of inputs of the conjunct block and to the third and fourth inputs of the fourth element, the input of the third element is connected to the corresponding i-th input of the second group of inputs of the conjunct block and to the second input of the sixth element, the output of which is the i-th output of the i-th conjunction block, the output of the first element is connected to the first and third inputs of the fifth element, the output of the second element is connected to the second and fourth inputs of the fifth element, the output of the third element is connected to the third input of the sixth element, the output of the fourth element is connected to the first input of the sixth element, and the output of the fifth element is connected to the fourth input of the sixth element, the third group of inputs of each conjunction block is variable inputs of each i-th block of conjuncture values contains k groups of n-1 elements 2 · 2NE-AND-OR, where k = int log ₂ (n), (n = 2 ^k ), that is, there is a “pyramidal” connection elements, and an additional element, with the first and second inputs of the first group of 2 · 2НЕ-AND-OR elements connected to the corresponding odd inputs of the conjunction value block, the third and fourth inputs of the first group of 2 · 2НЕ-AND-OR elements connected to the corresponding odd inputs of the block conjunction values, the outputs of the odd elements of the first group of elements 2 · 2NE-AND-OR are connected to nym inputs of the second element group 2 · 2He-AND-OR outputs even elements of odd group of elements 2 · 2He-AND-OR function realizing

connected to the even inputs of an even group of 2 · 2HE-AND-OR elements that implement the function

, the outputs of the penultimate group of elements 2 · 2NE-AND-OR contain two elements 2 · 2NE-AND-OR and the output of the first element of the penultimate group is connected to the first and second inputs of a single element of the last group, and the output of the second element of the penultimate group is connected to the third and fourth the inputs of a single element of the last group, the output of which is connected to all inputs of the additional element, the output of which is the output of a block of conjunction values.

, позволяет снизить аппаратные затраты на реализацию систем логических функций большого количества переменных.Introduction of the procedure for calculating logical functions in disjunctive normal form (DNF) based on logical elements that implement the function 2 · 2NE-AND-OR

, allows to reduce hardware costs for the implementation of logical function systems of a large number of variables.

The essence of the new procedure introduced is as follows:

a) in the task for each conjunction of the calculated system of logical functions of three constants - masks: the main one, which distinguishes essential variables, the additional one, which distinguishes non-inverse essential variables, of output functions, which functions of the system of functions are activated by this conjunction;

b) in calculating each bit of a given conjunction according to the corresponding bit of the input vector using 2 · 2HE-AND-OR logic elements;

c) in calculating the values of a given conjunction according to the corresponding results of calculating all its bits using 2 · 2HE-AND-OR logic elements;

d) in calculating the values of functions from the results of calculating all conjunctions using logical elements 2 · 2NE-AND-OR.

The introduction of additional k-1 groups of triggers of the first D-triggers of number n, where n is the bit depth of the calculated logical functions, k is the number of calculated conjunctions in the system of m functions allows you to store a k-1 n-bit main mask in the process of computing to highlight significant variables ( XO) to provide computations in k-1 conjunct blocks.

The introduction of additional k-1 groups of second D-flip-flops of quantity n allows you to store an n-bit additional mask in the process of computing k-1 to isolate non-inverse significant variables (XD) to provide calculations in k-1 conjunction blocks.

The introduction of additional k-1 groups of third D-flip-flops of quantity n allows you to store an n-bit mask of output functions (ZB) during the calculation process, indicating which functions of the system of functions this conjunction activates to provide calculations in function calculation blocks.

The introduction of conjunction blocks with the proposed structure and corresponding relationships allows us to calculate each bit of a given conjunction by the corresponding bit of the input vector using 2 · 2HE-AND-OR logic elements.

The introduction of blocks of conjunction values with the proposed structure and corresponding relationships allows us to calculate the value of this conjunction using the corresponding results of calculating all its bits in conjunction blocks using 2 · 2HE-AND-OR logic elements, and if the conjunction is true, that is, equal to one (all significant bits of the input vector coincide with the corresponding given conjunction), then a zero signal is generated at the output of the value block.

The introduction of new relationships for m function calculation blocks allows you to calculate the values of functions in the system of functions according to the results of calculations in blocks of conjunction values, using the configuration information in k-1 groups of third D-triggers during the implementation of the new discipline introduced.

The introduction of new relationships for the D-flip-flops of the first group allows us to store an n-bit main mask during the computation process for highlighting significant variables (XO) to provide calculations in the first block of conjunctions.

The introduction of new relationships for the D-flip-flops of the second group allows us to store an n-bit main mask during the computation process for highlighting significant variables (XO) to provide calculations in the first block of conjunctions.

The introduction of new relationships for the decoder allows programming of additional k-1 groups of D-flip-flops of the first, second and third groups for their subsequent participation in the implementation of computations of logical functions.

The introduction of new element relationships in the function calculation block allows you to calculate the values of functions in the function system according to the results of calculations in the conjunction value blocks, using the configuration information in k-1 groups of third D-triggers during the implementation of the new discipline introduced.

Figure 1 shows an electrical structural diagram of a programmable logic device.

Figure 2 - electrical functional diagram of the j-th category - the i-th conjunction block.

Figure 3 is an electrical functional diagram of the i-th block of conjunction values.

Figure 4 is an electrical functional diagram of the i-th function calculation unit.

The programmable logic device contains the first 1, second 2, and third 3 groups of D-flip-flops of quantity n, where n is the bit depth of the calculated logical functions, the group m of function calculation blocks 4, where m is the number of calculated logical functions, counter 5, decoder 6, k- 1 groups of the first D-flip-flops 7 of number n, where n is the capacity of the calculated logical functions, k is the number of computed conjunctions in the system of m functions, k-1 of the groups of the second D-flip-flops 8 of the number of n, k-1 groups of the third D-flip-flops 9 number n, a group of k blocks of conjunctions 10, a group of k blocks of conjunction 11.

The device has inputs for setting variables 12.

The information inputs of D-triggers from groups 1, 2, 3, 7, 8, 9 of D-triggers are connected to the corresponding bits of the data inputs 13.

The reset inputs of all D-flip-flops from groups 1, 2, 3, 7, 8, 9 of the D-flip-flops and the reset input of counter 5 are combined and connected to the reset input 14 of the device.

The output of the counter 5 is connected to the input of the decoder 6.

The first output 6.1.1 of the decoder 6 is connected to the synchronization inputs of the D-flip-flops of the first group of D-flip-flops 1.

The second output 6.1.2 of the decoder 6 is connected to the synchronization inputs of the D-flip-flops of the second group of D-flip-flops 2.

The third output 6.1.3 of the decoder 6 is connected to the synchronization inputs of the D-flip-flops of the third group of D-flip-flops 3.

The counting input of the counter 5 is the programming input of the device 15.

The outputs of the group m of function calculation blocks 4 are outputs of the device 16.

The information inputs of the D-flip-flops k-1 of the groups of the first D-flip-flops 7, the second D-flip-flops 8, the third D-flip-flops 9 are connected to the corresponding bits of the tuning inputs 13.

The reset inputs of the D-flip-flops k-1 of the groups of the first D-flip-flops 7, the second D-flip-flops 8, the third D-flip-flops 9 are combined and connected to the reset input 14 of the device.

The synchronization inputs of the D-flip-flops of the i-th of k-1 groups of the first D-flip-flops 7 are connected to the corresponding i-th of the k-1 outputs 6.i.1 of the decoder 6 for k-1 groups of the first D-flip-flops 7.

The synchronization inputs of the D-flip-flops of the i-th of k-1 groups of the second D-flip-flops 8 are connected to the corresponding i-th of the k-1 outputs 6.i.2 of the decoder 6 for k-1 groups of the second D-flip-flops 8.

The synchronization inputs of the D-flip-flops of the i-th of k-1 groups of the third D-flip-flops 9 are connected to the corresponding i-th of the k-1 outputs 6.i.3 of the decoder 6 for k-1 groups of the third D-flip-flops 9.

The outputs of the group of the first D-flip-flops 1 are connected to the first group of inputs 10.1.1 of the first block of conjunctions 10.1.

The outputs of the group of second D-flip-flops 2 are connected to the second group of inputs 10.1.2 of the first block of conjunctions 10.1.

The third groups of inputs 10.1.3 of all conjunction blocks are connected to the input of the job variables 12 of the device.

The outputs of k-1 groups of the first D-flip-flops 7 are connected to the first groups of inputs 10.i.1 of the corresponding i-th of k-1 blocks of conjunctions 10.i (i = 2 ... k).

The outputs of k-1 groups of the second D-flip-flops 8 are connected to the second groups of inputs 10.i.2 of the corresponding i-th of k-1 blocks of conjunctions 10.i (i = 2 ... k).

The outputs 10.1.4 of the i-th conjunction blocks 10.i are connected to the inputs of the corresponding blocks of conjunction values 11.i.

The outputs of the jth blocks of conjunction values 11.i are connected to the inputs of conjunctions 4.j of each of the blocks for calculating functions 4 (j = 1 ... k).

The outputs of the i-th D-flip-flops from k-1 groups of the third D-flip-flops 9 are connected to the corresponding i-th inputs of the functions 4.2.i (i = 1 ... m) of the function calculation blocks 4.

The device has 16 function value outputs.

The last output of the decoder 6 is the readiness output 17 of the device.

, где k=int log₂(n), (n=2^k). В первой группе n/2 элементов, в каждой группе элементов в два раза меньше, чем в предыдущей, в последней - один элемент, то есть имеется "пирамидальное" соединение элементов.Each block of the i-th calculation of functions 10.i contains k groups of n-1 elements 2 · 2NE-AND-OR that implement the function

where k = int log ₂ (n), (n = 2 ^k ). In the first group there are n / 2 elements, in each group of elements there are two times less than in the previous one, in the last one element, that is, there is a “pyramidal" connection of elements.

, 18.1.j количеством r, где r=2^n-1 подключены к соответствующим входам первой группы входов блока вычисления функций 4.1.1, 4.3.1…4.n-1.1. При этом предполагается, что

.Odd inputs of the first group of 2 · 2NE-AND-OR elements that implement the function

, 18.1.j of quantity r, where r = 2 ^{n-1 are} connected to the corresponding inputs of the first group of inputs of the function calculation block 4.1.1, 4.3.1 ... 4.n-1.1. It is assumed that

.

, 18.1.j подключены к соответствующим входам 4.2.1, 4.4.1…4.n.1 второй группы входов блока вычисления функций.Even inputs of the first group of elements 2 · 2NE-AND-OR, implementing the function

, 18.1.j are connected to the corresponding inputs 4.2.1, 4.4.1 ... 4.n.1 of the second group of inputs of the function calculation block.

, подключены к нечетным входам второй группы элементов 2·2НЕ-И-ИЛИ, реализующих функцию

, 18.2.j.The outputs of the odd elements of the first group of elements 2 · 2NE-AND-OR, implementing the function

connected to the odd inputs of the second group of elements 2 · 2NE-AND-OR, implementing the function

, 18.2.j.

, 18.1 подключены к четным входам второй группы элементов 2·2НЕ-И-ИЛИ, реализующих функцию

, 18.2.The outputs of the even elements of the first group of elements 2 · 2NE-AND-OR, implementing the function

, 18.1 are connected to the even inputs of the second group of 2 · 2HE-AND-OR elements that implement the function

, 18.2.

, 18.k подключены к нечетным входам следующей группы элементов 2·2НЕ-И-ИЛИ, реализующих функцию

, 18.k+1.Similarly, the outputs of the odd elements of the odd group of elements 22 · 2NE-AND-OR, implementing the function

, 18.k are connected to the odd inputs of the following group of 2 · 2NE-AND-OR elements that implement the function

, 18.k + 1.

, 18.k подключены к четным входам следующей группы элементов ·2·2НЕ-И-ИЛИ, реализующих функцию

, 18.k+1.The outputs of the even elements of the odd group 2 · 2NE-AND-OR, realizing the function

, 18.k are connected to the even inputs of the following group of elements · 2 · 2NE-AND-OR that implement the function

, 18.k + 1.

, 18.k-1.1, 18.k-1.2 содержат два элемента 2·2НЕ-И-ИЛИ, реализующих функцию

.The outputs of the penultimate group of 2 · 2HE-AND-OR elements that implement the function

, 18.k-1.1, 18.k-1.2 contain two 2 · 2HE-AND-OR elements that implement the function

.

The output of the first element of the penultimate group 18.k-1.1 is connected to the first and second inputs of the only element of the last group 18.k.

The output of the second element of the penultimate group 18.k-1.2 is connected to the third and fourth inputs of the only element of the last group 18.k, the output of which is the output of the i-th block of function calculation 16.i.

, 19-24.Each i-th block of conjunctions contains n groups of values of digits, each of which contains 6 elements 2 · 2НЕ-AND-OR, implementing the function

, 19-24.

The inputs of the first three elements 19, 20, 21 are combined, the input of the first element 19 is connected to the corresponding i-th input 10.1.3.i of the third group of inputs of the corresponding conjunction block 10 and to the first two inputs of the fourth element 22.

The input of the second element 20 is connected to the corresponding i-th input 10.1.1.i of the first group of inputs of this block of conjunctions 10 and to the third and fourth inputs of the fourth element 23.

The input of the third element 21 is connected to the corresponding i-th input 10.1.2.i of the second group of inputs of the conjunction block 10 and to the second input of the sixth element 24, the output of which is the i-th output 10.1.4.i of the i-th conjunction block 10.

The output of the first element 19 is connected to the first and third inputs of the fifth element 23.

The output of the second element 20 is connected to the second and fourth inputs of the fifth element 23.

The output of the third element 21 is connected to the third input of the sixth element, the output of the fourth element is connected to the first input of the sixth element 24.

, где k=int log₂(n), (n=2^k), и дополнительный элемент 26.The output of the fifth element 23 is connected to the fourth input of the sixth element 24. Each i-th block of conjuncture values 11 contains k groups of n-1 pyramidally connected elements 25, 2 · 2NE-AND-OR, implementing the function

, where k = int log ₂ (n), (n = 2 ^k ), and additional element 26.

, 25.1 подключены к соответствующим нечетным входам блока значений конъюнкций 10.1.4.The first and second inputs of the elements of the first group of elements 2 · 2NE-AND-OR, implementing the function

, 25.1 are connected to the corresponding odd inputs of the block of conjunction values 10.1.4.

, 25.1 подключены к соответствующим четным входам блока значений конъюнкций 10.1.4.The third and fourth inputs of the elements of the first group of elements 2 · 2NE-AND-OR, implementing the function

, 25.1 are connected to the corresponding even inputs of the block of conjunction values 10.1.4.

, 25.k подключены к нечетным входам четной группы 24.k+1 элементов 2·2НЕ-И-ИЛИ, реализующих функцию

.The outputs of the odd elements of the odd group of elements 2 · 2NE-AND-OR, implementing the function

, 25.k are connected to the odd inputs of the even group 24.k + 1 elements 2 · 2NE-AND-OR, implementing the function

.

, 25.k подключены к четным входам четной группы 25.k+1 элементов 2·2НЕ-И-ИЛИ, реализующих функцию

.The outputs of the even elements of the odd group of elements 2 · 2NE-AND-OR, implementing the function

, 25.k are connected to the even inputs of the even group 25.k + 1 elements 2 · 2NE-AND-OR, implementing the function

.

, 25.k-1 содержат два элемента 2·2НЕ-И-ИЛИ, реализующих функцию

, 25.k-1.1, 25.k-1.2 и выход первого элемента предпоследней группы 25.k-1.1 подключен к первому и второму входам единственного элемента последней группы 25.k.The outputs of the penultimate group of 2 · 2HE-AND-OR elements that implement the function

, 25.k-1 contain two 2 · 2NE-AND-OR elements that implement the function

, 25.k-1.1, 25.k-1.2 and the output of the first element of the penultimate group 25.k-1.1 is connected to the first and second inputs of the only element of the last group 25.k.

The output of the second element of the penultimate group 25.k-1.2 is connected to the third and fourth inputs of the only element of the last group 25.k, the output of which is connected to all inputs of the additional element 26, the output of which is the output of this i-th block of conjunction values 11.1.i.

The first group of D-flip-flops 1 and k-1 of the groups of the first D-flip-flops 7 (Fig. 1) of quantity n, where n is the bit depth of the calculated logical functions, k is the number of calculated conjunctions in a system of m functions are intended for recording and storage during the calculation tuning information for k n-bit main masks to highlight essential variables (CW) in order to provide calculations in k blocks of conjunctions 10.

The j-triggers of the D-triggers of these groups 1, 7 are recorded from the corresponding j-x bits of the tin inputs 13 along the leading edge of the signal "1" at the output 6.j.1 of the decoder 6 j = 1 ... k.

The D-flip-flops of these groups 1, 7 are reset to zero at the input of zeroing 14. The tuning information recorded in the D-flip-flops of these groups 1,7 controls the settings inputs 10.1.1-10.k.1 k of conjunction blocks 10.1-10.k and determines essential variables implemented in conjunctions.

D-flip-flops of these groups 1, 7 can be implemented, for example, on integrated circuits 155ТМ2 with additional inverters at the input R.

The second group of D-flip-flops 2 and k-1 groups of the second D-flip-flops 8 (Fig. 1) of quantity n, where n is the bit depth of the calculated logical functions, k is the number of calculated conjunctions in a system of m functions designed to be recorded and stored during calculations tuning information for k n-bit additional masks of non-inverse significant variables (XD) in order to provide calculations in k conjunction blocks 10.

The j-triggers of the D-triggers of these groups 2, 8 are recorded from the corresponding j-x bits of the tin inputs 13 along the leading edge of the signal “1” at the output 6.j.2 of the decoder 6, j = 1 ... k.

The D-flip-flops of these groups 2, 8 are reset to zero at the input of zeroing 14. The tuning information recorded in the D-flip-flops of these groups 2, 8 controls the settings inputs 10.1.2-10.k.2 k of conjunction blocks 10.1-10.k and determines significant non-inverse variables implemented in conjunctions.

D-triggers of these groups 2, 8 can be implemented, for example, on integrated circuits 155ТМ2 with additional inverters at the input R.

The third group of D-flip-flops 3 and k-1 of the groups of the third D-flip-flops 9 (Fig. 1) of quantity n, where n is the bit depth of the calculated logical functions, k is the number of calculated conjunctions in the system of m functions are intended for recording and storage during the calculation tuning information for k n-bit masks of output functions (ZB) indicating which functions of the function system this conjunction activates to provide calculations in function calculation blocks 4.

The j-triggers of the D-triggers of these groups 3, 9 are recorded from the corresponding j-x bits of the tin inputs 13 along the leading edge of the signal "1" at the output 6.j.3 of the decoder 6, j = 1 ... k.

The D-flip-flops of these groups 3, 9 are reset to zero at the input of zeroing 14. The tuning information recorded in the D-flip-flops of these groups 3, 9 controls the tuning inputs 4.2.1-4.2.mm of function calculation blocks 4, m≤n and indicates which functions of the system of functions are activated by this conjunction to provide calculations in function calculation blocks 4.

D-triggers of these groups 3, 9 can be implemented, for example, on integrated circuits 155ТМ2 with additional inverters at the input R.

Function calculation blocks 4 are intended for calculating the values of logical functions in a system of functions according to the results of calculations in blocks of conjunction values 11, using the tuning information in the D-triggers of groups 3, 9 for k inputs of conjunctions 4.j.1 ... 4.jk, where j - block number for calculating functions 4 of blocks 4.1 ... 4.j ... 4.m, m≤n.

Counter 5 is designed to control the decoder 6 in programming mode. Previously, the counter 5 is reset to zero at the reset input 14. The counter 5 receives pulses from the programming input 15. The counter 5 can be implemented, for example, on the integrated circuit 155IE2.

The decoder 6 is designed to control the synchronization inputs of D-flip-flops of groups of D-flip-flops 1, 2, 3, 7, 8, 9 according to information from counter 5.

The first programming pulse at the output of the counter 5 sets information leading to the setting of "1" at the output 6.1.1 of the decoder 6, the second at the output 6.1.2, the third at the output 6.1.3 and so on, for 3.k pulses activates all 3.k outputs of the decoder, while the information is recorded in the D-triggers of groups 1, 2, 3, 7, 8, 9.

According to the last 3.k, the 1st programming pulse is set to "1" at the last output of the decoder 6, which leads to the excitation of the output of the end of programming 17 and means the readiness to remove the values of functions from the outputs 16.1 ... 16.m.

Decoder 6 can be implemented, for example, on an integrated microcircuit 155ID3, and its control inputs must be connected to "0" V.

,Conjunction blocks 10 in the amount of k, where k is the number of conjunctions in the calculated system of logical functions, with the proposed structure and the corresponding relationships, are designed to calculate each bit of this conjunction by the corresponding bit of the input vector using 2 × 2HE-AND-OR logic elements that implement the function

,

The third group of inputs 10.i.3 of each i-th block of conjunctions 10.i are the inputs of the variables of the device 12.

,Blocks of values of conjunctions 11 in the amount of k, where k is the number of conjunctions in the calculated system of logical functions, with the proposed structure and corresponding relationships, are designed to calculate the values of conjunctions according to the corresponding results of calculating all its bits in the blocks of conjunctions using logical elements 2 · 2НЕ-И- OR implementing a function

,

The inputs of 12 variables with the capacity of n are intended for receiving input variables (input vector) and transmitting it to the third group of inputs of all conjunction blocks.

Tuning inputs 13 (data inputs) of bit n are designed to receive tuning information - k main (XOi), additional (XDi) masks and output signal masks (ZBi), i = 1 ... k in order to write this information to triggers of groups 1, 2 , 3, 7, 8, 9 to provide computations of systems of logical functions for the corresponding conjunctions.

The reset input 14 is intended to receive a zeroing pulse of a device for zeroing D-flip-flops of groups 1, 2, 3, 7, 8, 9 and counter 5.

The programming input 15 is intended for receiving programming pulses controlling the counter 5.

The group m of outputs of the values of the functions 16.1-16.m is intended for the output of the values of m logical functions calculated in the blocks for calculating the functions 4.1-4.m.

The output of the end of programming 17 is intended to provide a signal of the end of programming from the last output of the decoder 6, by which external devices are allowed to receive the results of calculations.

, где k=int log₂(n), (n=2^k), предназначены для вычисления соответствующей j-й выходной функцииIn each j-th block 4.j, the calculation of the functions of k groups 18.1 ... 18.k n-1 of pyramidally connected elements 2 · 2НЕ-AND-OR, realizing the function

, where k = int log ₂ (n), (n = 2 ^k ), are intended to calculate the corresponding jth output function

according to the results of calculations in blocks of conjunction values, when the result of calculating the corresponding i-th conjunction in the i-th block of conjunction values is zero:

(z _i = 0),

the conjunction is equal to unity, and this conjunction is included in the corresponding function of the system of logical functions:

(z _ioo = 1).

These elements can be implemented, for example, as described in patent No. 2438234 of 12/27/2011.

, предназначены для вычисления функцииIn each block of conjunctions 10n elements 19-24, 2 · 2НЕ-AND-OR, implementing the function

are intended to calculate the function

Highlighting by conjunction with the corresponding bit of the main mask (o) the significant bits in the input vector, and summing modulo two values of this i-th bit, if it is significant, with an additional mask (d).

, где k=int log₂(n),(n=2^k), и дополнительный элемент 26 предназначены для вычисления функцииIn each ith block of conjunction values 11 k groups 25.1 ... 25.k n-1 pyramidally connected elements 25, 2 · 2NE-AND-OR, implementing the function

, where k = int log ₂ (n), (n = 2 ^k ), and additional element 26 are used to calculate the function

equal to unity, when “zeros” are obtained for all digits z _{i of a} given n-bit conjunction, that is, the corresponding conjunction covers the input vector (equal to unity or true).

A programmable logic device operates in the following modes: 1) programming (or recording); 2) calculations in the absence of failures; 3) calculations in the presence of failures.

In programming mode (or settings), the device operates as follows.

In the initial state, D-flip-flops of groups 1, 2, 3, 7, 8, 9, counter 5 are reset to zero at the reset input 14 of the device (Fig. 1).

According to the first pulse received at the programming input 15 of the device, the counter 5 goes into the first state and the signal “1” appears at the output 6.1.1 of the decoder 6. According to this signal, programming information previously supplied to the data inputs 13 using technical means external to the device is recorded in the D-triggers of group 1. Information in the D-triggers of group 1 is entered from their inputs D along the edge of the signal coming from output 6.1 .1 decoder 6.

After that, using technical means external to the device, inputs 13 are used to input the programming information of the second group of D-flip-flops 2, into which it is recorded by the second programming pulse received at the input 15 of the device, along the edge of signal "1" arising at the output 6.1.2 decoder 6.

According to the third programming pulse, the output 6.1.3 of the decoder 6 is activated and the tuning information from the data inputs 13, previously supplied by external technical means, is recorded by the D inputs to the corresponding D-triggers of the third group 3.

Similarly, the recording of configuration information (programming information) in the D-triggers of group 7, 8, 9 takes place.

According to the last programming pulse at the last, separate output of the decoder 6, that is, at the output 17 of the end of programming, “1” is set, indicating the completion of the programming mode and readiness for calculations.

At the next programming cycle, the device is pre-zeroed at the input of zeroing 14, as a result of which counter 5 will be reset to zero, the initial state and “0” will appear at the output 17.

In the calculation mode, in the absence of failures, the device operates as follows.

After fixation by the technical means external to the claimed device of the readiness signal at the output 17 of the device, these external technical means supply the input vector 12 with variables, an input vector, and then the values of the calculated logical functions given by the settings of the function system are read from the outputs 16 of the device.

Information on the inputs 12 of the job variables can be supplied during programming and before it, but the reading of the information from the inputs 16 should be done by external technical means only after the device generates a signal "1" at the output 17.

It is assumed that external technical means will begin reading the calculated values 16 after the completion of transients in blocks 10, 11, 4.

Calculations are made by implementing the corresponding logical functions indicated above in blocks 10, 11, 4.

Calculations can be made in test mode.

For example, by comparing the results of calculations with the reference in the process of performing the described calculations. This can be done, for example, for individual conjunctions - by checking the correctness of the calculation of each conjunction by setting the corresponding constants that cause activation of all output functions. For example, the tests “running separate variable included in all functions”, “running inversion of a separate variable entering into all functions”, “conjunction of all variables entering into all functions”, “conjunction of inversions from all variables entering into all functions”, “A conjunction of alternating variables that is part of all functions.” There is some analogy with testing RAM.

In the calculation mode in the presence of failures, the device operates as follows.

If the test fails for certain conjunctions or functions, a decision can be made to exclude them using the appropriate configuration information, while the number of implemented conjunctions (functions) is reduced, which should be taken into account by external equipment.

In extreme cases, calculations can be performed on the efficient equipment of one conjunction (one block 10 and the corresponding block 11) and one function (block 4). At the same time, external equipment provides the alternation of programming and calculation cycles with fixing and interpretation of intermediate results of calculations. First, one function is calculated for the individual conjunctions corresponding to it, then the next and so on.

Consider examples of specific calculations of logical function systems in a programmable logic device.

1. An example of computing a system of logical functions.

Let it be necessary to calculate the following system of logical functions:

Let's make a list of conjunctions and functions that they initiate:

one)

The base (fixed sequence) of the input variables is y ₁ x ₂ x ₁ , the base of the output variables is z ₁ z ₂ . We will receive the list (array) of constants.

The basic constant X0 _i (i from 1 to 3 has three conjunctions) should highlight the essential variables, therefore it contains units in the positions of the essential variables of the ith conjunction (the positions are determined by the base of the full input word).

The additional constant XD _i corresponds to the truth values of the variables in the given conjunction; therefore, it contains ones at the positions of non-inverted variables and zeros at the remaining positions.

To excite the output functions, a third mask is needed - the output mask ZO _i , which contains units in the positions of the logical functions, which include the corresponding conjunction (the positions are determined by the base of the output functions). So, we get table 1:

Table 1 Tuning information for calculating a certain system of functions (array of masks - constants) No. Constant designation Code for input base y ₂ y ₁ x ₂ x ₁ Code at base of outputs z ₁ z ₂ Note one. X0 (1) 0011

conjunction

2. XD (1) 0010 conjunction

3. Z (1) 0010 conjunction

four. X0 (2) 0100 conjunction y ₁ (1, 2) 5. XD (2) 0100 conjunction y ₁ (1, 2) 6. Z (2) 0011 conjunction y ₁ (1, 2) 7. X0 (3) 1001 conjunction

8. XD (3) 0001 conjunction

9. Z (3) 0011 conjunction

Consider how the calculations are made. This is an improved hardware implementation of the PLA algorithm (Aleksenko A.G., Golitsyn A.A., Ivannikov A.D. Design of electronic equipment on microprocessors. - M.: Radio and communications, 1984. - S.109-111).

Let the input word y ₂ y ₁ x ₂ x ₁ = 0100. In the first block of conjunctions, the input word is bitwise masked by the first, main mask (constant):

And the bitwise addition operation is performed modulo 2 with an additional mask:

. Действительно, из входного слова видно, что, x₂=0, x₁=0. Это же видно и из результатов маскирования первой константы. А вторая константа показывает, что x₁ должен быть равен 0, x₂=1.The result is non-zero: this means that the conjunction

. Indeed, the input word shows that, x ₂ = 0, x ₁ = 0. The same can be seen from the results of masking the first constant. And the second constant shows that x ₁ should be equal to 0, x ₂ = 1.

Therefore, the output of the first block of conjunction values will be zero and the corresponding bit of the third mask (outputs) for this conjunction is ignored.

In the second block of conjunctions:

The result is zero, which means that the conjunction is y ₁ = 1 and one is formed at the output of the second block of conjunction values.

Therefore, units are formed in the last two blocks of function calculation, since the value of the mask Z (2) = 0011, that is, the second conjunction excites both the first function and the second.

In the third block of conjunctions:

The result is nonzero, therefore, at the output of the third block of conjunction values - zero and the third mask Z (3) in the function calculation blocks are ignored.

In hexadecimal code, the device programming array is as follows:

03H, 02H, 02H, 08H, 08H, 03H, 06H, 06H, 02H.

This array is loaded into the D-triggers of groups 1, 2, 3, 7, 8, 9 during programming.

2. An example implementation of a finite state machine.

When implementing (calculating) the system of logical functions of a finite state machine, its status code must be stored in equipment external to the device (external triggers or a register are necessary). Consider an example of the implementation of such a system of functions, and for simplicity we will not minimize functions.

Let there be given a table of transitions-outputs of some Miley recognition automaton (table 2).

table 2 Transition-output table of some automaton Status Code Y ₂ Y ₁ ab 00 01 eleven 10

00H

01H

03H 02H

00 04H

05H

07H

06H 01 0CH 0DH

0FH

0EH

eleven

Let the base of the input word have the form y ₂ y ₁ (t) ab (fed to inputs 12), the base of the output word y ₂ y ₁ (t + 1) z ₂ z ₁ (formed at outputs 16).

The following is a table of constants, which is derived from the transition table of the TABL outputs:

db 0FH, 01H, 04H,

db 0FH, 02H, 02H,

db 0FH, 04H, 06H,

db 0FH, 05H, 04H,

db 0FH, 07H, 0CH,

db 0FH, 0DH, 0EH,

db 0FH, 0FH, 0CH,

db 0FH, 0EH, 0DH.

Let us consider in more detail how they are obtained, using the example of the first three constants. The first constant 00FH is the same for all conjunctions: the least significant 4 bits are significant, because base of input word y ₂ y ₁ (t) ab. The input variables ab are the 2 least significant bits, then there are two bits that store the state code of the memory of the automaton Y ₂ Y ₁ .

. Аналогично получают остальные константы. Этот массив из троек констант загружается в D-триггеры групп 1, 2, 3, 7, 8, 9 в процессе программирования.The following constants are the code of the cell with non-zero contents (for example 01H). The last constant is obtained as follows. They take the contents of the cell, combine the numerator and denominator and translate it into a hexadecimal code:

. The rest of the constants get the same. This array of triples of constants is loaded into the D-triggers of groups 1, 2, 3, 7, 8, 9 during programming.

In blocks 4, the values y ₂ y ₁ (t + 1) z ₂ z _{1 are formed} . The functions y ₂ y ₁ (t + 1) are written into an external register from which the state variables y ₂ y ₁ are transferred to the corresponding inputs 12.

3. An example of diagnosing a device.

For simplicity, we consider a device with n = 4, m = 4, k = 4.

The test "running unit" is proposed - table 3:

Table 3 Running unit test No. Inputs 12 XO Xd Zo one. 1111 1000 1000 1000 2 - 0100 0100 0100 3 - 0010 0010 0010 four. - 0001 0001 0001

Each conjunction, consisting of one variable, activates "its" function. The outputs of the device 16 are all units. The “running zero” test is proposed - table 4:

Table 4 Running unit test No. Inputs 12 XO Xd Zo one. 0000 1000 0000 1000 2 - 0100 0000 0100 3 - 0010 0000 0010 four. - 0001 0000 0001

Each conjunction, consisting of one inverse variable, activates "its" function. The outputs of the device 16 are all units.

The “all units” test is proposed - table 5:

Table 5 All Unit Test No. Inputs 12 XO Xd Zo one. 1111 1111 1111 1000 2 - 1111 1111 0100 3 - 1111 1111 0010 four. - 1111 1111 0001

Each conjunction, consisting of all variables, activates "its" function. The outputs of the device 16 are all units.

The “all zeros” test is proposed - table 6:

Table 6 All Zeros Test No. Inputs 12 XO Xd Zo one. 0000 1111 0000 1000 2 - 1111 0000 0100 3 - 1111 0000 0010 four. - 1111 0000 0001

Each conjunction, consisting of inversions of all variables, activates “its” function. The outputs of the device 16 are all units.

Similarly, you can offer tests for each conjunction, checking how this conjunction activates all functions, for example, for the first conjunction - tables 7-8:

Table 7 Test "check the first unit conjunction" No. Inputs 12 XO Xd Zo one. 1111 1111 1111 1111 2 - 0000 0000 0000 3 - 0000 0000 0000 four. - 0000 0000 0000

The first conjunction, consisting of all variables, activates all functions. The outputs of the device 16 are all units.

Table 8 Test "check the first zero conjunction" No. Inputs 12 XO Xd Zo one. 0000 1111 0000 1111 2 - 0000 0000 0000 3 - 0000 0000 0000 four. - 0000 0000 0000

The first conjunction, consisting of inversions of all variables, activates all functions. The outputs of the device 16 are all units.

Similarly, other tests may be proposed.

4. An example of parry failure.

The device can fend off failures in computing conjunctions - blocks 10, 11, identified by the above diagnosis. For this, a defective conjunction corresponding, for example, to z ₁ in the expression

is disabled by setting, for example, z1o1 = 0, while the number of realized conjunctions is reduced by one.

In the extreme case, when the technical means for only one workable conjunction remain, the device can be used for software and hardware calculation in several clock cycles, using external technical means, by alternating the programming cycles of each next conjunction and calculating the functions corresponding to it.

The device can counter the failure of the calculation of functions in blocks 4 by eliminating this function, while the number of output functions is reduced.

In the extreme case, when the technical means remain for only one functional function (only one block 4), the device can be used for software and hardware calculation in several clock cycles, using external technical means, by alternating cycles of programming conjunctions and calculating the corresponding function. That is, in one cycle, only one function will be calculated, possibly depending on many conjunctions.

It is also possible to work on one of the two remaining operable lobes of blocks 4, by turning off the failed (not forming the necessary unit) signals z _ioi = 0, z _i .

We will evaluate the technical and economic efficiency of the proposed device.

, для инверсий переменных элементов. Кроме того, необходимо по 2n·2ⁿ триггеров настройки.In the prototype for the implementation of n blocks of functions (we take n = m) it is necessary n · [(2 ⁿ -1) + n], where (2 ⁿ -1) is the number of elements for implementing a multiplexer for 2 ⁿ channels, (+ n) - the number of elements 2 · 2NE-AND-OR that implement the function

, for inversions of variable elements. In addition, 2n2 ⁿ trigger settings are required.

In the proposed device for the implementation of an n-bit conjunction block, 6 elements are needed per variable 6 n, n-1 element for a block of conjunction values of n elements for a function calculation block.

If there are k conjunctions (we take n = m), then everything will be:

k (6n + n-1 + n) = k (8n-1)

Triggers settings need 3 kn.

Thus, the gain in the number of elements is described by the expression:

The gain in the number of triggers is described by the expression:

.

.

So, if n = m = 8, k = 10, we get:

The achievement of the technical result of the invention is confirmed by the above estimates.

Claims (1)

A programmable logic device containing the first, second, and third groups of D-flip-flops of quantity n, where n is the bit depth of the calculated logical functions, the group m of function calculation blocks, where m is the number of calculated logical functions, a counter, a decoder, and the information inputs of D-flip-flops from groups of D-flip-flops are connected to the corresponding bits of the data inputs, the reset inputs of all D-flip-flops of all groups of D-flip-flops and the counter reset input are combined and connected to the device reset input, the counter output is connected to the decoder input RA, the first output of the decoder is connected to the synchronization inputs of the D-flip-flops of the first group of D-flip-flops, the second output of the decoder is connected to the synchronization inputs of the D-flip-flops of the second group of D-flip-flops, the third output of the decoder is connected to the synchronization inputs of the D-flip-flops of the third group of D-flip-flops, the outputs of the group m of function calculation blocks are the outputs of the device, each function calculation block contains k groups of n-1 elements 2 · 2NE-AND-OR that implement the function

, where k = intlog ₂ (n), (n = 2 ^k ), in the first group there are n / 2 elements, in each group of elements there are two times less than in the previous one, in the last one element, that is, there is a “pyramidal” connection of elements, and the outputs of the odd elements of odd groups are connected to the first inputs of the corresponding elements of the next even group of 2 · 2HE-AND-OR elements that implement the function

, two elements of the odd group correspond to one element of the even group, the outputs of the even elements of the first group of 2 · 2НЕ-AND-OR elements that implement the function

are connected to the fourth inputs of the next even group of 2 · 2HE-AND-OR elements that implement the function

, characterized in that k-1 groups of first D-flip-flops of quantity n are additionally introduced, where n is the capacity of the calculated logical functions, k is the number of computable conjunctions in the system of m functions, k-1 is the group of second D-flip-flops of n, k- 1 groups of third D-triggers of n number, group k of conjunction blocks, group of k blocks of conjunction values, and the information inputs of D-triggers k-1 of groups of the first D triggers, second D triggers, third D-triggers are connected to the corresponding bits of data inputs, inputs reset D-triggers k-1 groups of the first D triggers Er, second D flip-flops, third ones are connected and connected to the device reset input, synchronization inputs of D-flip-flops of k-1 groups of the first D-flip-flops are connected to the corresponding k-1 decoder outputs for k-1 groups of the first D flip-flops, synchronization inputs of D-flip-flops k-1 groups of second D-flip-flops are connected to the corresponding k-1 decoder outputs for k-1 groups of second D-flip-flops, synchronization inputs of D-triggers of k-1 groups of third D-flip-flops are connected to the corresponding k-1 decoder outputs for k-1 groups of third D flip-flops, outputs of the group of first D-flip-flops the ditch is connected to the first group of inputs of the first conjunction block, the outputs of the group of second D-triggers are connected to the second group of inputs of the first conjunction block, the third groups of inputs of all conjunction blocks are connected to the input of the device variables, the outputs k-1 of the groups of the first D-triggers are connected to the first groups the inputs of the corresponding k-1 conjunction blocks, the outputs of k-1 groups of the second D-triggers are connected to the second groups of inputs of the corresponding k-1 conjunction blocks, the outputs of the conjunction blocks are connected to the inputs of the corresponding blocks of nunjunctions, outputs of blocks of conjuncture values are connected to the corresponding inputs of conjunctions of each function calculation block, outputs of k-1 groups of third D-triggers are connected to the corresponding inputs of blocks of function values, and the odd inputs of the first group of 2 · 2НЕ-AND-OR elements that implement the function

are connected to the corresponding inputs of the first group of inputs of the function calculation unit, the even inputs of the first group of 2 · 2NE-AND-OR elements that implement the function

are connected to the corresponding inputs of the second group of inputs of the function calculation block, the outputs of the odd elements of the odd groups of elements 22 · 2NE-AND-OR, implementing the function

connected to the third inputs of the corresponding elements of the second group of elements 2 · 2NE-AND-OR, implementing the function

, outputs of even elements of the first group of elements 2 · 2NE-AND-OR, implementing the function

connected to the second inputs of the second group of elements 2 · 2NE-AND-OR, implementing the function

, outputs of the penultimate group of elements 2 · 2NE-AND-OR, implementing the function

, contain two 2 · 2HE-AND-OR elements that implement the function

, and the output of the first element of the penultimate group is connected to the first and second inputs of the only element of the last group, and the output of the second element of the penultimate group is connected to the third and fourth inputs of the only element of the last group, the output of which is the output of the function calculation block, with each i-th block conjunctions contains n groups of values of digits, each of which contains 6 elements 2 · 2NE-AND-OR, implementing the function

and the inputs of the first three elements are combined, the input of the first element is connected to the corresponding i-th input of the third group of inputs of the conjunction block and to the first two inputs of the fourth element, the input of the second element is connected to the corresponding i-th input of the first group of inputs of the conjunction block and to the third and the fourth inputs of the fourth element, the input of the third element is connected to the corresponding i-th input of the second group of inputs of the conjunction block and to the second input of the sixth element, the output of which is the i-th output of the i-th conjunction block, the output of the first element is connected to the first and third inputs of the fifth element, the output of the second element is connected to the second and fourth inputs of the fifth element, the output of the third element is connected to the third input of the sixth element, the output of the fourth element is connected to the first input of the sixth element, and the output of the fifth element is connected to the fourth input of the sixth element, the third group of inputs of each conjunction block is the device variable inputs, and each i-th block of conjunction values contains k groups of n-1 elements 2 · 2 NOT-AND-OR, p implementing function

, where k = intlog ₂ (n), (n = 2 ^k ), that is, there is a "pyramidal" connection of elements, and an additional element, the first and second inputs of the first group of elements 2 · 2NE-AND-OR, implementing the function

connected to the corresponding odd inputs of the block of conjunction values, the third and fourth inputs of the first group of 2 · 2NE-AND-OR elements that implement the function

are connected to the corresponding odd inputs of the block of conjunction values, the outputs of the odd elements of the first group of elements 2 · 2NE-AND-OR, implementing the function

connected to the odd inputs of the second group of elements 2 · 2NE-AND-OR, implementing the function

, outputs of even elements of an odd group of 2 · 2НЕ-AND-OR elements realizing a function

connected to the even inputs of an even group of 2 · 2HE-AND-OR elements that implement the function

, outputs of the penultimate group of elements 2 · 2NE-AND-OR, implementing the function

, contain two 2 · 2HE-AND-OR elements that implement the function

, and the output of the first element of the penultimate group is connected to the first and second inputs of the only element of the last group, and the output of the second element of the penultimate group is connected to the third and fourth inputs of the only element of the last group, the output of which is connected to all inputs of the additional element, the output of which is the output of the value block conjunctions.

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