RU2379829C1 - Backup counter for generating time marks - Google Patents

Abstract

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to computer and pulse engineering and can be used in designing highly reliable backup systems for counting and processing digital information. The device consists of m channels, each with a control unit, an n-bit counter, a unit of n majority decision elements, a majority decision element, a monostable multivibrator, a multiplexer, a digital comparator, a first, second and m^th shift register, a slave counter, programmable memory, first and second decoders. A random failure occurring during operation in any channel of the backup counter will be countered in time T (input pulse period) by restoring correct information in each of the n-bit counters (5). The device is significantly simplified due to cutting on the number of elements providing inter-channel communication and amount of converted information.

EFFECT: simple circuit design of the device.

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Description

The present invention relates to computing and pulsed technology and can be used in systems using program-time devices.

Known redundant counter for the formation of time stamps, the description of which is given in [1]. The device contains 3 pairs of input buses and 3 channels, each of which contains bits, including a trigger, two AND elements and a majority element.

This device allows you to issue true information (form timestamps at a given time) in the presence of failures less than the majority number M, [M = (m + 1): 2] in each reserved digit of the counter. But with the accumulation of failures, their number in one category can exceed the number M, as a result of which the information in the counter becomes false, which is unacceptable. The counter itself does not recover information in the category that failed. The probability of failure of the redundant counter (and, consequently, the incorrect formation of time stamps) increases significantly if the operating time of this counter is large enough.

The closest technical solution to the proposed one is a redundant counter for forming time stamps [2], containing m channels, and in each channel an n-bit counter, a block of n majority elements and series-connected majority element and one-shot, the output of which is connected to the input C n -digit counter, input D of parallel recording of which is connected to the output bus of the block of n majority elements.

This device can independently recover information lost in the presence of failures, the number of which is less than the majority number M [M = (m + 1): 2] in each digit of the counter. This allows you to create timestamps at a given time despite individual meter failures.

The disadvantage of this device is that it has a large number of inter-channel connections, and, as a result, each such connection requires the installation of an additional matching device (for example, an optocoupler), since each channel is powered by a power source that is galvanically disconnected in many cases from a power source other channels. In addition, modern digital circuits are implemented on the basis of programmable logic integrated circuits (FPGAs) with a high degree of integration, which allows the implementation of logically complex circuits in one FPGA. A large number of inter-channel communications requires a large number of FPGA conclusions, which leads to the need to use two or more FPGAs or a more expensive FPGA with a large number of conclusions. In addition, the disadvantage of this device is that the formation of time stamps is performed by converting the code information of all bits of the counter, which requires a large number of elements involved in the conversion, and this complicates the device.

The objective of the invention is to simplify the device by reducing the number of inter-channel communications and reducing the amount of information being converted.

This task is achieved by the fact that in a redundant counter for forming time stamps containing m channels, and in each channel an n-bit counter, a block of n majority elements and series-connected majority element and one-shot, the output of which is connected to the input C of the n-bit counter , the parallel recording input D of which is connected to the output bus of a block of n majority elements, a multiplexer, a control unit, first, second and mth shift registers, a digital comparator, a controlled counter, and a program are entered into each channel mummable memory device, the first and second decoders, while in each channel the output of a single vibrator is connected to the first input of the controlled counter and the input of the control unit, the first and second outputs of which are connected to the PE inputs of the parallel recording of the n-bit counter and the first shift register, respectively, the third the control unit output is connected to the input C of the first shift register and the inputs C of the corresponding shift registers of other channels, the inputs D of which are connected to the output of the first shift register, the inputs D of a pair which records are connected to the output bus of the n-bit counter, the input bus B of the digital comparator and the first input bus of the block of n majority elements, the second and mth input buses of which are connected to the output buses of the second and mth shift registers, respectively, the input bus A digital comparator is connected to the data bus of the programmable storage device, the address bus of which is connected to the output bus of the controlled counter and the input bus of the first and second decoders, the control input of which is connected to by the stroke A = B of the digital comparator and the second input of the controlled counter, the output bus of the first decoder is connected to the output bus of the device, the output bus of the second decoder is connected to the input bus of the multiplexer, the inputs of which are connected to the corresponding inputs of the device, the output of the multiplexer of each channel is connected to the corresponding inputs of the majority element all channels.

The controllable counter contains a trigger, a generator, an AND element, a counter, first and second control inputs, wherein the generator output is connected to the first input of the And element, the second input of which is connected to the trigger output, the input of which is connected to the first control input and the counter input R, the third input of the element And is connected to the inverse output of the last bit of the counter, the input of which is connected to the output of the element And, the input R of the trigger is connected to the second control input, the outputs of each bit of the counter are connected to the output bus of the controlled account chica.

Figure 1 shows a block diagram of a redundant counter for forming time stamps, where 1 is a majority element, 2 is a one-shot, 3 is a control unit, 4 is a block of n majority elements, 5 is an n-bit counter, 6, 7 and 8 - first, second and m - and shift registers, 9 - multiplexer, 10 - digital comparator, 11 - controlled counter, 12 - programmable storage device, 13 - first decoder, 14 - second decoder, 15 - output bus, 16 - first channel 17 - the second channel, 18 - the m-th channel.

Figure 2 shows a block diagram of a controlled counter, where 19 is a trigger, 20 is a generator, 21 is an I element, 22 is a counter, 23 is a first control input, 24 is a second control input, 25 is an output bus of a controlled counter.

The redundant counter for forming time stamps contains m channels, each of which includes a majority element 1, a single-shot 2, a control unit 3, an n-bit counter 5, a block of n majority elements 4, the first 6, the second 7 and the mth 8 shift registers , multiplexer 9, digital comparator 10, controllable counter 11, programmable memory 12, first decoder 13, second decoder 14, output bus 15. In each channel, the majority element 1 and the one-shot 2 are connected in series, the output of which is connected to the input of the control unit 3, the first input of the controlled counter 11 and the input C of the n-bit counter 5, the parallel recording input D of which is connected to the output bus of a block of n majority elements 4. The output of the multiplexer 9 of each channel is connected to the corresponding inputs of the majority element of all channels. The first and second outputs of the control unit 3 are connected to the inputs PE for parallel recording of the n-bit counter 5 and the first shift register 6, respectively, the third output of the control unit 3 is connected to the input C of the first shift register 6 and the inputs C of the corresponding shift registers of other channels, inputs D which are connected to the output of the first shift register 6, the parallel recording inputs D of which are connected to the output bus of the n-bit counter 5, the input bus B of the digital comparator 10, and the first input bus of the block of n majority elements ov 4, the second and mth input buses of which are connected to the output buses of the second 7th and mth 8th shift registers, respectively. The input bus A of the digital comparator 10 is connected to the data bus of the programmable storage device 12, the address bus of which is connected to the output bus of the controlled counter 11 and the input bus of the first 13 and second 14 decoders, the control input of which is connected to the output A = B of the digital comparator 10 and the second input managed counter 11. The output bus of the first decoder 13 is connected to the output bus of the device 15, the output bus of the second decoder 14 is connected to the input bus of the multiplexer 9, the inputs of which are connected to the corresponding device inputs.

The controlled counter of figure 2 contains a trigger 19, a generator 20, an element And 21, a counter 22, a first control input 23, a second control input 24 and an output bus of a controlled counter 25. The output of the generator 20 is connected to the first input of the element And 21, the second input of which is connected with the output of the trigger 19, the input S of which is connected to the first control input 23 and the input R of the counter 22. The third input of the element And 21 is connected to the inverse output of the last bit of the counter 22, the input of which is connected to the output of the element And 21. The input R of the trigger 19 is connected to the second control input 24, the outputs of each category of the counter 22 are connected to the output bus of the managed counter 25.

The redundant counter works as follows (for simplicity we assume m = 3 and that all n - bit counters 6 are in the zero state). Let the input sequences of pulses τ _qi (i = 1, 2, 3) with the intervals τ _q1 , τ _q2 and τ _{q3 be} received at the inputs of multiplexer 9 of channel q (q = 1, 2, ... m). We assume that τ _q1 = τ ₁ = 1 hour, τ _q2 = τ ₂ = 1 min, τ _q3 = τ ₃ = 1 s, and the pulses τ _qi arrive synchronously. We also assume that when a pulse arrives from the output of a one-shot 2 to the input of the control unit 3, the following signals are generated at its outputs: a pulse P ₁ is formed at the first output, allowing parallel writing to the n-bit counter 5 of the code information of the output bus of the block of n majority elements 4 , a pulse P ₂ is generated at the second output, allowing parallel writing to the first shift register 6 of the code information of the output bus of the n-bit counter 5, a sequence of n pulses T _{n with a} frequency is generated at the third output following T ₀ . We assume that the first in time pulse is formed P ₂ , then a sequence of pulses T _n is formed and then the pulse P _{1 is formed} . We will also assume that the period of the input pulses is T> n T ₀ , and during the time T all signals from the outputs of the control unit 3 are formed: pulses P ₁ , P ₂ and the sequence T _n .

Let it be required to generate I = 5 timestamps M _j , while the time intervals T _j (j = 1, 2, ... 5) between adjacent timestamps are respectively equal to:

where the coefficients p _ji vary from zero to 59 (in this case, the ratio τ _i / τ _{(i + 1)} = K = 60). For simplicity, let p ₁₁ = p ₂₁ = p ₃₁ = p ₄₁ = p ₅₁ = 2, p ₁₂ = p ₂₂ = p ₃₂ = p ₄₂ = p ₅₂ = 8, p ₁₃ = p ₂₃ = p ₃₃ = p ₄₃ = p ₅₃ = 12.

Let pulses τ _qi synchronized in time be received at the inputs of each channel of the redundant counter to form time _stamps . In this case, when the next input pulses appear at the output of the majority element 1 of each channel, a signal is generated that goes to the input of the one-shot 2, which generates a pulse at the input C of the n-bit counter 5, at the first input of the controlled counter 11 and the input of the control unit 3. This pulse summed with the contents of the n-digit counter 5 enables the summation with the pulse generator 20, a counter 22 (Figure 2) and carries out start signal generation program P _1, P ₂ and T _n control unit 3. Consider first passage weekend x control unit 3. The generated signals by the first clock signal P ₂ performs recording the first parallel shift register 6 code information bus output n-bit counter 5. The formed further sequence of n T _n of pulses is input from the first shift register 6 and inputs C corresponding shift registers of other channels and transmits code information from the output of the first shift register 6 to the inputs D of the corresponding shift registers of other channels. Thus, after the passage of the nth pulse of the sequence T _n in each channel, the code state of the second 7 and mth 8 shift registers will correspond to the code state of the n-bit counter 5 of the other channels. As a result, code information of n-bit counters 5 of all channels is generated at the corresponding inputs of a block of n majority elements 4 of each channel (we believe that a block of n majority 4 elements contains n majority elements and the inputs of the d-th majority element of each input bus, d = 1, 2 (n are connected respectively to the outputs of the dth bit of the n-bit counter 5 and the corresponding shift registers of this channel).

At each output d of the output bus of the block of n majority elements 4, a state will be formed corresponding to the state of most dx bits of n-bit counters 5 of all channels. The code state of the output bus of a block of n majority elements 4 of each channel will correspond to the true value if, for some reason, the number of failures in any dx bits does not exceed the number M [M = (m + 1): 2]. The pulse P _1, which is further formed by the control unit 3 at the second output, will write to the n-bit counter 5 all channels of the code state of the block of n majority elements 4. Thus, if for some reason the information in the n-bit counter 5 of any channel turned out to be unreliable, it will be restored by the output pulse P ₁ at the time of writing to the n-bit counter 5 of all channels of the code state of a block of n majority elements 4.

The output pulse N _{K of the one-} shot 2 is supplied to the first input 24 of the controlled counter 11 (figure 2), sets the trigger 19 to a single state, and the counter 22 to a zero state. In this case, the second and third inputs of the And 21 element will have high levels and the output signals of the generator 20 will pass from the output of the And 21 element to the input From the counter 22. The counter 22 will count the pulses of the generator 20 until the last discharge of the counter 22 is in a single state. In this case, from the inverse output of the last discharge of the counter 22, the third input of the element And 21 will receive a low level and the element And 21 blocks the passage of the pulses of the generator 20. In this state, the controlled counter will remain until the next output pulse N _{K of the one-} shot 2. Stop counting pulses the generator 20 also occurs in the case of a signal from the output A = B of the digital comparator 10 being supplied to the second input 23 of the controlled counter 11. This signal sets the trigger 19 to zero and forms at its output low level. We assume that the generator 20 generates pulses with a frequency of T _G , and, I T _G <τ ₃ (τ ₃ is the minimum period of the input pulses).

Let the initial state of an n-bit counter 5 R ₁₀ and a controlled counter 11 R ₂₀ , with R ₁₀ = R ₂₀ = 0. In what follows, the number recorded in the n-bit counter 5 will be denoted by R _1X , and the number recorded in the managed counter 11 will be denoted by R _2X . The digital signal R _1X is formed by sequentially summing p _ji pulses of those sequences that determine the time T _j , and in the time interval T _j we will sequentially sum at first p _j1 pulses with a maximum repetition period τ ₁ , then p _j2 pulses with a shorter repetition period τ ₂ and at the end of p _jn pulses with the smallest repetition period τ _n , the timestamps M _j will be formed at time instants t _r (r = 1, 2, ... m), when digital signal C is equal to

Let R _2X = 1 programmable memory (ROM) 12 connects to its output a cell with the address R _2X = 1, the contents of which A = p ₁₁ = 2, and the second decoder 14 with R _2X = 0 generates such a code on its output D , which sets the multiplexer 9 in a state in which a pulse sequence τ _{q1 is} connected to its output. We believe that the first 13 and second 14 decoders convert the information on the input bus that took place at the time the signal from the output A = B of the digital comparator 10 arrived at the control input, and did not change its output signal until the next signal A = B arrived. After the first pulse arrives from the output of the one-shot 2, the controlled counter 11 will change its output signal R _2X from zero to the maximum, at which the state of the last discharge of the counter 22 will not be single. In this case, on the comparator bus A, all the numerical values generated by the ROM will appear, but none of these values will be equal to the current value of the digital information of the n-bit counter 5 R _1X and until the moment the information changes at the output of the n-bit counter 5 a signal A = B be generated. Thus, until the information R _1X = p ₁₁ = 2 appears at the output of the n-bit counter 5, the pulses will be counted from the output of the one-shot 2 by the n-bit counter 5, and the output information of the first 13 and second 14 remains unchanged. At the same time, each time a pulse arrives from the output of one-shot 2, the correct information is restored in each n-bit counter 5 if, for some reason, a failure occurs in any discharge.

When the next pulse N _K arrives from the output of the one-shot 2, the state of the n-bit counter is 5 R _1X = B = p = ₁₁ = 2, and when the state of the controlled counter is 11 R _2X = 1, the signal A = 2 is generated on the output bus of the ROM 12. In this case, at the output A = B of the digital comparator 10, a signal S = 1 is generated, which stops the pulse count from the generator 20 by the counter 22 and allows the formation of the output information by the first 13 and second 14 decoders with the code state on the input bus R _2X = 1. Suppose that for R _2X = 1, the second decoder 14 generates at its output D such a code that sets the multiplexer 9 to a state in which a pulse sequence τ _{q2 is} connected to its output, and the ROM at

R _2X = 2 connects to the output a cell with address 2, the contents of which A = p ₁₁ + p ₁₂ = 2 + 8 = 10. With the output signal of the n-bit counter 5 R _1X = p ₁₁ + p ₁₂ = 10, the signal A = 10 is formed on the bus A of the digital comparator 10, with R _2X = 2 and the output A = B of the digital comparator 10, the signal S = 1 is generated, which stops the pulse count from the generator 20 by the counter 22 and allows the formation of the output information by the first 13 and second 14 decoders with a code state on the input bus R _2X = 2.

Suppose that when R _2X = 2, the second decoder 14 generates at its output D such a code that sets the multiplexer 9 to a state in which the pulse sequence τ _{q3 is} connected to its output, and the ROM at R _2X = 3 connects the cell with the address 3 to the output, the contents of which A = p ₁₁ + p ₁₂ + p ₁₃ = 2 + 8 + 12 = 22. With the output signal of the n-bit counter 5 R _1X = p ₁₁ + p ₁₂ + p ₁₃ = 22, the signal A = 22 is generated on the bus A of the digital comparator 10, at R _2X = 3 and the signal A is generated at the output A = B of the digital comparator 10 = 1, which stops the pulse count from the generator 20 by the counter 22 and allows the formation of the output information by the first 13 and second 14 decoders with the code state on the input bus R _2X = 3.

Since the digital signal C = C ₁ = p ₁₁ + p ₁₂ + p ₁₃ , in this case, according to (6), the time stamp M ₁ is formed at the output of the first decoder 13, while the current time t = t ₁ = T ₁ . Next, the ROM connects to the output a cell with the address R _2X = 4, the contents of which A = p ₁₁ + p ₁₂ + p ₁₃ + p ₂₁ = 22 + 2 = 24, and the second decoder 14 generates at its output D with R _2X = 3 such a code that sets the multiplexer 9 to a state in which a pulse sequence τ _{q1 is} connected to its output. Further, the process of forming time stamps M ₂ , M ₃ , M ₄ and M _{5 is} similar to the process described above. When C = C ₂ = C ₁ + p ₂₁ + p ₂₂ + p ₂₃ according to (6), a time stamp M _{2 is formed} , while the current time t = t ₂ = T ₁ + T ₂ .

The switching law of the multiplexer 9 with known coefficients p _{ji is} very simple. If, for example, n = 3, then the control bus D of multiplexer 9 should contain 2 bits, while code 01 may correspond to connecting 2 pulses τ _q1 to the output of the multiplexer, code 02 may correspond to connecting 2 pulses τ _q2 to the output of the multiplexer, code 03 may correspond to the connection to the output of the multiplexer 2 pulses τ _q3 . If p _ji ≠ 0, then all numbers R _2X = 3d (d = 1, 2, ...) correspond to code 01, all numbers R _2X = 3d + 1 correspond to code 02, all numbers R _2X = 3d + 2 correspond to code 03.

The effect of using the present invention is to simplify implementation by reducing the number of inter-channel communications and reducing the amount of information being converted. Show it. Suppose the number n = 30. In this case, to implement a redundant counter according to the well-known scheme [2], 120 inter-channel communications will be required (each bit requires 4 inter-channel communications). In addition, the implementation of these links will require the installation of 60 optrons in each channel. If a redundant counter is implemented on an FPGA with 64 pins, three such FPGAs will be required instead of one.

To implement a redundant counter according to the proposed scheme, 6 inter-channel communications and the installation of 4 optocouplers are required in each channel

The implementation of the redundant counter according to the proposed scheme can be performed on one FPGA in each channel. Otherwise, the proposed redundant meter circuit is much simpler than the known solution [2] by reducing the number of inter-channel communications.

In the known solution [2], the formation of the time stamp occurs when the current time, fixed in the n-bit counter, coincides with the set one. For the case under consideration, the maximum time T _M , which must be compared with the specified one, will be T _M = T ₁ + T ₂ + T ₃ + T ₄ + T ₅ = 38460 s. Representing such numbers requires 16 bits. In a device that implements the proposed method of forming time stamps, the digital signal C, the maximum value of which is equal to

For the case under consideration, this number is C = 110. To represent this number, 7 bits are required.

The proposed set of features, in the solutions considered by the author, was not met to solve the problem and does not follow explicitly from the prior art, which allows us to conclude that the technical solution meets the criteria of "novelty" and "inventive step". As the majority elements, counters, shift registers, digital comparators, multiplexers, programmable storage device, etc. to implement the device, you can use the logical elements of digital circuits of any series, for example 564, etc.

Literature

1. USSR author's certificate N 982197, cl. H03K 21/40, 1982. Redundant pulse counter.

2. Patent of the Russian Federation N 2103815, cl. 7 Н03К 21/40, 21/10, 23/50 from 01/27/98. Reserved counter.

Claims (2)

1. A redundant counter for forming time stamps containing m channels, and in each channel an n-bit counter, a block of n majority elements and series-connected majority element and one-shot, the output of which is connected to the input C of the n-bit counter, parallel recording input D which is connected to the output bus of a block of n majority elements, characterized in that a multiplexer, a control unit, first, second and mth shift registers, a digital comparator, a controlled counter, programmable are introduced into each channel a storage device, first and second decoders, while in each channel the output of a single vibrator is connected to the first input of the controlled counter and the input of the control unit, the first and second outputs of which are connected to the PE inputs of the parallel recording of the n-bit counter and the first shift register, respectively, the third output the control unit is connected to the input C of the first shift register and the inputs C of the corresponding shift registers of other channels, the inputs D of which are connected to the output of the first shift register, the inputs D parallel to whose records are connected to the output bus of the n-bit counter, the input bus B of the digital comparator and the first input bus of the block of n majority elements, the second and mth input buses of which are connected to the output buses of the second and mth shift registers, respectively, the input bus A the digital comparator is connected to the data bus of the programmable storage device, the address bus of which is connected to the output bus of the controlled counter and the input bus of the first and second decoders, the control input of which is connected to the output A = V c Frova comparator and a second control input of the counter, the first output bus coupled to the decoder output bus of the device, the second output line of the decoder is connected to an input bus multiplexer whose inputs are connected to respective inputs of the device, each channel multiplexer output is connected to respective inputs of a majority component of all channels. 2. A redundant counter for forming time stamps according to claim 1, characterized in that the controllable counter comprises a trigger, a generator, an And element, a counter, first and second control inputs, wherein the generator output is connected to the first input of the And element, the second input of which is connected with the trigger output, the input S of which is connected to the first control input and the counter input R, the third input of the And element is connected to the inverse output of the last bit of the counter, the input From which is connected to the output of the And element, the trigger input R is connected to the second control input phenomenon, the outputs of each counter are connected to a discharge output bus managed counter.

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