RU2342690C1 - Relay regulator - Google Patents

Abstract

FIELD: physics; control.

SUBSTANCE: present invention pertains to automatic control technology, particularly to the technology of generating control signals. The relay regulator contains, in each of (2m+1) channels, an analogue-to-digital converter, memory device, digital comparator, pulse generator, pulse counter, trigger, multiplexer, first and second majority elements, OR and XOR elements. The given parameters of duration τ_d and interval τ_i of the control signal as a function of the input signal are stored in the memory device and due to continuous comparison of real values with given values, the relay regulator does not cause delays in the control system. Due to defined connections, correct functioning of the relay regulator can be achieved when there are faults in m channels of the regulator. The proposed relay regulator can be used in different control systems, particularly in spacecraft.

EFFECT: increased efficiency.

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Description

The present invention relates to techniques for automatic control, in particular to a technique for generating control signals, and can be used, for example, in redundant control systems for spacecraft.

Known relay controller [1], containing a pulse generator, pulse counter, trigger, encoder, key.

The disadvantage of this device is that it forms only the duration (or only a pause), leaving the switching period T of the executive bodies unchanged. The use of such a relay controller in the control system leads to a delay of time T, which in turn reduces the stability region of the control system.

The closest technical solution to the relay controller is a device [2], containing an analog-to-digital converter (ADC), a storage device (memory), a digital comparator, a pulse generator connected to its output by the pulse counter input, a trigger and a multiplexer, the outputs of which connected respectively to the buses of the positive and negative control signal. This controller does not delay the control system and does not reduce the stability region.

The disadvantage of this device is that it does not have sufficient reliability. So at one failure of any element, the relay controller does not ensure the performance of its functions, and the control system loses its performance.

The objective of the invention is to increase reliability.

This task is achieved by the fact that a relay controller containing an analog-to-digital converter (ADC), a storage device (memory), a digital comparator, a pulse generator connected to its output with the pulse counter input, a trigger and a multiplexer, the outputs of which are connected respectively to to the buses of the positive and negative control signal, the ADC input is connected to the input of the relay controller, and the outputs of the ADC data register are connected to the corresponding inputs of the memory address register, the outputs of the data register of which inens with the corresponding inputs of the register of the first compared number of the digital comparator, the inputs of the register of the second compared number of which are connected to the corresponding outputs of the pulse counter, the output of the digital comparator is connected to the counting input of the trigger, 2m (m = 1, 2, ...) channels are additionally introduced, and each channel additionally contains an exclusive OR element, the first and second majority elements and an OR element whose output is connected to the R-input of the pulse counter, the first input of the OR element is connected to the output of the digital com arator, and the second input is connected to the output of the exclusive OR element, the first input of which is connected to the output of the trigger, the first input of the first majority element and the corresponding inputs of the first majority element of other channels, the second input of the exclusive OR element is connected to the output of the first majority element, the input of the highest register memory addresses and the signal input of the multiplexer, the control input of which is connected to the output of the second majority element, the first input of which is connected to the output of the sign bit and ADC data register and respective second inputs of the majority element of other channels.

In the drawing: 1 - input of the relay controller, 2 - analog-to-digital converter (ADC), 3 - storage device (memory), 4 - digital comparator, 5 - trigger, 6 - pulse counter, 7 - pulse generator, 8 - multiplexer, 9 - bus of a positive control signal, 10 - bus of a negative control signal, 11 - first majority element, 12 - OR element, 13 - exclusive OR element, 14 - second majority element, 15 - first channel, 16 - second channel, 17 - ( 2m + 1) -th (m = 1, 2, ...) channel.

The input 1 in each channel of the relay controller is connected to the input of the analog-to-digital converter 2, the outputs of the data register of which are connected to the corresponding inputs of the address register of the memory device 3, the input of the highest category of which is connected to the output of the first majority element 11, the signal input of the multiplexer 8 and the second input of the element exclusive OR 13, the first input of which is connected to the first input of the first majority element 11 and to the corresponding inputs of the first majority element 11 of other channels. The outputs of the data register of the memory 3 are connected to the corresponding inputs of the register of the first compared number of the digital comparator 4, the inputs of the register of the second number of which are connected to the corresponding outputs of the counter 6. The output of the digital comparator 4 is connected to the counting input of the trigger 5 and the first input of the element OR 12, the second input of which is connected with the output of the element exclusive OR 13, the output of the element OR 12 is connected to the R-input of the pulse counter 6, the input of which is connected to the output of the pulse generator 7. The outputs of the multiplexer 8 are connected to the buses via ozhitelnogo 9 and 10 of the negative control signal, a control input of the multiplexer 8 is connected to the second output of the majority element 14, a first input coupled to an output of the sign data register discharge ADC 1.

The relay controller operates as follows. For simplicity, we will consider a three-channel relay controller (m = 1). Let the input signals U ₁ , U ₂ , U ₃ , respectively, be applied to the inputs 1 of each channel of the relay controller. These signals are input to the ADC 1, respectively, of the first 15, second 16 and third 17 channels and are converted into an n-bit code, which is fixed in the data register of ADC 1 of the corresponding channel. In these registers, the nth bit determines the sign of the input signal, and bits 1 through (n-1) determine the value (module) A _i (i = 1, 2, 3) of the corresponding input signal U _i . If Δt is the ADC conversion time, then during this time the state of the ADC 1 data register remains unchanged. The code of the number А _i goes to the address register of memory 3, to the senior n-th digit of which the output signal of the first majority element 11 is supplied. The state of trigger 5 determines at the given moment t _k = kΔt (k = 1, 2, ...) formation duration τ _d or pause τ _{p of the} output control signal.

If F _i is the output signal of trigger 5, then F _i = 1 corresponds to the formation of the duration τ _d , F _i = 0 corresponds to the formation of a pause τ _{p of the} control signal. The signals F _i are supplied to the corresponding inputs of the first majority element 11 of all channels. The output signal F _{M of the} first majority element 11 of each channel determines the formation of a duration τ _d or pause τ _{p of the} control signal. The relationship between the output signal F _{M of the} first majority element 11 and the output signals F _{i of} trigger 5 of all channels is determined by the relation (1)

where the function M means the majority choice of the value of most (m + 1) functions F _i from the possible number of values (2m + 1). Similarly, the output signal S of the second majority element 14 is formed, which determines the sign of the input signal.

If the output signal of the first majority element 11 F _M = 1, and the signals U _i > 0, then the output signal of the second majority element 14 S = 0 and the output signal F _{+ of} multiplexer 8 is formed on the bus 9 of the positive control signal. When F _M = 1, a signal F ₊ = 1 is formed, the duration τ _{d of} which is determined by the value of the signal U _i . When F _M = 0, the signal F ₊ = 0 (a pause τ _{p of the} control signal is formed, determined by the value of the signal U _i ). If the signals U _i <0, then the signal S = 1 and the output signal F _- multiplexer 8 is formed on the bus 10 of the negative control signal similar to the formation of a positive control signal.

The output signal C _{i of the} digital comparator 4 is formed as follows. If the value of the number D ₁ recorded in the register of the first compared number of the digital comparator 4 is greater than the value of D ₂ recorded in the register of the second compared number, then the signal C _i = 0, or

if

if

The memory 3 of each channel stored array Mτ _d setpoints duration τ _d and _n array Mτ predetermined pause value τ _n. Let input 1 of each channel receive input signals that are close in value, respectively, U ₁ , U ₂ , U ₃ , and U ₁ > U ₂ > U ₃ . The task of the relay controller is to generate the output control signals F ₊ and F _- so that these signals are formed synchronously in each channel, and the values of the duration τ _d and pause τ _{p of the} output control signal are determined by the average of the three input signals in the considered case signal U ₂ . We assume that with increasing signal U _i there is an increase in the duration τ _d and a decrease in the pause τ _{p of the} control signal.

The formation of the duration τ _{d of the} control signal in each channel begins when the trigger 5 goes into a single state (F _i = 1) and the output signal F _M = 1 of the first majority element 11. When the trigger 5 goes into a single state, the signal C _i = 1 of the digital comparator 4 passing through the OR element 12, the pulse counter 6 is zeroed, as a result, conditions (2) are fulfilled and the pulse counter 6 starts to read the pulses from the generator 7. The state of the digital comparator 4 (C _i = 0) does not change until it is satisfied conditions (3), i.e. until the duration τ _d becomes equal to the specified. At this point in time, C _i = 1, and trigger 5 goes into the zero state (F _i = 0).

Let the formation of the duration τ _{d of the} control signal occur at some point in time. In this case, F _M = 1, F _i = 1, the output signals of the digital comparator 4 and the exclusive element OR 13 are equal to zero.

The output of OR gate 12 is also equal to zero, and the input of the pulse counter 6 every channel receives pulses from the generator 7. In accordance with the above assumption formed duration τ τ _D1 and pause _P1 in the first channel 15 formed duration τ τ _d2 and a pause in the second _n2 channel 16 and the generated duration τ _d3 and pause τ _p3 in the third channel 17 are connected by the relation τ _d1 > τ _d2 > τ _d3 , τ _n1 <τ _n2 <τ _n3 . Conditions (3) will be satisfied first during the formation of the duration τ _d3 , i.e. in the third channel 17. In this case, the output signal of trigger 5 of the third channel is 17 F ₃ = 0, and since, according to (1), F _M = 1, the output signal of the element exclusive OR 13 of this channel will be equal to one. A high level will be applied to the R-input of pulse counter 6, which keeps the pulse counter 6 in the zero state until the signal F _M becomes zero. This will happen at the moment when conditions (3) are satisfied during the formation of the duration τ _d2 , i.e. in the second channel 16. From this moment in time F ₂ = 0 and according to (1) F _M = 0. At the same time, the formation of the pulse duration τ _d ends and the formation of the pause τ _p begins, i.e. the duration τ _{d of the} control signal F ₊ is equal to the duration τ _d2 defined by the signal U ₂ . Note that in the first channel 15, trigger 5, due to the lack of a signal C ₁ = 1 (τ _d1 > τ _d2 ), remains in a single state (F ₁ = 1), while the output signal of the exclusive OR 13 element has a high level, which leads to zeroing of the pulse counter 5.

From the moment of the appearance of the signal F _M = 0, the formation of a pause τ _{p of the} control signal F ₊ begins and from this moment the output signal of the OR element 12 of the second channel 16 and the third channel 17 has a low level, as a result of which the pulse counters 6 of these channels begin to perceive the pulses of the generator 7 thereby forming a pause τ _{p of the} control signal F ₊ . Conditions (3) are first satisfied for the signal U ₂ . At this moment, the signal C ₂ = 1 is generated and the trigger 5 of the second channel 16 goes into a single state (F ₂ = 1). Since the signals F ₁ = 1, F ₂ = 1, according to (1) F _M = 1 and the relay controller switches to the mode of formation of the duration τ _{d of the} control signal F ₊ . Thus, the generated pause τ _{p of the} control signal F ₊ is determined by the signal U ₂ and is equal to τ _p2 . Note that from this moment, due to the absence of the signal C ₃ = 1 (τ _n2 <τ _n3 ), trigger 5 of the third channel 17 remains in the zero state (F ₃ = 0). So, in the case under consideration, during the formation of the duration τ _d and the pause τ _{p of the} control signal F _+, trigger 5 of the first channel 15 remains in the single state (F ₁ = 1), trigger 5 of the third channel 17 remains in the zero state (F ₃ = 0) , and the formation of the duration τ _d and the pause τ _{p of the} control signal F _{+ is} carried out by the signal U ₂ .

Analogously produced formation duration τ _d τ _n and the pause control signal for negative signals U _i <0. In this case, the n-th digit of the ADC 2 goes into a single state and the output signal of the second majority element 14 of each channel S = 1. The output signal of the F _- multiplexer 8 is now formed on the bus 10 of the negative control signal similarly to the above-described formation of a positive control signal.

Consider possible cases of failure in any channel of the relay controller. In this case, the relay controller is considered to be working properly if at least (m + 1) channels form the control signal synchronously and in accordance with the changing input signal U _i . In redundant systems, relay executive bodies are usually controlled by forming a generalized majorized signal according to rule (1). In this case, properly working (m + 1) channels provide deterministic control. Let, for example, trigger 5 fail in the first channel 15 and its output signal F ₁ = 1, regardless of its input signal C ₁ . In this case, when forming the duration τ _d (let F ₂ = 1, F ₃ = 1 at this moment in time), the signal C ₃ = 1 is first generated, translating trigger 5 of the third channel 17 to the zero state (F ₃ = 0), and then the signal C ₂ = 1 is formed, translating the trigger 5 of the second channel 16 to the zero state (F ₂ = 0). From this moment in time, the output signal of the first majority element 11 of all channels F _M = 0 and the formation of a pause τ _{p of the} control signal begins. Depending on the ratio of signals U ₂ and U ₃ that are close in value, either a signal C ₂ = 1 or a signal C ₃ = 1 is generated, translating either trigger 5 of the second channel 16 or trigger 5 of the third channel 17 to a single state. From this moment in time, the output signal of the first majority element 11 of all channels F _M = 1 and the formation of the duration τ _{d of the} control signal begins. Thus, the formation of the duration τ _d and the pause τ _{p of the} control signal is carried out by the input signal of a working channel.

In other types of failure in any channel, for example, when the multiplexer 8 of the first channel 15 fails (the control signal F ₊ = 1 is constantly being generated), at least two of the three channels under consideration form the control signal in accordance with the input signal of the working channels. Thus, with any failure in one channel of the relay controller in the case m = 1, the operability of the relay controller is not violated. For other values of m, the operability of the relay controller is not violated during failures in m channels from (2m + 1).

Let us evaluate the reliability of the known [2] and proposed solution. Let the reliability of one channel be equal to p. Reliability P of the proposed solution can be estimated as

P = p ^{2m + 1} + (2m + 1) p ^2m (1-p) + C ² _{2m + 1} p ^2m-1 (1-p) ² + ... + C ^m _{2m + 1} p ^{m + 1} ( 1-r) ^m

where С ² _{2m + 1} is the number of combinations from (2m + 1) by 2, С ^m _{2m + 1} is the number of combinations from (2m + 1) by m.

The reliability enhancement coefficient Q is defined as the ratio of the probability of failure q of a known solution and the probability of failure q _{1 of the} proposed solution. In this case

Let us evaluate the reliability enhancement coefficient Q for m = 1 and p = 0.9. In this case, P = p ³ + 3p ² (1-p) + 3p (1-p) ² = 0.975, q = 0.1, q ₁ = 0.025

Q = 0.1 / 0.025 = 4

The proposed set of features in the solutions considered by the authors did not occur and does not follow explicitly from the prior art, which allows us to conclude that the technical solution meets the criteria of "novelty" and "inventive step".

As an ADC, memory, digital comparator can be used chips type 1113PV1, 556RT5, 564IP2, 564KP1. The implementation of the counter, trigger, OR element is well known (for example, 564IE14, 564TM2, 564GG1).

Literature

1. RF patent No. 1798764, G05В 11/14, 1992

2. RF patent No. 2141124, G05B 11/26, 1999

Claims (1)

A relay controller containing an analog-to-digital converter (ADC), a storage device (memory), a digital comparator, a pulse generator connected to its output with a pulse counter input, a trigger and a multiplexer, the outputs of which are connected to the buses of the positive and negative control signal, respectively, the ADC input is connected to the input of the relay controller, and the outputs of the ADC data register are connected to the corresponding inputs of the memory address register, the outputs of the data register of which are connected to the corresponding inputs register of the first compared number of the digital comparator, the inputs of the register of the second compared number of which are connected to the corresponding outputs of the pulse counter, the output of the digital comparator is connected to the counting input of the trigger, characterized in that 2m (m = 1, 2, ...) channels are additionally introduced into it and each channel additionally contains an exclusive OR element, the first and second majority elements and an OR element, the output of which is connected to the R-input of the pulse counter, the first input of the OR element is connected to the output of the digital compa ora, and the second input is connected to the output of the exclusive OR element, the first input of which is connected to the output of the trigger, the first input of the first majority element and the corresponding inputs of the first majority element of other channels, the second input of the exclusive OR element is connected to the output of the first majority element, the input of the highest register memory addresses and the signal input of the multiplexer, the control input of which is connected to the output of the second majority element, the first input of which is connected to the output of the sign discharge istra ADC data and corresponding inputs of a second majority element other channels.