RU2409824C1 - Relay regulator - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: each of (2m+1) channels of relay regulator includes analogue-to-digital converter (ADC), memory unit, digital comparator, pulse generator, pulse counter, trigger, multiplexor, the first and the second majority elements, univibrator, inverter, the first, the second, the third and the fourth OR elements and the first and the second EXCLUSIVE OR elements. Specified parametres of direction τ_d and pause τ_p of control signal as function of input signal are recorded in memory unit and owing to continuous comparison of actual values to the specified ones the relay regulator does not add delay to control system, and owing to certain communications the correct operation of relay regulator is reached at failures in m channels of regulator and the specified operation is achieved, which corresponds to shaping of control signal according to the change of an average as to the value from all input signals. The proposed relay regulator can be used in various control systems, namely in control systems of space vehicles.

EFFECT: improving reliability of relay regulator.

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Description

The present invention relates to techniques for automatic control, in particular to a technique for generating control signals, and can be used, for example, in redundant control systems for spacecraft.

Known relay controller [1], containing an analog-to-digital converter (ADC), a storage device (memory), a digital comparator, a pulse generator connected by its output to the input of the pulse counter, a trigger and a multiplexer, the outputs of which are connected respectively to the buses of the positive and negative control signal. This controller does not delay the control system and does not reduce the stability region.

The disadvantage of this regulator is that it does not have sufficient reliability. So, with one failure of any element, the relay controller does not ensure the performance of its functions, and the control system loses its functionality.

The closest technical solution to the relay controller is a device [2] containing (2m + 1) (m = 1, 2, ...) a channel, and in each channel an analog-to-digital converter (ADC), a storage device (memory), and a digital comparator , a pulse generator connected by its output to the input of the pulse counter, an exclusive OR element, the first and second majority elements, an OR element, a trigger and a multiplexer, the outputs of which are connected respectively to the buses of the positive and negative control signal.

The disadvantage of this relay controller is that, with some single failures in one of the channels, it can generate a false output signal determined by the characteristics of the failed channel, and when each channel receives various signals of different magnitude, the known controller in the absence of failures does not provide operation corresponding to the formation of the control signal according to the change in the average value of all input signals.

The objective of the invention is to increase the reliability of the relay controller.

This task is achieved by the fact that in the relay controller containing (2m + 1) (m = 1, 2, ...) a channel, and in each channel an analog-to-digital converter (ADC), a storage device (memory), a digital comparator, a pulse generator connected by its output to the pulse counter input, trigger, first exclusive OR element, first and second majority elements, first OR element whose output is connected to the pulse counter R-input, the ADC input is connected to the input of the relay controller, and the outputs of the ADC data register are connected with corresponding inputs register and memory addresses, the outputs of the data register of which are connected to the corresponding inputs of the register of the first compared number of the digital comparator, the inputs of the register of the second compared number of which are connected to the corresponding outputs of the pulse counter, the first input of the first element exclusive OR connected to the output of the first majority element, are additionally introduced into each channel the second, third and fourth elements OR, the second element exclusive OR, one-shot, inverter, the first and second elements AND, the first inputs of which are connected with the trigger output, the output of the first AND element is connected to the first input of the first majority element, the second input of the first element exclusive OR and the corresponding inputs of the first majority element of other channels, the output of the second AND element connected to the first input of the second majority element, the second input of the second element exclusive OR and the corresponding inputs of the second majority element of other channels, the outputs of the first and second elements exclusive OR are connected respectively with the first and second inputs third its OR element, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the digital comparator, the output of the second OR element is connected to the input of the one-shot and the first input of the first OR, the second input of which is connected to the output of the one-shot, the trigger input is connected to the output of the first OR element, the second input of which is connected to the inverter output, the input of which is connected to the output of the sign bit of the ADC data register and the second input of the second AND element, the output of the first majority coagulant connected to the bus of a positive control signal and the first input of the fourth OR gate, the output of the second majority element connected to the bus of the negative control signal, the first input of the second element of the exclusive OR and the second input of the fourth OR gate, whose output is connected to the input older memory address register discharge.

In the drawing: 1 - input of the relay controller, 2 - analog-to-digital converter (ADC), 3 - storage device (memory), 4 - digital comparator, 5 - trigger, 6 - pulse counter, 7 - pulse generator, 8 - inverter, 9 - bus of the positive control signal, 10 - bus of the negative control signal, 11 - the first majority element, 12 - the first OR element, 13 - the first exclusive OR element, 14 - the second majority element, 15 - the one-shot, 16 - the second OR element, 17 - the third element OR, 18 - the second element exclusive OR, 19 - the fourth element OR, 20 - ne the first element And, 21 - the second element And, 22 - the first channel, 23 - the second channel, 24 - (2m + 1) -th (m = 1,2, ...) channel.

In each channel, input 1 of the relay controller is connected to the input of the ADC 2, the outputs of the data register of which are connected to the corresponding inputs of the register of the memory address 3. The outputs of the data register of memory 3 are connected to the corresponding inputs of the register of the first compared number of the digital comparator 4, the inputs of the register of the second compared number of which are connected with the corresponding outputs of the pulse counter 6, the output of the digital comparator 4 is connected to the second input of the second element OR 16, the first input of which is connected to the output of the third element OR 17. The output of the second element OR 16 is connected to the input of the single-vibrator 15 and the first input of the first element OR 12, the second input of which is connected to the output of the single-vibrator 15. The output of the first element OR 12 is connected to the counting input of the trigger 5 and to the R-input of the pulse counter 6, the input of which is connected with the output of the pulse generator 7. The first inputs of the first 20 and second 21 AND elements are connected to the trigger output 5, the output of the first And 20 element is connected to the first input of the first majority element 11, the exclusive OR 13 is the second input of the first element, and corresponding E inputs of a majority of the first element 11 of the other channels, the output of the second AND gate 21 is connected to a first input of a second majority element 14, the second input of the second exclusive OR element 18 and the respective inputs of a second majority element 14 of the other channels. The output of the first majority element 11 is connected to the bus of the positive control signal 9, the first input of the first element exclusive OR 13 and the first input of the fourth element OR 19, the output of the second majority element 14 is connected to the bus of the negative control signal 10, with the first input of the second element exclusive OR 18 and the second input of the fourth element OR 19. The outputs of the first 13 and second 18 elements exclusive OR are connected respectively to the first and second inputs of the third element OR 17, the second input of the first element AND 20 with union of the inverter 8 to output, whose input is connected to the output of ADC older data register 2 and the second discharge input of the second AND gate 21. The output of the fourth OR gate 19 is connected to the input of MSB ZU3 address register.

The relay controller operates as follows. For simplicity, we will consider a three-channel relay controller (m = 1). Let the input signals U ₁ , U ₂ , U ₃ , respectively, be applied to the inputs 1 of each channel of the relay controller. These signals are fed to the input of the ADC 2 of the first 22, second 23, and third 24 channels, respectively, and are converted into an n-bit code, which is fixed in the ADC 2 data register of the corresponding channel. In these registers, the nth bit determines the sign of the input signal, and bits 1 through (n-1) determine the value (module) A _i (i = 1, 2, 3) of the corresponding input signal U _i . If Δt is the ADC conversion time, then during this time the state of the ADC 2 data register remains unchanged. The code of the number A _i goes to the memory register of the memory 3, to the senior n-th bit of which the output signal of the fourth element OR 19 is supplied. The state of the fourth element OR 19 determines at the given moment t _k = kΔt (k = 1, 2, ...) formation duration τ _d or pause τ _{p of the} output control signal.

We assume that if the input signal is U ₁ > 0, then the sign bit of the ADC 2 data register is in the zero state and its output signal is S _i = 0. If the input signal is U ₁ <0, then the sign bit of the ADC 2 data register is in a single state and its output signal is S _i = 1. If F _i is the output signal of trigger 5, then the output signals F _i ^{+ of the} first element And 20 and F _i ^{- of the} second element And 21 will be determined by the equalities

F _i ⁺ = 0 if F _i = 0 or F _i = 1 and S _i = 1,

F _i ⁺ = 1, if F _i = 1 and S _i = 0,

F _i ^- = 0 if F _i = 0 or F _i = 1 and S _i = 0,

F _i ^- = 1 if F ₁ = 1 and S _i = 1.

These equalities directly follow from the analysis of the circuit in the drawing. When S _i = 0, the first element And 20 is open (the output signal of the first inverter 8 is equal to one), when S _i = 1, the second element And 21 is open.

The relationship between the output signal F _{+ of the} first majority element 11 and the output signals F _i ^{+ of the} first element And 20 and between the output signal F _{- of the} second majority element 14 and the output signals F _i ^{- of the} second element And 21 of all channels is determined by the relation (1)

where the function M means the majority choice of the value of most (m + 1) functions F _i from the possible number of values (2m + 1).

If F ₊ = 1 or F _- = 1, then the output signal F _{M of the} fourth element OR 19 is equal to unity, which corresponds to the formation of the duration τ _d . If F ₊ = 0 and F _- = 0, then the output signal F _{M of the} fourth element OR 19 is zero, which corresponds to the formation of a pause τ _p .

If the output signal of the first majority element 11 F ₊ = 1, then the output signal F ₊ is generated on the bus 9 of the positive control signal. If the output signal of the second majority element 14 F _- = 1, then the output signal F _{- is} formed on the bus 10 of the negative control signal.

The output signal C _{i of the} digital comparator 4 is formed as follows. If the value of the number D ₁ recorded in the register of the first compared number of the digital comparator 4 is greater than the value D ₂ recorded in the register of the second compared number, then the signal C _i = 1, or

The memory 3 of each channel stored array Mτ _d setpoints duration τ _d and _n array Mτ predetermined pause value τ _n. Let input 1 of each channel receive input signals that are close in value, respectively, U ₁ , U ₂ , U ₃ , and U ₁ > U ₂ > U ₃ . The task of the relay controller is to generate the output control signals F ₊ and F _- so that these signals are formed synchronously in each channel, and the values of the duration τ _d and pause τ _{p of the} output control signal are determined by the average of the three input signals in the considered case signal U ₂ . We assume that with increasing signal U _i there is an increase in the duration τ _d and a decrease in the pause τ _{p of the} control signal.

Let the formation of the duration τ _{d of the} control signal occur at some point in time. In this case, F ₊ = 1, F _M = 1, F _i = 1, the output signals of the digital comparator 4, the first 13 and second 18 elements exclusive OR are equal to zero. The output signal of the first element OR 12 is also equal to zero and pulses from the generator 7 are received at the input of the pulse counter 6 of each channel 7. In accordance with the assumption made, the duration τ _d1 and pause τ _p1 in the first channel 22, the duration τ _d2 and pause τ _p2 are formed the second channel 23 and the generated duration τ _d3 and the pause τ _p3 in the third channel 24 are connected by the relation τ _d1 > τ _d2 > τ _d3 , τ _n1 <τ _n2 <τ _n3 . Conditions (3) will be satisfied first during the formation of the duration τ _d3 , i.e. in the third channel 24. In this case, the output signal C _i = 1 of the digital comparator 4, passing through the second element OR 16, the one-shot 15 and the first element OR 12, sets the trigger 5 of the third channel 24 to zero and produces a zero counter pulse 6. Output the trigger signal 5 of the third channel is 24 F ₃ = 0, and since according to (1) F ₊ = 1, the output signal of the first element exclusive OR 13 of this channel will be equal to one.

A high level will be applied to the R-input of pulse counter 6 through the third 17, second 16, and first 12 elements, which will keep the pulse counter 6 in the zero state until the signal F ₊ becomes zero. This will happen at the moment when conditions (3) are satisfied during the formation of the duration τ _d2 , i.e. in the second channel 23. From this moment in time F ₂ = 0 and according to (1) F ₊ = 0. At the same time, the output signal of the first majority element 11 of the first channel 22 F ₊ = 0, the output signal of the trigger 5 of this channel F ₁ = 1 and the output signal of the first element And 20 F _i ⁺ = 1. As a result, at the output of the first element exclusive OR 13, a high level is formed, which through the third 17, second 16 and first 12 elements OR is fed to the input of trigger 5, setting it to zero. Thus, at the time of formation of the signals F ₊ = 0, the triggers 5 go to the zero state in all channels and the signals F _M = 0. At the same time, the formation of the pulse duration τ _d ends and the formation of the pause τ _p begins, i.e. the duration τ _{d of the} control signal F ₊ is equal to the duration τ _d2 defined by the signal U ₂ .

From the moment the signal F _M = 0 appears, the formation of a pause τ _{p of the} control signal F ₊ begins and from this moment the output signal of the first element OR 12 of all channels has a low level, as a result of which the pulse counters 6 of these channels begin to perceive the pulses of the generator 7, thereby forming a pause τ _p control signal F ₊ . Conditions (3) are first satisfied for the signal U ₁ . At this moment, a signal C ₁ = 1 is generated and trigger 5 of the first channel 22 goes into a single state (F ₁ = 1) according to the algorithm described above. Since F ₁ = 1, F ₊ = 0, the output signal of the first element exclusive OR 13 of this channel will be equal to one. A high level will be applied to the R-input of pulse counter 6, which keeps the pulse counter 6 in a zero state until the signal F ₊ becomes equal to one. Conditions (3) are second satisfied for the signal U ₂ . At this moment, the signal C ₂ = 1 is generated and the trigger 5 of the second channel 23 goes into a single state (F ₂ = 1). Since the signals F ₁ = 1, F ₂ = 1, according to (1) F ₊ = 1 and the relay controller goes into the mode of forming the duration τ _{d of the} control signal F ₊ . At the time of formation of the signal F _M = 1 at the output of the first element exclusive OR 13 of the third channel 24, a high level is formed, which through the third 17, second 16 and first 12 elements OR is fed to the input of trigger 5, setting it to a single state. Thus, the generated pause τ _{p of the} control signal F ₊ is determined by the signal U ₂ and is equal to τ _p2 . So, in the case under consideration, the formation of the duration τ _d and the pause τ _{p of the} control signal F _{+ is} carried out by the signal U ₂ and is performed simultaneously in all channels.

Similarly, the formation of the duration τ _d and pause τ _{p of the} control signal is produced for negative signals U _i <0. In this case, the n-th digit of the ADC 2 goes into a single state and blocks the formation of the signal F ₊ . The output signal F _{- of the} second majority element 14 is now formed on the bus 10 of the negative control signal similar to the above-described formation of a positive control signal.

Note that at the moment of the beginning of the formation of the duration τ _d or pause τ _{p of the} control signal, the triggers 5 of all channels are set to the required state.

Consider possible cases of failure in any channel of the relay controller. In this case, the relay controller is considered to be working properly if at least the (m + 1) channel generates a control signal synchronously and in accordance with the changing input signal U _i . In redundant systems, relay executive bodies are usually controlled by forming a generalized majorized signal according to rule (1). In this case, properly working (m + 1) channels provide deterministic control. Let, for example, trigger 5 fail in the first channel 22 and its output signal F ₁ = 1, regardless of its input signal C ₁ . In this case, when forming the duration τ _d (let F ₂ = 1, F ₃ = 1 at this moment in time), the signal C ₃ = 1 is first generated, translating trigger 5 of the third channel 24 to the zero state (F ₃ = 0), and then the signal C ₂ = 1 is formed, translating the trigger 5 of the second channel 23 to the zero state (F ₂ = 0). From this moment in time, the output signal of the second majority element 14 of all channels F _- = 0 and the formation of a pause τ _{p of the} control signal begins. Depending on the ratio of signals U ₂ and U ₃ that are close in value, either a signal C ₂ = 1 or a signal C ₃ = 1 is generated, translating either trigger 5 of the second channel 23 or trigger 5 of the third channel 24 to a single state. From this moment in time, the output signal of the second majority element 14 of all channels F _- = 1 and the formation of the duration τ _{d of the} control signal begins. Thus, the formation of the duration τ _d and pause τ _{p of the} control signal is carried out by the input signal of a working channel.

In other types of failure in any channel, for example, in the event of a failure of the first majority element 11 of the first channel 22 (a control signal F ₊ = 1 is constantly being generated), at least two of the three channels under consideration form a control signal in accordance with the input signal of the working channels . Thus, with any failure in one channel of the relay controller in the case m = 1, the operability of the relay controller is not violated. For other values of m, the operability of the relay controller is not violated during failures in m channels from (2m + 1).

Let us consider a failure of this type when in one of the failed channels the formation of the control signal F ₊ and F _- occurs according to a law that differs significantly from the given one (for example, due to a significant increase in the frequency of the generator 7 of one of the channels). In this case, the generated durations τ _d and pauses τ _{p of the} control signal of the failed channel will be significantly less than the set ones. In the proposed controller, the formation of the duration τ _d or pause τ _p always starts from the moment the triggers 5 of all channels are set to a given state. And this means that the formation of the duration τ _d and the pause τ _{p is} made by triggering two channels out of three, i.e. to trigger a working channel.

In the known [2] controller, the formation of a duration of τ _d or a pause of τ _p starts from the moment the triggers 5 of two channels of three are set to a predetermined state, which means that in the case of the considered failure option, the formation of a duration of τ _d and a pause of τ _{p is} made according to the signals of the faulty channel.

Note that the well-known controller [2] with the most common failures of the type "open" or "circuit" provides the specified operation of the controller.

Thus, the proposed controller ensures proper functioning with all possible types of failure in any of the channels.

Let us now consider the operation of the relay controller in the case of the arrival at its inputs of signals significantly different in level U _i . Let U ₁ > U ₂ > 0, U ₃ <0. In this case, the average is the signal U ₂ . In the case under consideration, signals F ₁ ⁺ = 1, F ₂ ⁺ = 1, F ₃ ^- = 1 will be generated, which means that the signal F _{- is} always zero, and the signal F ₊ is generated by the signals F ₁ ⁺ and F ₂ ⁺ , the duration τ _{d of the} output control signal F ₊ is determined by a signal that is lower in level, i.e. signal U ₂ .

Thus, the considered relay controller generates a control signal, the law of change of which is determined by the "average" of the set of input signals U _i , which increases the functional reliability of the relay controller.

In the known controller, if, for example, the signals U ₁ and U ₃ are close in value, then the output control signal will be determined by one of these signals, each of which is not the "average" of the set of input signals U _i .

Let us evaluate the reliability of the known [2] and proposed solution. Let the reliability of one channel be p, and the reliability of the pulse generator 7 included in the channel is p ₁ , and the reliability of the rest of the circuit of this channel is p ₂ , with p = p ₁ p ₂ . The reliability P _{p of the} proposed solution can be estimated in the form

where C ² _{2m + 1} is the number of combinations from (2m + 1) by 2, C ^m _{2m + 1} is the number of combinations from (2m + 1) by m.

The reliability of P _{and the} known solution, taking into account the possible malfunction of the pulse generator, can be estimated in the form

Let m = 1, p ₁ = 0.99, p ₂ = 0.9. In this case, from (4) and (5), respectively, we have P _n = 0.967, P _AND = 0.943. Thus, the reliability of the proposed controller R _p higher than the reliability of the known controller R _And .

The proposed set of features in the solutions considered by the authors did not occur and does not follow explicitly from the prior art, which allows us to conclude that the technical solution meets the criteria of "novelty" and "inventive step".

As an ADC, memory, digital comparator can be used chips type 1113PV1, 556RT5, 564IP2, 564KP1. The implementation of the counter, trigger, AND, OR, exclusive OR elements is well known (for example, 564IE14, 564TM2, 564GG1).

Literature

1. RF patent No. 2141124, G05B 11/26, 1999

2. RF patent No. 2342690, G05В 11/26, 2008

Claims (1)

A relay controller containing (2m + 1) (m = 1, 2, ...) a channel, and in each channel an analog-to-digital converter (ADC), a storage device (memory), a digital comparator, a pulse generator connected by its output to the counter input pulses, trigger, the first element exclusive OR, the first and second majority elements, the first OR element, the output of which is connected to the R-input of the pulse counter, the ADC input is connected to the input of the relay controller, and the outputs of the ADC data register are connected to the corresponding inputs of the memory address register, data register outputs of which are connected to the corresponding inputs of the register of the first compared number of the digital comparator, the inputs of the register of the second compared number of which are connected to the corresponding outputs of the pulse counter, the first input of the first element exclusive OR connected to the output of the first majority element, characterized in that a second is additionally introduced into each channel, the third and fourth elements OR, the second element exclusive OR, one-shot, inverter, the first and second elements AND, the first inputs of which are connected to the output m of the trigger, the output of the first AND element is connected to the first input of the first majority element, the second input of the first element exclusive OR and the corresponding inputs of the first majority element of other channels, the output of the second AND element connected to the first input of the second majority element, the second input of the second element exclusive OR the inputs of the second majority element of other channels, the outputs of the first and second elements exclusive OR are connected respectively to the first and second inputs of the third element OR, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the digital comparator, the output of the second OR element is connected to the input of the one-shot and the first input of the first OR, the second input of which is connected to the output of the one-shot, the trigger input is connected to the output the first OR element, the second input of which is connected to the output of the inverter, the input of which is connected to the output of the digit of the ADC data register and the second input of the second AND element, the output of the first majority element is connected n with the positive bus control signal and the first input of the fourth OR gate, the output of a majority of the second element is connected to the bus of the negative control signal to a first input of the second exclusive OR element and the second input of the fourth OR gate, whose output is connected to the input memory address register older discharge.