RU2408914C1 - Relay control - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: relay control has in each of (2m+1) channels of an analogue-to-digital converter (ADC) a memory device, a digital comparator, a pulse generator, a pulse counter, a flip flop, a multiplexer, first and second majority decision elements, first and second univibrators, first and second inverters, first, second and third OR elements and first and second XOR elements. Given duration τ_d and pause τ_p parametres of the control signal as a function of the input signal are recorded in the memory device and owing to continuous comparison of actual values with given values, the relay control does not cause delays in the control system and non-faulty operation of the relay during faults in m channels of the control and given operation, corresponding to generation of a control signal in accordance with variation of the average-value from all input signals, is ensured owing to certain connections. The disclosed relay control can be used in various control systems, particularly in spacecraft control systems.

EFFECT: high reliability.

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Description

The present invention relates to techniques for automatic control, in particular to a technique for generating control signals, and can be used, for example, in redundant control systems for spacecraft.

Known relay controller [1], containing an analog-to-digital converter (ADC), a storage device (memory), a digital comparator, a pulse generator connected to its output with the input of the pulse counter, a trigger and a multiplexer, the outputs of which are connected respectively to the buses of the positive and negative control signals. This controller does not delay the control system and does not reduce the stability region.

The disadvantage of this regulator is that it does not have sufficient reliability. So at one failure of any element, the relay controller does not ensure the performance of its functions, and the control system loses its performance.

The closest technical solution to the relay controller is a device [2] containing (2m + 1) (m = 1, 2, ...) a channel, and in each channel an analog-to-digital converter (ADC), a storage device (memory), and a digital comparator , a pulse generator connected by its output to the input of the pulse counter, an exclusive OR element, the first and second majority elements, an OR element, a trigger and a multiplexer, the outputs of which are connected respectively to the buses of the positive and negative control signals.

The disadvantage of this relay controller is that, with some single failures in one of the channels, it can generate a false output signal determined by the characteristics of the failed channel, and when each channel receives various signals of different magnitude, the known controller in the absence of failures does not provide operation corresponding to the formation of the control signal according to the change in the average value of all input signals.

The objective of the invention is to increase the reliability of the relay controller.

This task is achieved by the fact that in the relay controller containing (2m + 1) (m = 1, 2, ...) a channel, and in each channel an analog-to-digital converter (ADC), a storage device (memory), a digital comparator, a pulse generator connected by its output to the pulse counter input, trigger, first exclusive OR element, first and second majority elements, first OR element whose output is connected to the pulse counter R-input, the ADC input is connected to the input of the relay controller, and the outputs of the ADC data register are connected with corresponding inputs register and memory addresses, the outputs of the data register of which are connected to the corresponding inputs of the register of the first compared number of the digital comparator, the inputs of the register of the second compared number of which are connected to the corresponding outputs of the pulse counter, the output of the digital comparator is connected to the counting input of the trigger and the first input of the first OR element, the first input of the first the exclusive OR element is connected to the output of the first majority element, the second and third OR elements are additionally introduced into each channel, the second element excludes flashing OR, first and second one-shots, first and second inverters, first and second AND elements, the first inputs of which are connected to the trigger output, the output of the first AND element is connected to the first input of the first majority element, the second input of the first element is exclusive OR and the corresponding inputs of the first majority element of other channels, the output of the second element And is connected to the first input of the second majority element, the second input of the second element exclusive OR and the corresponding inputs of the second majority element of other channels, the outputs of the first and second exclusive OR elements are connected respectively to the first and second inputs of the third OR element, the output of which is connected to the second input of the first OR element, the second input of the first AND element is connected to the output of the first inverter, the input of which is connected to the output of the register bit ADC data and the second input of the second AND element, the output of the first majority element is connected to the bus of the positive control signal and the first input of the second OR element, the output of the second majority ment is connected to the bus of the negative control signal, with the first input of the second element exclusive OR and the second input of the second element OR, the output of which is connected to the input of the upper order of the memory address register, the input of the second inverter and the input of the first one-shot, the output of which is connected to the S-input of the trigger, The R-input of which is connected to the output of the second one-shot, connected by its input to the output of the second inverter.

In the drawing: 1 - input of the relay controller, 2 - analog-to-digital converter (ADC), 3 - storage device (memory), 4 - digital comparator, 5 - trigger, 6 - pulse counter, 7 - pulse generator, 8 - first inverter , 9 - bus of the positive control signal, 10 - bus of the negative control signal, 11 - the first majority element, 12 - the first OR element, 13 - the first exclusive OR element, 14 - the second majority element, 15 - the first one-shot, 16 - the second inverter, 17 - the second one-shot, 18 - the second element exclusive OR, 19 - the second element OR, 20 - the third element OR, 21 - the first element AND, 22 - the second element And, 23 - the first channel, 24 - the second channel, 25 - (2m + 1) -th (m = 1,2, ...) channel.

In each channel, the input 1 of the relay controller is connected to the input of the ADC 2, the outputs of the data register of which are connected to the corresponding inputs of the register of the memory address 3. The outputs of the data register of the memory 3 are connected to the corresponding inputs of the register of the first compared number of the digital comparator 4, the inputs of the register of the second compared number of which are connected with the corresponding outputs of the pulse counter 6, the output of the digital comparator 4 is connected to the counting input of the trigger 5 and the first input of the first element OR 12, the second input of which is connected to the output to the third element OR 20. The output of the first element OR 12 is connected to the R-input of the pulse counter 6, the input of which is connected to the output of the pulse generator 7. The first inputs of the first 21 and second 22 elements AND are connected to the output of the trigger 5, the output of the first element And 21 is connected with the first input of the first majority element 11, the second input of the first element exclusive OR 13 and the corresponding inputs of the first majority element 11 of other channels, the output of the second element And 22 is connected to the first input of the second majority element 14, the second input the second element exclusive OR 18 and the corresponding inputs of the second majority element 14 of other channels. The output of the first majority element 11 is connected to the bus of the positive control signal 9, the first input of the first element exclusive OR 13 and the first input of the second element OR 19, the output of the second majority element 14 is connected to the bus of the negative control signal 10, with the first input of the second element exclusive OR 18 and the second input of the second element OR 19. The outputs of the first 13 and second 18 elements exclusive OR are connected respectively to the first and second inputs of the third element OR 20, the second input of the first element And 21 is connected with the output of the first inverter 8, the input of which is connected to the output of the high-order bit of the ADC data register 2 and the second input of the second element 22. The output of the second element OR 19 is connected to the input of the high-order bit of the memory address 3, the input of the second inverter 16 and the input of the first one-shot 15, the output of which is connected to the S-input of trigger 5, the R-input of which is connected to the output of the second one-shot 15, connected by its input to the output of the second inverter 16.

The relay controller operates as follows. For simplicity, we will consider a three-channel relay controller (m = 1). Let the input signals U ₁ , U ₂ , U ₃ , respectively, be applied to the inputs 1 of each channel of the relay controller. These signals are fed to the input of ADC 2, respectively, of the first 23, second 24, and third 25 channels and are converted into an n-bit code, which is fixed in the data register of ADC 2 of the corresponding channel. In these registers, the nth bit determines the sign of the input signal, and bits 1 through (n-1) determine the value (module) A _i (i = 1, 2, 3) of the corresponding input signal U _i . If Δt is the ADC conversion time, then during this time the state of the ADC 2 data register remains unchanged. The code of the number А _i goes to the memory register of the memory 3, to the senior n-th bit of which the output signal of the second OR element 19 is supplied. The state of the second OR element determines at the given moment t _k = kΔt (k = 1, 2, ...) the formation of the duration τ _D or pause τ _{P of the} output control signal.

We assume that if the input signal is U ₁ > 0, then the sign bit of the ADC 2 data register is in the zero state and its output signal is S _i = 0. If the input signal is U ₁ <0, then the sign bit of the ADC 2 data register is in a single state and its output signal is S _i = 1. If F _i is the output signal of trigger 5, then the output signals F _i ^{+ of the} first element And 21 and F _i ^{- of the} second element And 22 will be determined by the equalities

F _i ⁺ = 0 if F _i = 0 or F _i = 1 and S _i = 1,

F _i ⁺ = 1, if F _i = 1 and S _i = 0,

F _i ^- = 0 if F _i = 0 or F _i = 1 and S _i = 0,

F _i ^- = 1 if F _i = 1 and S _i = 1,

These equalities directly follow from the analysis of the drawing scheme. When S _i = 0, the first element And 21 is open (the output signal of the first inverter 8 is equal to one), when S _i = 1, the second element And 22 is open.

The relationship between the output signal F _{+ of the} first majority element 11 and the output signals F _i ^{+ of the} first element And 21 and between the output signal F_ of the second majority element 14 and the output signals F _i ^{- of the} second element And 22 of all channels is determined by the relation (1)

where the function M means the majority choice of the value of most (m + 1) functions F _i from the possible number of values (2m + 1).

If F ₊ = 1 or F _- = 1, then the output signal F _{M of the} second element OR 19 is equal to one, which corresponds to the formation of the duration τ _D. If F ₊ = 0 and F _- = 0, then the output signal F _{M of the} second element OR 19 is zero, which corresponds to the formation of a pause τ _P.

If the output signal of the first majority element 11 F ₊ = 1, then the output signal F ₊ is generated on the bus 9 of the positive control signal. If the output signal of the second majority element 14 F _- = 1, then the output signal F _{- is} formed on the bus 10 of the negative control signal.

The output signal C _{i of the} digital comparator 4 is formed as follows. If the value of the number D ₁ recorded in the register of the first compared number of the digital comparator 4 is greater than the value D ₂ recorded in the register of the second compared number, then the signal C _i = 1, or

In the storage device 3 of each channel, an array of Mτ _D preset values of duration τ _D and an array of Mτ _P preset pause values of τ _{P are} stored. Let input 1 of each channel receive input signals that are close in value, respectively, U ₁ , U ₂ , U ₃ , and U ₁ > U ₂ > U ₃ . The task of the relay controller is to generate the output control signals F ₊ and F _- so that these signals are formed synchronously in each channel, and the values of the duration τ _D and pause τ _{P of the} output control signal are determined by the average of the three input signals in the considered case signal U ₂ . We assume that with increasing signal U _i there is an increase in the duration τ _D and a decrease in the pause τ _{P of the} control signal.

The formation of the duration τ _{D of the} control signal in each channel begins when the trigger 5 goes into a single state (F _i = 1) and the output signal F _M = 1 of the second element And 19. When the trigger 5 goes into a single state, the output signal C _i = 1 of the digital comparator 4, passing through the first element OR 12, the pulse counter 6 is zeroed, as a result, conditions (2) are fulfilled and the pulse counter 6 starts to read pulses from the generator 7. The state of the digital comparator 4 (C _i = 0) does not change until conditions (3) are not satisfied, i.e. until the duration τ _D becomes equal to the specified. At this point in time, C _i = 1, and trigger 5 goes into the zero state (F _i = 0).

Let the formation of the duration τ _{D of the} control signal occur at some point in time. In this case, F ₊ = 1, F _M = 1, F _i = 1, the output signals of the digital comparator 4 and the first 13 and second 18 elements exclusive OR are zero. The output signal of the first element OR 12 is also equal to zero, and pulses from the generator 7 are received at the input of the pulse counter 6 of each channel. In accordance with the assumption made, the duration τ _D1 and the pause τ _P1 in the first channel 23, the formed duration τ _D2 and the pause τ _P2 in the second channel 24 and the formed duration τ _D3 and the pause τ _P3 in the third channel 25 are connected by the relation τ _D1 > τ _D2 > τ _D3 , τ _P1 <τ _P2 <τ _P3 . Conditions (3) will be the first to be fulfilled during the formation of duration τ _D3 , i.e. in the third channel 25. In this case, the output signal of the trigger 5 of the third channel 25 F ₃ = 0, and since according to (1) F ₊ = 1, the output signal of the first element exclusive OR 13 of this channel will be equal to one. A high level will be applied to the R-input of pulse counter 6, which keeps the pulse counter 6 in a zero state until the F ₊ signal becomes zero. This will happen at the moment when conditions (3) are satisfied when the duration τ _{D2 is formed} , i.e. in the second channel 24. From this moment in time F ₂ = 0 and according to (1) F ₊ = 0. At this point in time, the output signal of the second inverter 16 of all channels is at a high level and a pulse is generated at the output of the second one-shot 17, which is fed to input R of trigger 5, setting it to zero in all channels. At the same time, the formation of the pulse duration τ _D ends and the formation of the pause τ _P begins, i.e. the duration τ _{D of the} control signal F ₊ is equal to the duration τ _D2 determined by the signal U2.

From the moment of the appearance of the signal F _М = 0, the formation of a pause τ _{P of the} control signal F ₊ begins, and from this moment the output signal of the first element OR 12 of all channels has a low level, as a result of which the pulse counters 6 of these channels begin to receive the pulses of the generator 7, thereby pause τ _P control signal F ₊ . Conditions (3) are first satisfied for the signal U ₁ . At this moment, a signal C ₁ = 1 is generated and trigger 5 of the first channel 23 goes into a single state (F ₁ = 1). Since F ₁ = 1, F ₊ = 0, the output signal of the first element exclusive OR 13 of this channel will be equal to one. A high level will be applied to the R-input of pulse counter 6, which keeps the pulse counter 6 in a zero state until the signal F ₊ becomes equal to one. Conditions (3) are second satisfied for the signal U ₂ . At this moment, the signal C ₂ = 1 is generated and the trigger 5 of the second channel 24 goes into a single state (F ₂ = 1). Since the signals F ₁ = 1, F ₂ = 1, according to (1) F ₊ = 1 and the relay controller switches to the mode of formation of the duration τ _{D of the} control signal F ₊ . At the time of formation of the signal F _M = 1, the input signal of the first one-shot 15 of all channels has a high level and a pulse is generated at the output of this one-shot, which is fed to input S of trigger 5, setting them to a single state in all channels. Thus, the generated pause τ _{P of the} control signal F ₊ is determined by the signal U ₂ and is equal to τ _P2 . So, in the case under consideration, the formation of the duration τ _D and the pause τ _{P of the} control signal F _{+ is} carried out by the signal U ₂ .

Similarly, the formation of the duration τ _D and the pause τ _{P of the} control signal is produced for negative signals U _i <0. In this case, the n-th digit of the ADC 2 goes into a single state and blocks the formation of the signal F ₊ . The output signal F _{- of the} second majority element 14 is now formed on the bus 10 of the negative control signal similar to the above-described formation of a positive control signal.

Note that at the beginning of the formation of the duration τ _D or pause τ _{P of the} control signal, the triggers 5 of all channels are set to the required state.

Consider possible cases of failure in any channel of the relay controller. In this case, the relay controller is considered to be working properly if at least (m + 1) channels form the control signal synchronously and in accordance with the changing input signal U _i . In redundant systems, relay executive bodies are usually controlled by forming a generalized majorized signal according to rule (1). In this case, properly working (m + 1) channels provide deterministic control. Let, for example, trigger 5 fail in the first channel 23, and its output signal F ₁ = 1, regardless of its input signal C ₁ . In this case, during the formation of the duration τ _D (let F ₂ = 1, F ₃ = 1 at this moment in time), the signal C ₃ = 1 is first generated, translating trigger 5 of the third channel 25 to the zero state (F ₃ = 0), and then the signal C ₂ = 1 is formed, translating the trigger 5 of the second channel 24 to the zero state (F ₂ = 0). From this moment in time, the output signal of the second majority element 14 of all channels F _- = 0 and the formation of a pause τ _{P of the} control signal begins. Depending on the ratio of signals U ₂ and U ₃ that are close in value, either a signal C ₂ = 1 or a signal C ₃ = 1 is generated, translating either trigger 5 of the second channel 24 or trigger 5 of the third channel 25 to a single state. From this moment in time, the output signal of the second majority element 14 of all channels F _- = 1 and the formation of the duration τ _{D of the} control signal begins. Thus, the formation of the duration τ _D and pause τ _{P of the} control signal is carried out by the input signal of a working channel.

In other types of failure in any channel, for example, in the event of a failure of the first majority element 11 of the first channel 23 (a control signal F ₊ = 1 is constantly being generated), at least two of the three channels under consideration generate a control signal in accordance with the input signal of working channels. Thus, with any failure in one channel of the relay controller in the case m = 1, the operability of the relay controller is not violated. For other values of m, the operability of the relay controller is not violated during failures in m channels from (2m + 1).

Let us consider a failure of this type when in one of the failed channels the formation of the control signal F ₊ and F _- occurs according to a law that differs significantly from the given one (for example, due to a significant increase in the frequency of the generator 7 of one of the channels). In this case, the generated durations τ _D and pauses τ _{P of the} control signal of the failed channel will be significantly less than the specified ones. In the proposed controller, the formation of a duration τ _D or a pause τ _P always starts from the moment the triggers 5 of all channels are set to a predetermined state. This means that the formation of a duration of τ _D and a pause of τ _{P is} made by triggering two channels out of three, i.e. to trigger a working channel.

In the well-known [2] controller, the formation of the duration τ _D or pause τ _P starts from the moment the triggers 5 of two channels of three are set to a predetermined state, which means that in the case of the considered failure option, the formation of the duration τ _D and pause τ _{P is} produced by the signals channel.

Note that the well-known controller [2] with the most common failures of the type "open" or "circuit" provides the specified operation of the controller.

Thus, the proposed controller ensures proper functioning with all possible types of failure in any of the channels.

Let us now consider the operation of the relay controller in the case of the arrival at its inputs of signals significantly different in level U _i . Let U ₁ > U ₂ > 0, U ₃ <0. In this case, the average is the signal U ₂ . In the case under consideration, signals F ₁ ⁺ = 1, F ₂ ⁺ = 1, F ₃ ^- = 1 will be generated, which means that the signal F _{- is} always zero, and the signal F ₊ is generated by the signals F ₁ ⁺ and F ₂ ⁺ , the duration τ _{D of the} output control signal F ₊ is determined by a signal that is lower in level, i.e. signal U ₂ .

Thus, the considered relay controller generates a control signal, the law of change of which is determined by the "average" of the set of input signals U _i , which increases the functional reliability of the relay controller.

In the known controller, if, for example, the signals U ₁ and U ₃ are close in value, then the output control signal will be determined by one of these signals, each of which is not the "average" of the set of input signals U _i .

Let us evaluate the reliability of the known [2] and proposed solution. Let the reliability of one channel be equal to p, and the reliability of the pulse generator 7, which is part of the channel, equal to p ₁ , and the reliability of the rest of the circuit of this channel is equal to p ₂ , with p = p ₁ · p ₂ . Reliability R _{P of the} proposed solution can be estimated in the form

where С ² _{2m + 1} is the number of combinations from (2m + 1) by 2, С ^m _{2m + 1} is the number of combinations from (2m + 1) by m.

Reliability P _{And the} known solution, taking into account the possible malfunction of the pulse generator, can be estimated in the form

Let m = 1, p ₁ = 0.99, p ₂ = 0.9. In this case, from (4) and (5), respectively, we have P _P = 0.967, P _AND = 0.943. Thus, the reliability of the proposed controller R _P higher than the reliability of the known controller R _And .

The proposed set of features in the solutions considered by the authors did not occur and does not follow explicitly from the prior art, which allows us to conclude that the technical solution meets the criteria of "novelty" and "inventive step".

As an ADC, memory, digital comparator can be used chips type 1113PV1, 556RT5, 564IP2, 564KP1. The implementation of the counter, trigger, AND, OR, exclusive OR elements is well known (for example, 564IE14, 564TM2, 564GG1).

Literature

1. RF patent No. 2141124, G05B 11/26, 1999

2. RF patent No. 2342690, G05B 11/26, 2008

Claims (1)

A relay controller containing (2m + 1) (m = 1, 2, ...) a channel, and in each channel an analog-to-digital converter (ADC), a storage device (memory), a digital comparator, a pulse generator connected by its output to the counter input pulses, trigger, the first element exclusive OR, the first and second majority elements, the first OR element, the output of which is connected to the R-input of the pulse counter, the ADC input is connected to the input of the relay controller, and the outputs of the ADC data register are connected to the corresponding inputs of the memory address register, data register outputs of which are connected to the corresponding inputs of the register of the first compared number of the digital comparator, the inputs of the register of the second compared number of which are connected to the corresponding outputs of the pulse counter, the output of the digital comparator is connected to the counting input of the trigger and the first input of the first OR element, the first input of the first exclusive OR element is connected to the output the first majority element, characterized in that the second and third OR elements are additionally introduced into each channel, the second element excluding OR , the first and second one-shots, the first and second inverters, the first and second elements AND, the first inputs of which are connected to the output of the trigger, the output of the first element And is connected to the first input of the first majority element, the second input of the first element exclusive OR and the corresponding inputs of the first majority element of others channels, the output of the second element AND is connected to the first input of the second majority element, the second input of the second element exclusive OR and the corresponding inputs of the second majority element of other channels Generally, the outputs of the first and second exclusive-OR elements are connected respectively to the first and second inputs of the third OR element, the output of which is connected to the second input of the first OR element, the second input of the first AND element is connected to the output of the first inverter, the input of which is connected to the output of the sign bit of the data register ADC and the second input of the second element AND, the output of the first majority element is connected to the bus of the positive control signal and the first input of the second element OR, the output of the second majority element is connected is not with the bus of the negative control signal, with the first input of the second element exclusive OR and the second input of the second element OR, the output of which is connected to the input of the upper order of the memory address register, the input of the second inverter and the input of the first one-shot, the output of which is connected to the S-input of the trigger, R - the input of which is connected to the output of the second one-shot, connected by its input to the output of the second inverter.