RU2474043C1 - Pulse selector - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: under conditions of noise disturbance with no input pulse available there is an additional strobe-pulse generated in the strobe, and its position is determined based on the preceding interval of occurrence of the input pulse, i.e. in the assumption that the last received pulse is a noise. The pulse selector comprises the following components: a unit of first pulse separation, three OR circuits, three counters, two units of strobe generation, four AND circuits, two count units, a generator, a trigger, a coder, a code shifter, two summators, two registers and a switchboard with appropriate connections.

EFFECT: higher reliability of selector functioning under conditions of noise effect.

1 dwg

Description

The invention relates to the field of pulsed technology, in particular to selectors for the period following, and can be used in the equipment of semi-active homing heads to isolate signals against interference.

Known selector (patent No. 2073953, CL H03K 5/26 from 04.11.93,), containing a series-connected block selection of the first pulse, the first element "NOT", the first element "OR", the delay element, the first gate driver, the second element "OR", the first and second elements "AND", a series-connected restart circuit, a failure indicator, a hit counter, a second element "NOT", a second gate driver and a third element "OR", as well as an adjustable delay device. The output of the first pulse extraction block is connected to the second inputs of the gate generator and the restart block, the output of the first element "NOT" is connected to the second input of the second OR element, the output of the first gate generator is connected to the third input of the restart circuit, the output of the second OR element is connected to by the second inputs of the hit counter and the adjustable delay device, the output of the first AND element is connected to the third inputs of the hit counter and the adjustable delay circuit, the first inputs of the restart circuit and the allocation unit the first pulse and the second inputs of the counter failure and the first element "OR". The output of the restart circuit is connected to the first inputs of the failure counter and the first pulse allocation unit. The output of the hit counter is connected to the fourth input of the restart circuit, the first input of the adjustable delay device and the second input of the second AND element. The output of the adjustable delay device is connected to the second input of the second gate driver, and the output of the third OR element is connected to the second input of the second AND element.

The closest in technical essence to the proposed one is the pulse selector for the period following (copyright certificate No. 1758864, class Н03К 5/26 of 03/11/90), containing a delay line, a block for the extraction of the first pulse, three elements "And", the trigger, the “OR” element, the delay element, the strobe forming unit, the conversion unit, the first pulse extraction unit, the “OR” element, the delay element, the strobe forming unit, the third AND element connected in series, the output of the third AND element connected to the first recount input ka, to the selector output and the second inputs of the gate formation unit and the OR element, the second input of the third AND element is connected to the input of the selector and the first inputs of the first pulse selection block, the first AND element and the delay line, delay line, first and third “AND” elements are connected in series, the trigger output is connected to the second input of the second “AND” element, and the first input of the trigger is connected to the output of the second “AND” element and the third input of the “OR” element, the fourth input of the “OR” element is connected to the output of the delay element , the second entrance is a cat cerned is connected to the second inputs of the delay lines, the block allocation of the first pulse, the flip-flop and the output sealer unit, the second input sealer unit connected to the output and the second output - to a third input of the gates forming. The delay line contains a clock generator, second and third triggers, a pulse counter, the first and second memory blocks and the second OR element, the output of which is connected to the output of the delay line, and the first and second inputs are with the outputs of the first and second memory blocks, respectively, address inputs which are bitwise connected to the outputs of the pulse counters, the write-read control inputs correspond to the first and second outputs of the third trigger, respectively, and the information inputs - to the output of the second trigger, the input is set It is connected to the first input of the delay line, the second input of which is connected to the reset inputs of the first and second memory blocks and the pulse counter, the counting input of which is connected to the output of the clock pulse generator and the reset input of the second trigger, and the overflow output is connected to the counting input of the third trigger.

The disadvantage of the above selectors is that in the presence of internal or external interference, they may get inside the gated interval, leading to an error in determining the position of the next input pulse and, as a consequence, to the loss of the input pulse. Moreover, these selectors switch to the resumption mode of searching for input signals at a given letter frequency, which leads to the loss of part of the output pulses.

The objective of the invention is to increase the reliability of the selector under the influence of interference.

This task is achieved by the fact that in the pulse selector containing a series-connected block selection of the first pulse, the first OR circuit, the first counter and the first block forming gates, series-connected the first circuit And and the first conversion block, series-connected generator and second counter, as well as a trigger , the second, third AND circuit, the second OR circuit, the output of the first AND circuit being the output of the pulse selector connected to the second input of the first OR circuit, the input of the pulse selector connected to the first the odes of the first pulse extraction unit and the first AND circuit, a series encoder, a code shifter, a first adder, a third counter, a second strobe generation unit, a fourth AND circuit and a third OR circuit, a first register, a second adder and a switch connected in series to a second a conversion block and a second register, the output of the first conversion block connected to the first inputs of the second AND circuit and the encoder, as well as to the second inputs of the switch and the second counter, the trigger output is soy Din with the first inputs of the third AND circuit and the second conversion unit and the second inputs of the encoder, code shifter and the fourth AND circuit, the output of the first circuit AND is connected to the first trigger input and the second inputs of the third OR circuit, the first and second registers and the third counter, the output of the first block the gate driver is connected to the second inputs of the second and third AND circuits, the second conversion block and the trigger and the first input of the second OR circuit, the output of the second circuit AND is connected to the second inputs of the highlight block of the first pulse and the first of the third block, the output of the third AND circuit is connected to the third inputs of the first OR circuit and the second conversion block, the encoder output is connected to the second inputs of the first and second strobe forming blocks, the generator output is connected to the third input of the third counter and the second input of the first counter, the output of the switch is connected to the third input of the first counter, and the fourth input of the switch is an input of the letter frequency code, the output of the first register is connected to the third input of the second register, the output of which is connected to the second input of the first sum ator, the second output of the second counting unit is connected to the second input of the first register, the output of the third OR circuit is connected to the fourth input of the third counter, the output of the fourth circuit AND is connected to the second input of the second OR circuit, the output of the second counter is connected to the third input of the first register, the output of the code shifter connected to the second input of the second adder, and the output of the second OR circuit is connected to the second input of the first circuit I.

The technical result is achieved by the fact that under the influence of interference in the absence of an input pulse, an additional strobe pulse is formed in the strobe, the position of which is determined by the previous interval of occurrence of the input pulse, i.e. under the assumption that the last received pulse was an obstacle.

In FIG. the block diagram of the selector is shown, where

1 - block allocation of the first pulse (BVPI),

2, 5, 7, 16 - circuit I (I2, I3, I1, I4, respectively),

3, 19 - recalculation unit (PB1, PB2, respectively),

8, 14, 23 - counters (CT1, CT2, CT3, respectively),

4, 17, 21 - OR scheme (OR 1, OR2, OR3, respectively),

6 - encoder (W),

9 - switch (K),

10, 24 - adder (CM2, CM1, respectively),

11 - shifter codes (SD),

12 - trigger (T),

13, 22 - block forming the strobe (BFS1, BFS2),

15, 20-register (RG1, RG2, respectively),

18 - generator (G),

The proposed device operates as follows.

When a supply voltage is applied to the device, a pulse is generated at the leading edge of the device, resetting the trigger 12 and the first 3 and second 19 counting units, thereby preparing the selector for receiving the input signal - a sequence of pulses with a predetermined repetition period. The predetermined repetition period is determined by the letter frequency code supplied to the input of the first counter 8 through the first signal switch 9 from the input of the letter frequency code of the pulse selector. The generator 18 generates clock pulses for the first 8, second 14 and third 23 counters.

The first of the input pulses arriving at the input of the extraction unit of the first pulse 1 is passed by it to the first input of the first OR 4 circuit and through it to the first input of the first counter 8, which performs the function of the delay element, making it start. The output pulse of the first counter 8 is delayed relative to the trigger for a while:

where T is the specified period of repetition of the input pulses;

t _with - the duration of the gating pulse;

N is the letter frequency code;

t ₀ is the repetition period of clock pulses.

This pulse is used to start the first block forming gates 13, forming a strobe pulse coming through the second circuit OR 17 to the input of the first circuit And 7 and allowing the passage of the next pulse, following at a given frequency, to the output of the selector. The leading edge of the strobe pulse is also reset trigger 12.

The duration of the strobe pulse is determined by the code N _p generated by the encoder 6. In the search mode, the value of this code is determined from the ratio:

where Δ is the largest deviation of the repetition period of the input pulses from the nominal,

Δ _g - the largest deviation of the formation time of the front of the gating pulse from the nominal.

The input pulse arriving in the gated interval, passing through the first circuit And 7, sets the first trigger 12 to state “1”, which fixes the next pulse in the gated interval, increments the state of the first recalculation block 3, fixing the number of consecutive (without gaps) of the input pulses in the gated interval, restarts through the second input of the first circuit OR 4, the first counter 8 and the second counter 14, forming a code of the current value of the repetition period of the input pulses. The first trigger 12, in turn, enables the pulse counting by the second counting unit 19. The trailing edge of the pulse from the output of the first strobe block is incrementing the state of the counting unit 19. When two input pulses fall in a gated interval, the first and second outputs of the second counting block are trailing the pulse from the output of the strobe forming unit is alternately set to a single state. In this case, the signal from the second output of the second counting unit allows the contents of the second counter 14 to be written to the first register 15, and from the first to overwrite the contents of the first register 15 to the second register 20. Thus, starting from the third input pulse falling into the gated interval in the first and second registers, codes are stored for the duration of the last and penultimate repetition periods of the input pulses, respectively. If there is no input pulse in the gated interval, trigger 12 remains in its initial state and allows resetting of the second counting block 19 through the third And 5 circuit, the first counting block 3 and the block of extraction of the first pulse 1 through the second And 2 circuit - the selector is ready to receive the first pulse of a new sequence. When falling into the gated interval, and therefore to the input of the counting unit 3, the required number of input pulses m (from three to five, depending on the required probability of a false alarm when the desired pulse sequence is detected and the acceptable search time), the signal from the output of the counting unit 3 translates selector in the tracking mode for the input pulses. In this case, the output signal of the first counting unit 3 prohibits the passage through the second circuit And 2 of the restart pulse of the extraction unit of the first impulse 1 and the counting unit 3, the switch 9 connects the second (information) input of the counter 8 through the second adder 10 to the output of the first register 15, i.e. . the predicted position of the strobe is determined by measuring the previous repetition period stored in the first register 15.

The signal from the output of the first conversion unit 3 also enters the input of the encoder 6 to generate a code for the duration of the gate pulse during tracking. The value of this code is determined by the ratio:

where Δ _k , Δ _gk is the short-term instability of the repetition periods of the input pulses and the predicted delay time generated by the counter 8, respectively.

To match the middle of the strobe pulse with the predicted position of the next input pulse in the adder 10, a difference is generated between the codes of the previous period of the input pulse and the code value of the duration of the strobe interval, which passes through the switch 9 to the second input of the first pulse counter 8. The code coming from the output is subjected to a similar transformation the second register 20 through the first adder 24 to the second input of the third counter 23.

With a regular hit of the input pulse in the predicted gating interval, the tracking of the input pulse sequence is as follows. Upon the arrival of the input pulse, the contents of the first register 15 is copied to the second register 20, the contents of the second counter 14 is copied to the first register 15, the second counter 14 is cleared and the result of measuring the current period is accumulated in it, the first counter 8 is started, the delay of the pulse from which is determined by the input the second adder 10 and the switch 9 updated contents of the first register 15, starts the third counter 23, the delay pulse from the output of which is determined by the updated contents of the second register 2 0. At the end of the delay times, triggering pulses of the first and second blocks of the formation of gates are formed, respectively. Since the passage of the strobe pulse from the output of the second driver of the strobe pulse 22 through the fourth circuit AND 16 to the input of the second circuit OR 17 is blocked by the single state of trigger 12, it does not affect the operation of the selector.

If there is no next pulse in the gating interval, trigger 12 remains in the initial state and the pulse from the output of the second block forming the gating pulse through the AND circuit is fed to the input of the OR circuit 17. Thus, the second gating interval is formed, which is assumed under the assumption that the last received input pulse was an obstacle . At the same time, the state of the logic level at the third input of the encoder and the code shifter 11 changes. At the same time, the code at the output of the encoder changes, and, consequently, the duration of the generated gate intervals. Moreover, if the absence of a pulse in the gated interval is due to the absence of input pulses, the required duration of the gating interval is determined by the ratio:

where n is the permissible number of missed pulses of the input signal. If the loss is due to interference, then the required duration of the gated interval:

As the duration of the strobe pulses, the larger of the values Δ _ps1 or Δ _{ps2 is selected} .

In the absence of output pulses of the selector, the formation of strobe pulses is as follows. On the trailing edge of the pulse, the first counter is launched from the output of the first strobe block. In this case, the code shifter 11, due to the action at the input of the logic zero level from the output of the trigger 12, generates a code shifted by one bit to the left (a code with a double value), which is subtracted further from the value of the code stored in the first register. Thus, the repetition period of strobe pulses at the output of the first gate driver remains equal to the last measured value of the repetition period of the input pulses. Similarly, strobe pulses are generated at the output of the second block of the gate generator 22. When the next pulse falls into one of the gated intervals, the first, second, and third counters are restarted — the selector is synchronized with respect to the input pulse. When the level of a logical unit appears at the output of the trigger, the code at the output of the encoder 6, and therefore, the duration of the strobe pulses decreases to a value determined by relation (3).

The first pulse extraction unit may be made in accordance with that used in the analogue and prototype.

The strobe forming units are delayed elements 1 and trigger 2 connected in series, the output of which is connected to the input of the delay line and is the output of the gate generator, and the installation input of the trigger is its input. The gate driver is launched by setting the trigger to the state of a logical unit, the end of the gate pulse occurs at the moment the trigger is reset by the pulse from the delay element. The delay element, in turn, can be implemented on the counter with a preset that is performed when the gate generator is started, and the pulse duration is determined by the parallel code supplied to the counter input.

Counting blocks can be performed, for example, on a shift register with a serial input connected to the level of a logical unit, and parallel outputs. Input 1 for the first conversion block and the third for the second are timing, input 2 for the first conversion block and second for the second are reset inputs, and the first input of the second conversion block is the shift enable input. The register of the second conversion block is two-bit, the number of triggers in the register of the first conversion block is m - the number of pulses sufficient to reliably detect the desired pulse sequence.

Other components of the proposed selector can be implemented on chips of the 533 series, or using programmable logic integrated circuits (FPGA), compatibility on logical levels (for example, input 1 of the second circuit And the second input of the fourth circuit And inverse) is ensured by the inclusion of additional inverters. As a trigger, a 564TM2 chip can be used.

Claims (1)

A pulse selector comprising serially connected a first pulse extraction unit, a first OR circuit, a first counter and a first strobe forming unit, a first AND circuit and a first conversion unit, a generator and a second counter connected in series, as well as a trigger, a second, a third And circuit, a second OR circuit, wherein the output of the first AND circuit, which is the output of the pulse selector, is connected to the second input of the first OR circuit, the input of the pulse selector is connected to the first inputs of the allocation unit of the first pulse and the first AND circuit, characterized in that a sequentially connected encoder, a code shifter, a first adder, a third counter, a second gate forming unit, a fourth AND circuit and a third OR circuit, a first register, a second adder and a switch connected in series are connected in series the second conversion unit and the second register, the output of the first conversion unit connected to the first inputs of the second circuit And the encoder, as well as to the second inputs of the switch and the second counter, the trigger output is connected to the inputs of the third AND circuit and the second conversion unit and the second inputs of the encoder, code shifter and the fourth AND circuit, the output of the first AND circuit is connected to the first input of the trigger and the second inputs of the third OR circuit, the first and second registers and the second counter, the output of the first block of the gate generator connected to the second inputs of the second and third circuits AND, the second conversion block and trigger and the first input of the second circuit OR, the output of the second circuit And connected to the second inputs of the allocation unit of the first pulse and the first conversion block, you One of the third AND circuit is connected to the third inputs of the first OR circuit and the second conversion block, the encoder output is connected to the second inputs of the first and second strobe forming blocks, the generator output is connected to the third input of the third counter and the second input of the first counter, the output of the switch is connected to the third input of the first counter, and the fourth input of the switch is the input of the letter frequency code, the output of the first register is connected to the third input of the second register, the output of which is connected to the second input of the first adder, the second the second output of the second counting unit is connected to the second input of the first register, the output of the third OR circuit is connected to the fourth input of the third counter, the output of the fourth circuit And is connected to the second input of the second OR circuit, the output of the second counter is connected to the third input of the first register, the output of the code shifter is connected to the second input of the second adder, and the output of the second OR circuit is connected to the second input of the first circuit I.