SU972513A2 - Device for checking pulse sequence - Google Patents

Description

The invention relates to an automatic machine and computer engineering, in particular to pulse sequence control devices, and can be used in digital computing devices.

According to the main author. St. No. 440665, a pulse sequence control device is known that contains two OR elements, a first delay element, a trigger, a first AND element, and the output of the first OR element is connected to a counting input of a trigger, the zero input of which is connected to the • output of the first delay element., Whose input is connected to the output of the second OR element and with the first input of the first AND element, the second input of which is connected to the inverse output of the trigger, the output of the first AND element is the output of the device, the group of odd pulse inputs of which are connected ene respectively to the inputs of the first OR gate, the inputs of second OR input group are respectively the even pulses device [1].

However, the known pulse sequence control device has the following disadvantages:

- uneven delay in detecting the loss of pulses, which consists in the fact that the detection of the disappearance of an odd pulse occurs at the moment of arrival of the next even pulse, i.e. with a delay of one clock cycle, and the detection of the loss of an even pulse is delayed by two clock cycles (also at the time of arrival of the next even pulse), which in turn reduces the speed of the device;

- in the event of a failure or malfunction of the elements of the device, you may be; given false - a signal about the passage of pulses, which leads to a decrease in the reliability of the device.

_ The invention aims _{to claim} ²⁰ povy shenio 'device performance. This goal is achieved by the fact that the second and third delay elements, the second and third elements are introduced into the device for controlling the sequence of pulses ^; And, the third and fourth elements OR, the second control node, the first input · of the first control node connected to the first input of the second control node, 30 'the second input of which is connected to the second input of the first control node, the output of which is connected to the input of the second delay element, with the first input of the second AND element, with the first input of the third OR element, the second input of which is connected to the input of the third-5 of its delay element, with the output of the second control unit, with the first input of the third AND element, the second input of which is connected to the output of the second delay element output of the third delay element 10 is connected to the cop second input of the second AND gate, whose output is connected to a first input of the fourth OR gate, the second input. g; which is connected to the output of the third 15 AND element, the output of the third AND element is the first output of the device, the second output of which is connected to the output of the fourth OR element.

In FIG. 1 shows a functional diagram of a device; in FIG. 2 b a time diagram of states. .

The device contains an element OR 1 |, element OR 2, the first 3 and second 4 control nodes, consisting of trigger _ 5, delay element b, element ^ AND 7, elements 8 and 9, elements 10 ^x and il delay, elements OR 12Ί5 .13, inputs 14 and 15 of the control nodes.

The device operates as follows. thirty

At the outputs of the OR elements 1 and 2, signals of the assemblies of odd and even monitored pulses are generated, which then arrive at the inputs 14 and 15 of the control nodes 3 and 4 (Fig. 2a, b) '35 The operation of the first control node 3 is carried out in this way.

Odd pulses arrive directly at the counting input of the trigger and translate it each time into a food-to-personal state (Fig. 2, c). The incoming even impulse through the delay element b (Fig. 2d) returns the trigger ι ger 5 to the zero state (Fig. 2c).

If the odd pulse disappears (Fig. 2a by a dot-dash line), trigger 5 is not brought into a single state and a high level from the inverse output of trigger 5 allows passage of the next even pulse (7) to the output of control channel 3 through element 7 (Fig. 2e). Thus, the delay in detecting the fact of the disappearance of an odd pulse for the first control node 3 is equal to one clock cycle.

If the even pulse disappears (dashed line in Fig. 2b), trigger 5 is converted to zero control (Fig. 2E). In this case, the delay n £ and the detection of the '· disappearance' of the even pulse of the first control channel 3 is two clock cycles.

The second control unit 4 operates in a similar manner and differs from the first control unit 3 in that even pulses are supplied to its input 14, and odd pulses to the input 15. In FIG. 2g, h shows the output pulses of the first 3 and second 4 control nodes corresponding to the disappearance of an odd pulse (Fig. 2A - dotted line). In Figs. 2i, k, the output pulses of the nodes 3 and 4 are shown. Monitoring when an even pulse disappears (Fig. 2b is a dashed line).

Elements 10 and 11 delays delay pulses from the outputs of nodes 3 and 4 for one clock cycle, and then their combination is checked by elements 8 and 9. If the odd pulse disappears, the output pulse of the first control channel 3, delayed by one clock by the delay element 10 (Fig.2zhpuntir), is fed to the first input of the And 8 element, the second input of which receives a pulse from the output of the second control node 4. These pulses coincide, and a pulse appears at the output of the OR 13 element, confirming the normal operation of the device.

When an even pulse disappears, the first pulse appears at the output of the second control node 4, which (is delayed by one clock of the delay elements 11 (Fig. 2k by a dashed line) and arrives at the first input of the And 9. element coincides with the pulses' and the output of the OR element 19 a pulse will appear confirming the normal operation of the device.

Thus, at the output of the element OR 12, in the event of the disappearance of any of the pulses, a pair of pulses will be generated, and the first pulse will be delayed by one clock cycle from the moment of the disappearance of any of the pulses. This pulse can be used to record the fact of the disappearance of pulses.

The introduction into the device of an additional second monitoring unit, identical to the first, of two OR elements, two AND elements, and two pulse delay elements, can significantly increase the reliability of digital devices and reduce equipment downtime by eliminating false triggering of the pulse sequence monitoring circuit.

Claims (1)

1. USSR author's certificate 440665, cl. G 06 F 11/00, 1972 (th rototype).