RU2430464C2 - Scaler with frequency-phase comparator circuit - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: proposed device comprises counters, comparators, control devices, pulse generator, trigger, threshold units, switches and memory units.

EFFECT: faster correction and higher data immunity.

1 dwg

Description

The invention relates to a pulse technique and can be used in information and telemetry systems.

A recounting device is known that contains a repetition counter, a switch, adder blocks, a control key, a shift register, a decoder adder, a majority element, an error counter, and a comparison circuit (see USSR author's certificate No. 729849, published on 04.25.1980).

A disadvantage of the known device is its low speed.

The closest in technical essence to the claimed invention relates to a recounting device containing counters, comparison units, elements that exclude OR and OR elements, a control unit with NOT elements, a shaper and a trigger (see USSR author's certificate No. 1424694, class H03K 21/40 , published on 08.20.1995).

The disadvantage of this device is the lack of noise immunity of data reception.

A recounting device with a frequency-phase comparison circuit contains counters 1-3, comparison blocks 4 and 5, a control unit 12, a shaper 13 and a trigger 14. The device includes: threshold blocks 8 and 9, keys 6 and 10, and memory blocks 7 and 11 A recalculation device with a frequency-phase comparison circuit ensures the automatic elimination of a single failure during a time that does not depend on the number of the meter that has knocked down and provides an indication of a group failure, in which data from the meters may not be received by an external device.

The invention relates to a pulse technique, namely to meters with increased requirements for reliable operation, can be used in information-measuring systems.

The technical result is an increase in the speed of correction and the exclusion of the issuance of false information in order to increase the noise immunity of data reception.

The specified technical result is achieved by introducing new design features, a threshold block, a key and a memory block, the output of which is connected to the information input of the key, the control input of which is connected to the failure output of the threshold block, the output of which is connected, are additionally introduced into the device into each comparison circuit with the control unit, the output of the comparison unit is connected to the input of the threshold unit, the output of the key is connected to the input of the comparison unit.

The drawing shows a structural diagram of a recalculation device with a frequency-phase comparison circuit.

The recounting device with a frequency-phase comparison circuit includes a first, second and third counters 1, 2, 3, a comparison unit 4, a comparison unit 5, threshold blocks 8 and 9, keys 6 and 10 and memory blocks 7 and 11, a control unit 12, driver 13, trigger 14, input bus 15, reset bus 16, first, second and third outputs 18, 19, 20 of control unit 12, output bus 17.

The first input of the comparison unit 4 is connected to the output of the counter 1 and to the information input of the counter 2, the output of which is connected to the second input of the comparison unit 4 and to the first input of the comparison unit 5, the second input of which is connected to the output of the counter 3 and the information input of the counter 1, the input the bus 15 is connected to the counting inputs of the counters 1-3, the reset inputs of which are connected to the reset bus 16, the zero setting input and the information input of the trigger 14 are connected respectively to the output bus 17, the reset bus 16 and the output of the former 13, the outputs of blocks 4, 5 inputs are connected respectively to the inputs of the threshold blocks 8 and 9, the first outputs of which are connected to the inputs of the control unit 12, the outputs 18, 19, 20 of which are connected respectively to the inputs for controlling the load of the counters 1, 2, 3, the information input of the counter 3 is connected to the output of the counter 2 , outputs 19, 20 of block 12 are connected respectively to the input of the shaper 13 and to the clock input of the trigger 14, the second outputs of the threshold blocks 8 and 9 are connected to the control inputs of the keys 6 and 10, which are connected to the comparison circuits 4 and 5, the reference signals from the memory blocks 7 and 11 enter through the keys 6 and 10 to the inputs of the comparison circuits 4 and 5.

The device operates as follows. On the bus 16 "reset" counters 1, 2, 3 and trigger 14 are set to zero, after which the counters 1,2, 3 begin the process of counting pulses received on the bus 15. During normal operation of the counters at the outputs of blocks 4 and 5 - zero signals, since at both inputs of each of these blocks the same signals. Accordingly, at both inputs of block 12 there are zero signals (for the case if the signal passes through the threshold block, that is, it is useful), and at outputs 18, 19, 20 - “units”. Upon receipt of the number from the memory unit 7 to the comparison circuit 4, the resulting signal should go to the threshold unit 8, where a certain threshold value is set based on the necessary noise immunity. If this threshold is increased, a signal appears at the input of the control unit 12, while the key 6 is open, through which new compliance measures are written to the memory unit 7. If the threshold is not exceeded, then the key 6 will not be opened, and the process of searching for the necessary signal will be repeated . The operation of blocks 5, 9, 10, 11 is similar. If a malfunction occurs, for example, of counter 1, then its code will not coincide with the code of counter 2, and the signals at the inputs of block 4 do not match, and a “one” signal will appear at its output. Thus, at the inputs of block 12, there will be a combination of “10” and at output 18 a zero signal will appear that will go to the input of the counter 1 load control. As a result, the correct counter code 3 will be written to counter 1, in all counters 1, 2, 3 there will be the same codes and block 12 will return to its original, normal state when there will be “units” at its outputs 18, 19, 20. Thus, a pulse is generated at the output 18, the duration of which is determined by the time of writing to the counter and the delay of blocks 4, 5, and 12.

If counter 2 is knocked down, then at the inputs of block 12 there will be a combination of “11”. A negative pulse is generated at output 19, by which the correct counter code 1 is written to counter 2.

Thus, the device automatically eliminates the failure of any of the counters, and the device is operable upon receipt of an unlimited number of failures, provided that at the same time two or three counters do not go off at once.

If two or three counters fail at the same time in the proposed device, that is, all three counters have different codes, then first there will be a combination of “11” at the inputs of block 12 and a pulse will be generated at output 19, by which the code of counter 1 will be written to counter 2. Since the codes of the counters 1, 2 are the same, then “zero” is set at the output of block 8, the “one” is saved at the output of block 9, because the codes of the counters 2, 3 are not the same. As a result of this, at the end of the pulse, a negative pulse is generated at the output 20. The pulse from the output 19 starts the driver 13, which generates a positive pulse that is approximately two times longer than the pulse duration of the control unit 12 during the action of the pulse at the clock input of the trigger 14, by its information input will be "one", the signal "malfunction" will be received on bus 17. If the information inputs of the counter 2 are connected to the outputs of the counter 3 (and not counter 1), the clock input of the trigger 14 is connected to the output 20 of block 12, then the functionality of the device will be preserved.

Thus, the proposed recounting device with a frequency-phase comparison circuit provides the automatic elimination of a single failure during a time that does not depend on the number of the failed counter, provides error elimination in the communication channel by comparing the received signal with the reference signal and a certain threshold value of the signal in phase and frequency , provides an indication of a group (unrecoverable) failure, in which data from the meters may not be received by external devices.

Claims (1)

A recalculation device with a frequency-phase comparison circuit containing an input bus, a reset bus, three counters and two comparison blocks, the first group of inputs of the first of which is connected to the outputs of the first counter and to the information inputs of the second counter, the outputs of which are connected to the second group of inputs of the first block comparison with the first group of inputs of the second comparison unit, the second group of inputs of which are connected to the outputs of the third counter and with the information inputs of the first counter, the input bus and the reset bus are connected respectively only with a counting input and a reset input of each of the counters, a control unit, a pulse shaper and a trigger, a direct output, a zero setting input and an information input of which are connected respectively to the output bus, a reset bus, and a pulse shaper output, the first, second, and third outputs of the block control are connected respectively to the inputs of loading control of the first, second and third counters, the information inputs of the last of which are connected to the outputs of the second counter, the second and third outputs of the control unit are connected they are respectively connected with the inputs of the driver and with the clock input of the trigger, characterized in that, in order to increase the speed of correction and exclude the issuance of false information, the first and second threshold blocks, the first and second keys, as well as the first and second memory blocks are additionally introduced into the device, the outputs of which are connected to the information inputs of the first and second keys, respectively, the control inputs of which are connected to the second outputs of the first and second threshold blocks, the first outputs of which are connected to the first and the second input of the control unit, the outputs of the first and second comparison units are connected to the inputs of the first and second threshold blocks, respectively, the outputs of the first and second keys are connected to the inputs of the first and second comparison unit.