RU2415509C1 - Pulse selector by repetition cycle - Google Patents

Abstract

FIELD: electricity. ^ SUBSTANCE: device comprises generator, address counter, memorising unit, six triggers, four "AND" circuits, two "OR" circuits, counter of digitisation intervals, three circuits of comparison, frequency divider, controlled frequency divider, counter-decoder, period counter, summator. ^ EFFECT: improved reliability of selector functioning under conditions of noise effect. ^ 1 dwg

Description

The invention relates to the field of pulsed technology, in particular to selectors for the period following, and can be used in the equipment of semi-active homing heads to isolate signals against interference.

Known selector (patent No. 2073953, CL H03K 5/26 from 04.11.93,), containing a series-connected block selection of the first pulse, the first element "NOT", the first element "OR", the delay element, the first gate driver, the second element "OR", the first and second elements "AND", a series-connected restart circuit, a failure indicator, a hit counter, a second element "NOT", a second gate driver and a third element "OR", as well as an adjustable delay device. The output of the first pulse extraction block is connected to the second inputs of the gate generator and the restart block, the output of the first element "NOT" is connected to the second input of the second OR element, the output of the first gate generator is connected to the third input of the restart circuit, the output of the second OR element is connected to by the second inputs of the hit counter and the adjustable delay device, the output of the first AND element is connected to the third inputs of the hit counter and the adjustable delay circuit, the first inputs of the restart circuit and the allocation unit the first pulse and the second inputs of the counter failure and the first element "OR". The output of the restart circuit is connected to the first inputs of the failure counter and the first pulse allocation unit. The output of the hit counter is connected to the fourth input of the restart circuit, the first input of the adjustable delay device and the second input of the second AND element. The output of the adjustable delay device is connected to the second input of the second gate driver, and the output of the third OR element is connected to the second input of the second AND element.

The disadvantage of the considered selector is that the first received pulse may not belong to the desired sequence. In this case, none of the useful impulses falls within the specified interval and the search process is repeated. The probability of the first pulse to appear from the desired sequence sharply decreases when there are pulse sequences in the input signal, in addition to noise, the repetition periods of which are close to the specified one. So, if there are N sequences in the spectrum of the input signal, the probability of the first pulse to arrive from the desired sequence P = 1 / N is small, which can lead to an unacceptably long duration of the search for a pulse sequence with a given repetition period.

The closest in technical essence to the proposed one is the pulse selector for the period following (copyright certificate No. 1758864, class Н03К 5/26), containing a delay line, a block for the extraction of the first pulse, three “I” elements, a trigger, an “OR” element, an element delays, a strobe formation unit, a conversion unit, the first pulse extraction unit, an “OR” element, a delay element, a strobe formation unit, a third AND element, are connected in series, the output of the third “I” element is connected to the first input of the conversion unit, the output the selector and the second inputs of the block forming the gates and the element "OR", the second input of the third element "AND" is connected to the input of the selector and the first inputs of the block selection of the first pulse, the first element "And" and the delay line, delay line, the first and third elements "AND "Are connected in series, the trigger output is connected to the second input of the second AND element, and the first input of the trigger is connected to the output of the second AND element and the third input of the OR element, the fourth input of the OR element is connected to the output of the delay element, the second input which sub It is connected to the second inputs of the delay line, the first pulse extraction unit, the trigger, and the output of the conversion unit, the second input of the conversion unit is connected to the output, and the second output to the third input of the strobe forming unit. The delay line contains a clock generator, second and third triggers, a pulse counter, the first and second memory blocks and the second OR element, the output of which is connected to the output of the delay line, and the first and second inputs are with the outputs of the first and second memory blocks, respectively, address inputs which are bitwise connected to the outputs of the pulse counters, the write-read control inputs correspond to the first and second outputs of the third trigger, respectively, and the information inputs - to the output of the second trigger, the input is set It is connected to the first input of the delay line, the second input of which is connected to the reset inputs of the first and second memory units and the pulse counter, the counting input of which is connected to the output of the clock pulse generator and the reset input of the second trigger, and the overflow output is connected to the counting input of the third trigger.

This selector is quite effective when there are up to 5 pulse sequences at close frequencies in the input signal, which is equivalent to having 5 irradiated targets in the field of view of the homing head, four of which are a source of interference. With an increase in the number of simultaneously present pulse sequences to 16, the noise density proportionally increases, which leads to an unacceptable increase in the probability of false alarm.

The objective of the invention is to increase the reliability of the selector under the influence of interference.

This task is achieved by the fact that in the pulse selector for the period following, containing a generator, address counter, storage unit, three triggers, series-connected first and second circuits “I”, third circuit “I”, two circuits “OR” are additionally introduced series-connected a sampling interval counter and a first comparison circuit, a frequency divider, a controlled frequency divider, a decoder counter, a period counter, a second and third comparison circuit, an adder, three triggers and a fourth “I” circuit, with the generator output connected to the input of the frequency divider and the first inputs of the controlled frequency divider and the counter-decoder, the second input of which is connected to the output of the frequency divider, the output of the controlled frequency divider is connected to the first inputs of the address counter, sampling interval counter, period counter, second trigger, and the fourth AND circuit ", As well as with the second input of the first comparison circuit, the first output of the counter-decoder is connected to the first inputs of the adder and the sixth trigger, its second output is connected to the second inputs of the second circuit “And” of the memory block, address counter and the first trigger, and the third output is with the first inputs of the fourth and fifth triggers, the output of the memory block is connected to the second inputs of the fourth and sixth triggers, the output of the first circuit “I” is additionally connected to the first inputs of the third circuit "And" and the storage unit, the third input of which is connected to the output of the adder, the second input of which is connected to the output of the address counter, the output of the fourth trigger is connected to the second input of the fifth trigger and the first input of the first OR circuit, output which is connected to the first input of the first And circuit, the second input of which is connected to the output of the first trigger, the output of the second And circuit is connected to the second input of the sampling interval counter, the output of which through the second comparison circuit is connected to the second input of the fourth And circuit, the output of which is connected to the first input of the third trigger, and the third input to the output of the third comparison circuit, the output of the second OR circuit is connected to the second inputs of the second trigger and the period counter, its second input is connected to the output of the first comparison circuit, and p the first input is the input of the initial installation, the output of the second trigger is connected to the second inputs of the third trigger and the first OR circuit, the third input of which is connected to the output of the sixth trigger, and the fourth input is connected to the output of the fifth trigger, the output of the period counter is connected to the first input of the third comparison circuit, the output of the third trigger is connected to the second input of the third AND circuit, the second input of the controlled frequency divider is the input of the selectable frequency code, the second input of the third comparison circuit is the input of the number code and the periods of analysis, the third input of the first comparison circuit and the second input of the second comparison circuit receive codes of numbers zero and one, respectively, the first input of the first trigger is the input of the selector, and the output of the third circuit "And" is its output.

The drawing shows a structural electrical circuit of the selector, where

1 - frequency divider (DF),

2 - counter-decoder (SCH),

3, 17, 23 - comparison schemes (CC3, CC1, CC2, respectively),

4 - generator (G),

5 - address counter (AdrSch),

6, 8, 11, 16, 18, 19, - triggers (Tr4, Tr2, Tr5, Tr6, Tr3, Tp1, respectively),

7 - period counter (SCP),

9 - controlled frequency divider (UDM),

10 - adder (Sum),

12, 13 - scheme "OR" (OR1, OR2, respectively),

14, 20, 21, 24 - “I” schemes (I4, I1, I2, I3, respectively),

15 - storage unit (ST),

22 - counter sampling intervals (MFR).

The proposed device operates as follows.

After applying power to the device at the corresponding inputs, the code of the selectable letter frequency and the code of the number of analysis periods are set. At the third input of the first comparison circuit 17, a zero code is constantly present, and at the second input of the second comparison circuit 23, a unit code. The signal "initial setup" through the second circuit, "OR" 13 resets the period counter 7 and sets the second trigger 8 - in the state "1". In turn, the signal from the output of the second trigger 8 resets the third trigger 18, which prohibits the signal from passing through the third AND circuit 24 to the selector output, and also blocks the signal from passing through the first OR circuit 12. At the same time, the logic a unit that allows the direct passage of the signal from the output of the first trigger 19 to the input of the storage unit 15 through the first circuit "And" 20 - the pulse selector is in the accumulation mode of the input signals. Under the influence of pulses from the output of the generator 4, pulses with a repetition period equal to the repetition period of the selected pulses are formed at the output of the controlled frequency divider 9, and pulses determining the sampling interval of the input signal of the selector are output at the output of the frequency divider 1. The frequency divider 1 generates pulses restarting the counter-decoder 2. The counter-decoder 2 carries out the pulse count of the generator 4 modulo 4, after which the count is stopped. Moreover, the presence of logical 1 at output 3 corresponds to the state “0” of counter 2, and the presence of a pulse at its first and second outputs corresponds to the state “1” and “2”, respectively. The trailing edge of the pulses from the second output of the counter-decoder 2, delayed relative to the pulses from the output of the frequency divider 1, the first trigger 19 is set to its initial state, and the state of the address counter 5 changes, the signal at the output of which determines the base address of the cell of the storage unit 15 to be processed . The absolute address for the storage unit 15, taking into account the offset determined by the signal from the first output of the counter-decoder 2, is formed by the adder 10. Any of the pulses received at the input of the selector in the interval between the reset pulses of the first trigger 19 sets it to the state “1”. The signal from the second output of the counter-decoder 2, preceding the reset of the first trigger 19, rewrites its state in the cell of the storage unit 15 at the base address. Thus, in the interval between the occurrence of overflow pulses at the output of the controlled frequency divider 9, the cells of the memory block 15 are filled with signal samples at the input of the selector, and in the absence of a signal, “0” is recorded, and in the presence of at least one pulse in the sampling interval, “1” . First, when the signal is “inactive”, the pulse from the output of the controlled divider 9 sets the trigger 8 to state “0”, which corresponds to the selector in the filtering mode. In this mode, the passage of signals through the first "OR" 12 is allowed, and the signal recorded in the cell of the storage unit 15 is determined by the ratio:

where D is the signal recorded in the storage unit 15 in the cell with the base address;

I - the state of the first trigger 19 to the end of the sampling interval;

Q _n , Q _n-1 , Q _{n + 1} - the value of the signal recorded in the storage unit in the cell with the base address, as well as in adjacent cells in the previous signal filtering cycles;

Λ, V are symbols of logical multiplication and addition, respectively.

Accounting signal values adjacent to the base cells of the storage unit 15 allows you to avoid omissions of the input signal due to the frequency inequality of the given and received to the input of the selector pulse sequence in the absence of synchronization of the position of the input pulse relative to the middle of the sampling interval of the input signal. In this case, the allowable mismatch of frequencies can be determined by the ratio:

where T _back , T _with - given and arriving at the input of the selector periods of repetition of the input pulses;

P is the number of periods of filtering the input signal required for reliable detection of the input signal;

t is the duration of the sampling interval of the input signal.

To determine the state of the base and adjacent cells of the storage unit 15 in the state “0” of the counter-decoder 2, the signal from the output 3 of the counter-decoder 2 is transferred to the fourth trigger 6, the contents of the cell of the storage unit are copied to the base (n) address, and the contents of the fifth trigger 11 are copied the fourth trigger 6. Thus, the contents of the fourth trigger 6 corresponds to the contents of cell number n, and trigger 11 to the contents of cell number n-1, defined in the previous sampling interval. In state “1” of counter-decoder 2, the signal from the first output of state counter 2 to the sixth trigger 16 corresponds to the contents of the cell with the address n + 1 of the storage unit 15. In state “2” of counter-decoder 2, the signal filtered into the cell with address n is written relation (1) the value of the input signal generated at the output of the first circuit "And" 20. When writing to the storage unit 15 logical 1, the sampling interval is considered active. In this case, at the same time as writing to the storage unit 15, the counter of sampling intervals is incremented 22. If, by the moment of the occurrence of an overflow pulse, the controlled frequency divider, which is the gate for the first comparison circuit 17, the state of the counter of sampling intervals 22 is zero (physically this means that there is no selector at the input pulses of a given frequency) logical 1 at the output of the first comparison circuit 17 through the second circuit OR 13 installs the second trigger 8 with the restart of the selector.

After several letter periods, the calculation of which is done by the counter of periods 7, and subject to the presence of a pulse sequence in the signal at the input of the selector with a repetition period close to the specified one, logical 1 will remain in only one cell of memory block 15, the contents of the sampling interval counter 22 will be equal to 1, thereby leading to the appearance of a logical unit at the output of the second comparison circuit 23. If the contents of the counter of periods 7 of the repetition of the letter frequency exceed P (the number of repetition periods sufficient for reliable analysis), the logical 1 appears at the output of the third comparison circuit 3, the overflow pulse at the output of the controlled frequency divider 9 carries out the third trigger 18 to state “1” through the fourth “I” circuit 14, thereby allowing in the next period analysis of the passage of the pulse from the output of the first circuit "And" 20 through the third circuit "And" 24 to the output of the selector, informing about the presence at the input of the selector pulses with a repetition period close to the letter. The predicted time of occurrence of the next pulse is the sampling interval with a number determined by the contents of the address counter 5 at the time the output pulse of the selector appears.

The proposed selector can be implemented on chips 533, 564 and 1638 series, or using programmable logic integrated circuits (FPGA). Counter-decoder 2 can be performed on a type 565IE8 chip with a shortened cycle; D-flip-flops 564TM2 can be used as triggers 6, 11, 16, 19, the first OR circuit 12 can be implemented on a 533ЛР13 chip, and the second on a chip 533LE1.

Mathematical modeling of the detection process and the results of tests carried out for the presence of simultaneously 32 pulse sequences at the input of the selector with repetition periods differing by 100 μs from each other show that reliable detection is achieved after 4-5 filtering periods.

Claims (1)

The pulse selector for the repetition period, containing a generator, an address counter, a memory unit, three triggers, connected in series the first and second circuits And, the third circuit And, two circuits OR, characterized in that it is additionally introduced in series connected counter sampling intervals and the first circuit comparisons, a frequency divider, a controlled frequency divider, a counter-decoder, a period counter, a second and third comparison circuit, an adder, three triggers and a fourth And circuit, the generator output being connected to the input frequency divider and the first inputs of the controlled frequency divider and counter-decoder, the second input of which is connected to the output of the frequency divider, the output of the controlled frequency divider is connected to the first inputs of the address counter, sampling interval counter, period counter, second trigger and fourth circuit And, as well as the second input of the first comparison circuit, the first output of the counter-decoder is connected to the first inputs of the adder and the sixth trigger, its second output is connected to the second inputs of the second circuit And, the memory unit a, the address counter and the first trigger, and the third output is with the first inputs of the fourth and fifth triggers, the output of the storage unit is connected to the second inputs of the fourth and sixth triggers, the output of the first circuit And is additionally connected to the first inputs of the third circuit And and the storage unit, the third input which is connected to the output of the adder, the second input of which is connected to the output of the address counter, the output of the fourth trigger is connected to the second input of the fifth trigger and the first input of the first OR circuit, the output of which is connected to the first input ohm of the first circuit And, the second input of which is connected to the output of the first trigger, the output of the second circuit And is connected to the second input of the counter of sampling intervals, the output of which through the second comparison circuit is connected to the second input of the fourth circuit And, the output of which is connected to the first input of the third trigger, and the third input is with the output of the third comparison circuit, the output of the second OR circuit is connected to the second inputs of the second trigger and the period counter, its second input is connected to the output of the first comparison circuit, and the first input is the input of the initial installation, the output of the second trigger is connected to the second inputs of the third trigger and the first OR circuit, the third input of which is connected to the output of the sixth trigger, and the fourth input is connected to the output of the fifth trigger, the output of the period counter is connected to the first input of the third comparison circuit, the output of the third trigger is connected to the second input of the third circuit And, the second input of the controlled frequency divider is the input of the selectable frequency code, the second input of the third comparison circuit is the input of the code of the number of analysis periods, to the third input of the first comparison methods and the second input of the second comparison circuit, the codes of numbers are zero and one, respectively, the first input of the first trigger is the input of the selector, and the output of the third circuit And is its output.