Summary of the invention
Technical problem to be solved by this invention is to provide a kind of sef-adapting filter, can carry out filtering adaptively to input signal, and reject the Vibrating pulse near digital signal edge, filtering can not produce extra phase shift or time delay.
For solving the problem, the present invention proposes a kind of sef-adapting filter, comprising:
Pulse detecting unit, in order to receive input signal, and detects the pulse of described input signal, exports each pulse detection signals;
Pulse duration timing unit, in order to receive each pulse detection signals that described pulse detecting unit exports, and carries out timing to the width of described each pulse, output pulse width timing signal;
Pulse duration representative value statistic unit, receive the pulse duration timing signal that described pulse duration timing unit exports, and determine a representative value according to each pulse duration timing signal, and export described representative value, described representative value can reflect the Steady-state Parameters of the pulse duration of described input signal;
Dead band timing unit, receive the representative value of described pulse duration representative value statistic unit, an activationary time is determined according to representative value, in described activationary time, described dead band timing unit exports the inhibit signal in order to keep described input signal, otherwise described dead band timing unit exports follows signal in order to what follow described input signal.
According to one embodiment of present invention, described pulse detecting unit is edge detecting unit, in order to receive input signal, and detects the edge of each pulse of described input signal, exports each porch detection signal.
According to one embodiment of present invention, described edge detecting unit comprises a shift register, shift register is shifted in response to clock signal, described shift register is stored in the instantaneous signal levels in corresponding clock edge moment, stores according to shift register rising edge and the trailing edge that content determines each pulse.
According to one embodiment of present invention, next pulse of receiving in response to its input of described pulse duration timing unit and resetting.
According to one embodiment of present invention, described pulse duration timing unit is configured to saturated blocking, and remains unchanged to reach setting maximum at pulse duration timing signal after.
According to one embodiment of present invention, described pulse duration representative value statistic unit, in the All Time of each section of setting-up time or the course of work, determines a representative value according to each pulse duration timing signal in this period.
According to one embodiment of present invention, described representative value is pulse duration timing signal corresponding to maximum pulse in every section of setting-up time.
According to one embodiment of present invention, described pulse duration representative value statistic unit comprises:
First comparison module, its first input end receives the pulse duration timing signal that described pulse duration timing unit exports, and its output exports comparative result;
First latch module, its input receives described comparative result, and its Enable Pin connects the output of described pulse detecting unit, and its output exports described representative value, and its output is also connected to the second input of described first comparison module simultaneously;
Wherein, when the signal of the first input end reception of described first comparison module is greater than the signal of the second termination receipts, the signal that described first input end receives is exported as comparative result, otherwise the signal that described second input receives is exported as comparative result.
According to one embodiment of present invention, described representative value is in the All Time of the course of work, the average weighted value of the pulse duration timing signal of new pulse and the pulse duration timing signal of history pulse, and with the pulse duration timing signal that this iteration obtains, formula is as (a):
PW
typ,n=PW
typ,n-1*λ+PW
n*(1-λ)(a)
Wherein, λ is the moving average factor, and the span of this factor is [0,1]; PW
typ, n-1for the pulse duration timing signal of history pulse, PW
nfor the pulse duration timing signal of new pulse.
According to one embodiment of present invention, described moving average factor value is 1/2
nor (1-1/2
n), N is positive integer.
According to one embodiment of present invention, the activationary time of described dead band timing unit is the value after certain proportion got by described representative value, and formula is as (b):
T
deadzone=r*PW
typ(0<r≤1)(b)
Wherein, r is the value ratio of representative value, PW
typfor described representative value, T
deadzonefor described activationary time.
According to one embodiment of present invention, the value ratio r of described representative value is 1/2
m, M is nonnegative integer.
According to one embodiment of present invention, described dead band timing unit also receives each pulse of described pulse detecting unit, and redefines described activationary time when each pulse occurs.
According to one embodiment of present invention, described dead band timing unit comprises:
Subtraction count module, the described representative value that its input received pulse width representative value statistic unit exports, it is got the value after certain proportion according to described clock signal to representative value and to subtract counting, receive each pulse detection signals of described pulse detecting unit simultaneously, be loaded into up-to-date described representative value when each pulse occurs, and the value after certain proportion is got to described representative value restart the counting that subtracts;
Second comparison module, its first input end receives the output signal of described subtraction count module, and its second end input zero, its output exports described inhibit signal or follows signal.
According to one embodiment of present invention, described subtraction count module is without symbol subtraction clock counter, and described pulse duration representative value statistic unit exports signless representative value.
According to one embodiment of present invention, the figure place M position less of the figure place of the output of described pulse duration representative value statistic unit of the input of described subtraction count module, with make representative value receive time by value for 1/2
m, M is nonnegative integer.
According to one embodiment of present invention, also comprise:
Output latch unit, its Enable Pin connects the output of described dead band timing unit, and its input inputs described input signal, and it is according to described inhibit signal or follow the corresponding maintenance of signal that signal makes its output export or follow described input signal.
The present invention also provides a kind of sef-adapting filter, comprising:
First pulse list edge detecting unit, in order to receive input signal, and detects the rising edge of a pulse of described input signal, exports rising edge of a pulse detection signal;
First pulse duration timing unit, in order to receive the rising edge detection signal that described first pulse list edge detecting unit exports, and carries out timing in conjunction with the width of clock signal to described each pulse, exports the first pulse duration timing signal;
First pulse duration representative value statistic unit, receive the first pulse duration timing signal that described first pulse duration timing unit exports, and determine a representative value according to each first pulse duration timing signal, and exporting described representative value, described representative value can reflect the Steady-state Parameters of the pulse duration of described input signal;
Second pulse list edge detecting unit, in order to receive input signal, and detects the pulse falling edge of described input signal, exports pulse falling edge detection signal;
Second pulse duration timing unit, in order to receive the trailing edge detection signal that described second pulse list edge detecting unit exports, and carries out timing in conjunction with the width of clock signal to described each pulse, exports the second pulse duration timing signal;
Second pulse duration representative value statistic unit, receive the second pulse duration timing signal that described second pulse duration timing unit exports, and determine a representative value according to each second pulse duration timing signal, and exporting described representative value, described representative value can reflect the Steady-state Parameters of the pulse duration of described input signal;
Data selector, the representative value that the representative value selecting described first pulse duration representative value statistic unit to export or the second pulse duration representative value statistic unit export exports, when rising edge detection signal is effective, select the representative value that described first pulse duration representative value statistic unit exports, otherwise when trailing edge detection signal is effective, select the representative value that described second pulse duration representative value statistic unit exports;
Dead band timing unit, receive the representative value that described data selector exports, described representative value is got certain proportion to obtain an activationary time, in described activationary time, described dead band timing unit exports the inhibit signal in order to keep described input signal, otherwise described dead band timing unit exports follows signal in order to what follow described input signal.
According to one embodiment of present invention, output latch unit, its Enable Pin connects the output of described dead band timing unit, and its input inputs described input signal, and it is according to described inhibit signal or follow the corresponding maintenance of signal that signal makes its output export or follow described input signal.
After adopting technique scheme, the present invention has following beneficial effect compared to existing technology: by detecting the pulse of input signal, timing is carried out to each pulse, the representative value that one can characterize input signal typical case effective pulse width is obtained according to each pulse duration timing signal, it is dead band state of activation within the scope of the time width that the value after certain proportion (this value ratio can be 1) got by this representative value, this state of activation keeps incoming signal level, then can follow the level of input signal under unactivated state, activationary time is determined according to effective pulse width, and excite according to pulse detection signals, this pulse is followed when the first effective impulse of input signal occurs, at the end of this effective impulse, namely input signal becomes no pulse, enter state of activation, input signal is kept in activationary time, namely keep this no pulse state, the Vibrating pulse then and then occurred after effective impulse is by filtering, before next effective impulse occurs, activationary time is used up.Sef-adapting filter of the present invention can realize filtering parameter self adaptation, has nothing to do with factors such as the frequencies of input signal, this be analog filter incomparable; Substantially without time delay and reducible duty ratio, can be used on high accuracy, high real-time occasion that traditional scheme cannot be applied; Can fully digitalization and to take resource few, directly can be integrated in the digital information processing systems such as FPGA inner, reduce the hardware cost because external circuit devices brings.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public concrete enforcement.
Filter of the present invention can adjust inner parameter automatically according to the real-time status of input signal, and filtering can not produce extra phase shift or time delay.Can combine with conventional comparator, replace the hysteresis function of traditional hysteresis loop comparator or the Filter Design of comparator, be applicable to being applied to the various occasions such as frequency measurement, threshold triggers, output control.
Referring to Fig. 1, in the present embodiment, sef-adapting filter can comprise pulse detecting unit 1, pulse duration timing unit 2, pulse duration representative value statistic unit 3, dead band timing unit 4.
Pulse detecting unit 1 receives input signal, and detects the pulse of input signal, exports each pulse detection signals.Pulse detection for input signal can be such as by detecting impulse level change, detecting the appearance that pulse is known in the edge change etc. of pulse.
In preferred embodiment, pulse detecting unit 1 can be edge detecting unit, and edge detecting unit receives input signal, and detects the edge of each pulse of input signal, exports each porch detection signal.
Edge detecting unit such as can detect the edge of input signal in real time by calculus of differences circuit or combinational logic circuit.When edge occurs, calculus of differences circuit output pulse or combinational logic circuit output logic high (can certainly be low, high and low be relative noun, for simplicity, describes it as height); When boundless along time, edge detecting unit, without effective output, is namely in logic low.
Edge detecting unit does not distinguish the pseudo-edge that the edge of input signal and noise produce, no matter which kind of edge, as long as it appears at its input, then edge detecting unit will output logic be high immediately, and switches back logic low after edge terminates.
In a specific embodiment, pulse detecting unit 1 comprises a shift register, shift register is shifted in response to clock signal, and described shift register is stored in the instantaneous signal levels in corresponding clock edge moment, determines rising edge and the trailing edge of each pulse according to the storage content of shift register, when the content in shift register is high, be shown to be pulse, when being low, be shown to be no pulse, and when content comprises high and low, then show to have occurred edge.
More specifically, referring to Fig. 2, by one, pulse detecting unit 1 can remain that the output of the 2bit shift register of synchronized sampling state judges, it can certainly be the shift register of more multidigit, shift register is under the driving of clock signal, and each clock cycle sampled input signal (input) also moves one.When the output of shift register is 01, illustrates and there occurs rising edge; When the output of shift register is 10, illustrates and there occurs trailing edge.Shift register output signal is the XOR operation result of content in dibit position.
An example of input signal of the present invention is the output signal of comparator, due to comparator input is analog signal, usually containing shake, thus when it and comparison value compares time, the shake near comparison value can produce unnecessary pulse, in Fig. 3, signal a is as test signal, visible, and the signal b exported from comparator creates Vibrating pulse near effective impulse, if do not process this input signal, then can have an impact to the work of following digital circuit.
Each pulse detection signals that pulse duration timing unit 2 received pulse detecting unit exports, and in conjunction with clock signal, timing is carried out to the width of each pulse, output pulse width timing signal.The width of paired pulses by can from quantification impulse width the time after timing, as the basis of follow-up formation representative value.
In one embodiment, next pulse of receiving in response to its input of pulse duration timing unit 2 and resetting.Concrete, pulse duration timing unit 2 can be realized by the mode such as digit counter or capacitor charging.Pulse duration timing unit 2 can comprise clock counter, counts, to obtain pulse duration timing signal in the width range of each pulse to the clock signal of input.Referring to Fig. 3, signal c, pulse duration timing unit 2 measures from last edge that (pulse of the present invention comprises effective impulse and Vibrating pulse, edge is also corresponding comprises effective edge and pseudo-edge) terminate time of experiencing to current time, if do not have new edge to start, then measured value is passed and linear increment in time.When new edge starts, pulse duration timing unit 2 is reset to zero immediately, and starts to measure the time that new porch experiences to next pulse edge.Pulse duration timing signal is the duration of each triangle signal in the signal c of Fig. 3.
Pulse duration timing unit 2 can be realized by a clock counter.In the present embodiment, use a 32bit to count 100MHz clock signal without symbol clock counter, its inner parameters computational methods are as follows:
Amount to and allow timing length to be about:
Can ensure that the undersaturated minimum frequency input signal of clock counter is 1/T
max, be about 23.3mHz.Preferably, saturated truncation can be done to clock counter, namely clock counter remains unchanged after reaching setting maximum, even if now the frequency of input signal is low again, also counter overflow (saturated and do not overflow) can not be caused, thus the restriction of the minimum frequency input signal of deactivation system.
When pulse duration timing unit 2 arrives at the edge of input signal, be reset to zero and restart counting, again and again the pulse duration between every two edges being measured, and be supplied to rearmounted unit using clock number as measurement result.
The pulse duration timing signal that pulse duration representative value statistic unit 3 received pulse width timing unit exports, and determine a representative value according to each pulse duration timing signal, and exporting representative value, representative value can reflect the Steady-state Parameters of the pulse duration of described input signal.Because the width of effective impulse and the width of Vibrating pulse exist larger difference, thus representative value can be used for distinguishing effective impulse and Vibrating pulse easily.
Pulse duration representative value statistic unit 3 adds up the measurement result each time of pulse duration timing unit, in each section of setting-up time, a representative value is determined according to the whole pulse duration timing signals in this period, in order to characterize the current Steady-state Parameters of input signal, for rearmounted unit at different levels, filter operation is performed to input signal.
The statistical method of pulse duration representative value statistic unit 3 is relevant to actual demand, usually, can preferred following several method: representative value is pulse duration timing signal corresponding to the maximum pulse of the All Time of the course of work (can certainly be in) in every section of setting-up time; Representative value is in every section of setting-up time, the average weighted value of the pulse duration timing signal of new pulse and the pulse duration timing signal of history pulse, and with the pulse duration timing signal that this iteration obtains.
Representative value is the mode of pulse duration timing signal corresponding to the maximum pulse in every section of setting-up time, concrete: get the maximum of the pulse duration in one section of setting-up time as representative value, and the statistics of this maximum that resets after this period, to avoid because the abnormal condition causing continuing is lost at accidental edge.Suppose that the pulse width measuring result in the time period is respectively { PW
1, PW
2..., PW
n, wherein each measurement result PW
ibe nonnegative real number, then representative value PW
typavailable following formula is expressed:
PW
typ=MAX({PW
1,PW
2,…,PW
n})
Use maximum as the method for representative value, the pseudo-edge of optional position can be filtered to greatest extent, ensure that output signal is very pure, be applicable to need as much as possible to perform filtration thus the occasion avoiding misoperation.
Representative value is in the All Time of the course of work, the average weighted value of the pulse duration timing signal of new pulse and the pulse duration timing signal of history pulse, and the mode of the pulse duration timing signal obtained with this iteration, specifically: use moving average algorithm, when new edge event being detected, by the mean value weighting of the pulse duration of last time and history pulse duration, obtain new mean value at every turn, by the continuous iteration of this method, and using the real-time results of iteration as representative value.Suppose that the pulse width measuring result after starting working is respectively { PW
1, PW
2..., PW
n, wherein each measurement result PW
ibe nonnegative real number, then representative value PW
typiterative process can express with following formula:
PW
typ,1=PW
1
PW
typ,2=PW
typ,1*λ+PW
2*(1-λ)
…
And have general formula (a):
PW
typ,n=PW
typ,n-1*λ+PW
n*(1-λ)(a)
Wherein, λ is the moving average factor, and the span of this factor is [0,1]; PW
typ, n-1for the pulse duration timing signal of history pulse, PW
nfor the pulse duration timing signal of new pulse.
The value of this moving average factor is less, then smooth effect is more weak, and filter is then stronger with the fast-changing ability of input signal; The value of this moving average factor is larger, then smooth effect is stronger, and filter suppresses the effect of accidental transient signal then better.Preferably, the above moving average factor can value be 1/2
nor (1-1/2
n), facilitate Digital Logical Circuits to realize, N is positive integer.Preferred, moving average selecting predictors is 7/8.
Use sliding average as the method for representative value, various periodicity and non-periodic signals can be adapted to preferably, and stability is better, is applicable to the occasions such as most step-by-step counting, frequency measurement.
The representative value of dead band timing unit 4 received pulse width representative value statistic unit, an activationary time is determined according to representative value, in activationary time, dead band timing unit 4 exports the inhibit signal keeping described input signal, otherwise dead band timing unit exports follows signal in order to what follow described input signal.
The a period of time of state that dead band refers to that output signal is in " maintenance ", during this period of time in (i.e. dead band), no matter how input signal changes, the digital signal that this filter exports remains at the state before entering dead band, will not overturn, with the filtering of the maintenance functional realiey Vibrating pulse in dead band.
In one embodiment, sef-adapting filter also comprises output latch unit 5.The Enable Pin of output latch unit 5 connects the output of dead band timing unit 4, its input input input signal, and it is according to inhibit signal or follow the corresponding maintenance of signal that signal makes its output export or follow input signal.
Dead band timing unit 4 directly controls output latch unit 5, and when dead band is in state of activation, output latch unit is in hold mode, and no matter how input signal changes, and it is constant that output signal maintains current level; On the contrary, when dead band activationary time time-out, when dead band switches to unactivated state, output latch unit 5 outputs signal and synchronously changes with input signal, namely follows input signal.
Each pulse of all right received pulse detecting unit of dead band timing unit 4, and redefine activationary time when each pulse occurs.The activationary time of dead band timing unit 4 is the statistics of pulse duration representative value statistic unit, whenever detecting that new edge produces, no matter why timing is before this worth remaining time, dead band timing unit all can be loaded into up-to-date representative value at once and start countdown, before the timing unit time-out of dead band, output latch unit is all in hold mode.
Alternatively, the activationary time of dead band timing unit 4 is set to the certain proportion of the representative value of pulse duration representative value statistic unit 3, instead of all, to realize more stable filtering performance.In other words, the activationary time of dead band timing unit is the value after certain proportion got by described representative value, and formula is as (b):
T
deadzone=r*PW
typ(0<r≤1)(b)
Wherein, r is representative value value ratio, PW
typfor described representative value, T
deadzonefor described activationary time.
When value ratio r is less than 1, filter allows new edge to arrive in advance, avoid causing the edge arrived in advance to be postponed by this filter because of excessive filtering, thus be more applicable for the unstable and real-time that exports of frequency input signal or the higher occasion of duty-cycle requirement.Preferably, r can be got and equal 1/2
m, M is nonnegative integer, facilitates Digital Logical Circuits to realize.Now according to maximum as statistic algorithm, then can whole pseudo-edge within the scope of 1/4th signal periods after the real edge of property filter cycle signal.
Below by concrete circuit connection diagram, sef-adapting filter of the present invention is described, but is only the concrete execution mode illustrated to set forth the present invention better, not as restriction.In order to clearly express logical AND function described in embodiment, in schematic diagram, eliminate power supply, reset and the part universal architecture for clock synchronous, signal delay etc.
Referring to Fig. 2, pulse detecting unit comprises DQ trigger 101, DQ trigger 102 and NOR gate circuit 103.Wherein the input of DQ trigger 101 receives input signal, the clock terminal receive clock signal of DQ trigger 101, the output of DQ trigger 101 is connected to the input of DQ trigger 102, the same receive clock signal of clock terminal of DQ trigger 102, the output of DQ trigger 101 and the output of DQ trigger 102 are connected respectively to two inputs of NOR gate circuit 103, and the output of NOR gate circuit 103 exports pulse detection signals.Thus realize according to the displacement of clock signal to input signal, to detect the generation of rising edge and trailing edge.
Pulse duration timing unit comprises clock counter 104, can be realized by Digital Logical Circuits, the clock terminal receive clock signal of clock counter 104, clear terminal connects the output of NOR gate circuit 103, thus start counting according to the generation of porch, reset according to the generation of porch, thus obtain pulse duration timing signal.
Pulse duration representative value statistic unit comprises: the first comparison module 105, the pulse duration timing signal that its first input end receive clock counter 104 exports, and its output exports comparative result; The input of the first latch module 106 receives the comparative result of the first comparison module 105 output, the Enable Pin of the first latch module 106 connects the output of NOR gate circuit 103, the output of the first latch module 106 exports representative value, and the output of the first latch module 106 is also connected to the second input of the first comparison module 105 simultaneously; Wherein, when the signal of the first input end reception of the first comparison module 105 is greater than the signal of the second termination receipts, the signal that the first input end of the first comparison module 105 receives is exported as comparative result, otherwise the signal that the second input of the first comparison module 105 receives is exported as comparative result.
The execution mode of pulse duration representative value statistic unit is not limited thereto, and in the present embodiment, selects maximum value process simply, and the method can ensure that filter can filter pseudo-edge to greatest extent.In the Digital Logic of the present embodiment, maximum statistical function can be made up of without sign register (the first latch module 106) and a 32bit unsigned number word comparator (the first comparison module 105) a 32bit.Register stores the temporal maximum statistics in nearest a period of time, and upgrades when arriving at the edge of each appointment polarity.Comparing of described register and up-to-date pulse duration statistical value be then responsible for by digital comparator, and will compare the maximum obtained and give the data input pin of described register.
Preferably, maximum statistics representative value is reset to 0 within a period of time, and restarts statistics, to avoid causing filter to continue normally to work because accidental edge loses.In the present embodiment, optionally to reset a statistics representative value every 30s.
Dead band timing unit comprises subtraction count module 107, the representative value that the output that subtraction count module 107 input receives the first latch module 106 exports, subtraction count module 107 is got the value after certain proportion according to clock signal to representative value and to be subtracted counting, the certain proportion got is representative value value ratio r, each pulse detection signals that the output simultaneously receiving NOR gate circuit 103 exports, be loaded into up-to-date representative value when each pulse occurs, and the value after certain proportion is got to described representative value restart the counting that subtracts; The first input end of the second comparison module 108 receives the output signal of subtraction count module 107, and the output of second end input the zero, second comparison module 108 of the second comparison module 108 exports inhibit signal or follows signal.The output of the second comparison module 108 connects the control end of output latch unit 109, and the input of output latch unit 109 receives input signal.
As preferred embodiment, dead band timing unit is realized by the clock counter of a subtraction count.This subtraction clock counter, when each edge arrives, is loaded into pulse duration representative value statistics according to representative value value ratio r, and starts countdown immediately.Preferred, subtraction count module is without symbol subtraction clock counter, pulse duration representative value statistic unit exports signless representative value, in one embodiment, the figure place M position less of the figure place of the output of pulse duration representative value statistic unit of the input of subtraction count module, M is nonnegative integer, and so representative value is 1/2 by value when being received by subtraction count module automatically
m, that is subtract counter can realize representative value value ratio is simultaneously 1/2
m, and without the need to other the digital device for realizing value ratio.Concrete, when pulse width counter bit wide is 32bit, a 31bit so can be used to carry out subtraction count without symbol subtraction clock counter to 100MHz system clock, it is 1/2 that subtract counter can realize representative value value ratio simultaneously.
The state of the direct controlling dead error of output of subtraction clock counter, when subtraction clock counter is non-vanishing, then dead band is in state of activation, and dead band judges that output signal is high as logic, and output latch unit 109 exports locking input signal and remains unchanged; Otherwise be logic low, output latch unit 109 output is followed input signal and is synchronously changed.
Subtract counter then stops counting immediately after reducing to zero, and remains on nought state, until next clock signal arrives and starts once new countdown always.
According to Fig. 2 embodiment, be 1Vpp to certain amplitude, frequency is that the analog signal of 100Hz is tested, and it is 20% that signal comprises amplitude, and frequency is about the HF noise signal of 1500Hz as test signal a.By the preposition non-hysteresis loop comparator of test signal a input adaptive filter, comparator reference voltage is set to 0.28V, comprises pseudo-edge, the porch that the width namely in signal b is less in the primary output signal of now comparator.Signal c after the timing of pulse duration timing unit is rendered as the triangle signal of linear growth, and suddenly falls when trailing edge, and the base width of each triangle signal is pulse duration.Signal d after the process of pulse duration representative value statistic unit is the statistics of pulse-width, and signal e is obtained after getting ratio, each triangle signal of signal e is for being in state of activation, under this state, the control signal f of output latch is low level, be used for controlling to keep input signal, the non-triangle signal of signal e is for being in unactivated state, and under this state, the control signal f of output latch is high level, is used for control to follow input signal.After the process of this sef-adapting filter unit at different levels, final stable output signal g does not comprise pseudo-edge and serves the effect of filtering at pseudo-edge.
The sef-adapting filter of the embodiment of the present invention can use the digital logic devices such as FPGA (field programmable gate array) as carrier, passes through digital circuit.In FPGA device, an overall system works clock is needed to drive the unit (such as pulse duration timing unit, dead band timing unit) of this filter, this work clock is higher, the peak frequency of the input signal that then can process is higher, but the bit wide of inner individual count device is also larger, and the logical resource taken is also more.In the present embodiment, system works clock is chosen as 100MHz, and now according to Nyquist criterion, the peak signal frequency allowing input is 50MHz (not comprising this value).
Referring to Fig. 4, the present invention also provides a kind of sef-adapting filter, comprising: the first pulse list edge detecting unit 21, in order to receive input signal, and detects the rising edge of a pulse of described input signal, exports rising edge of a pulse detection signal; First pulse duration timing unit 22, in order to receive the rising edge detection signal that described first pulse list edge detecting unit 21 exports, and carries out timing in conjunction with the width of clock signal to described each pulse, exports the first pulse duration timing signal; First pulse duration representative value statistic unit 23, receive the first pulse duration timing signal that described first pulse duration timing unit 22 exports, and determine a representative value according to each first pulse duration timing signal, and exporting described representative value, described representative value can reflect the Steady-state Parameters of the pulse duration of described input signal; Second pulse list edge detecting unit 24, in order to receive input signal, and detects the pulse falling edge of described input signal, exports pulse falling edge detection signal; Second pulse duration timing unit 25, in order to receive the trailing edge detection signal that described second pulse list edge detecting unit 24 exports, and carries out timing in conjunction with the width of clock signal to described each pulse, exports the second pulse duration timing signal; Second pulse duration representative value statistic unit 26, receive the second pulse duration timing signal that described second pulse duration timing unit 25 exports, and determine a representative value according to each second pulse duration timing signal, and exporting described representative value, described representative value can reflect the Steady-state Parameters of the pulse duration of described input signal; Data selector 27, the representative value that the representative value selecting described first pulse duration representative value statistic unit 23 to export or the second pulse duration representative value statistic unit 26 export exports, when rising edge detection signal is effective, select the representative value that described first pulse duration representative value statistic unit exports, otherwise when trailing edge detection signal is effective, select the representative value that described second pulse duration representative value statistic unit exports; Dead band timing unit 28, receive the representative value that described data selector 27 exports, an activationary time is determined according to representative value, in described activationary time, described dead band timing unit 28 exports the inhibit signal keeping described input signal, otherwise what described dead band timing unit 28 exported to follow described input signal follows signal.The output signal of dead band timing unit 28 controls output latch unit 29, to control the hold mode or the following state that export this input signal.
The embodiment of Fig. 4 is two edge filters, comprise with the single edge filter difference structurally in Fig. 1 and 2: first, the double edge detection function of pulse detecting unit is split as independently rising edge detecting unit and trailing edge detecting unit, and carries out pulse duration timing and pulse duration representative value statistics respectively.The second, when dead band timing unit needs to occur at the edge of any polarity of input signal, according to the Polarity Control data selector of current edge, select one of pulse duration representative value statistics of loading two opposite levels.Particularly, the output of two independently pulse duration representative value statistic units is connected to the input of data selector, the output of data selector is connected to the input of dead band timing unit, and the data select signal of data selector is then controlled by the output of the edge detecting unit of two opposed polarities.If it is 1 that rising edge edge detecting unit exports, it is 0 that trailing edge edge detecting unit exports, then the pulse duration representative value statistics that data selector selection rising edge edge detecting unit is corresponding, otherwise selects another.Two edge filters mode except this difference structurally of the embodiment of Fig. 4, all with reference to the aforementioned description about the single edge filter in Fig. 1 and 2, can not repeat them here.
Two edge filter accurately can go back the duty ratio of original input signal, and the pseudo-edge near the edge simultaneously filtering out any polarity, is applicable to occasion duty ratio being had to requirement, and such as power analysis, power quality analysis etc. measure quasi-instrument.
Although the present invention with preferred embodiment openly as above; but it is not for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.