CN103633963B - Based on duty ratio comparison circuit and the method for single-wire-protocol - Google Patents
Based on duty ratio comparison circuit and the method for single-wire-protocol Download PDFInfo
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- CN103633963B CN103633963B CN201310558032.9A CN201310558032A CN103633963B CN 103633963 B CN103633963 B CN 103633963B CN 201310558032 A CN201310558032 A CN 201310558032A CN 103633963 B CN103633963 B CN 103633963B
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Abstract
The present invention relates to the duty ratio comparison circuit based on single-wire-protocol, comprise: input connects the edge sense circuit, up counter and the subtract counter that input pwm signal, wherein the input end of clock of up counter and subtract counter is also connected with counting clock, signal after detection is input in described up counter and subtract counter by edge sense circuit, and up counter is connected output pulse signal after carrier adder through latch respectively with the output of subtract counter.The present invention is based on duty ratio comparison circuit and the method for single-wire-protocol, due to there is not traditional circuit simulation manner of comparison in too low or the too high and situation that is that cannot compare of charging voltage, compare therefore, it is possible to realize duty ratio accurately and rapidly under enough wide in range frequency range and change in duty cycle scope.
Description
Technical field
The present invention relates to comparison circuit and the method for duty ratio, is the duty ratio comparison circuit based on single-wire-protocol and method concretely.
Background technology
Portable intelligent device to achieve the development of advancing by leaps and bounds and universal in recent years, and this growth momentum is also in continuity.The human-computer exchange of this kind of portable intelligent device is usually shown by lcd screen and contacts and realize, the LED-backlit driving chip of this kind of display screen also requires simpler and practical, therefore for realizing exact figure dimming function, often adopt multiplexing functions and single-wire-protocol to realize, only need a holding wire just can complete serial communication.
In order to determine the light modulation bit data of input pulse, common single-wire-protocol employing definition input signal is be greater than or less than the time of high level to be maintained the low level time, the counting clock frequency of setting certain proportion relation respectively to two counters is defined as two kinds of contrary light modulation bit data, as long as can realize its definition.Such as be judged to be 0 data bit when duty ratio is less than 50%, be judged to be 1 data bit when duty ratio is greater than 50%, this just needs duty ratio comparison circuit to realize.Common duty ratio comparison circuit adopts a certain constant current to fixed capacity at input PWM(pulse-width signal) height of waveform and low level stage charge respectively, utilize the voltage of analog comparator to twice charging to compare and draw duty ratio comparative result, but this comparative approach has certain area requirement to the frequency of pwm signal and duty ratio size, otherwise there will be capacitor charging voltage exceed comparator comparison range and cannot be relatively or relatively more inaccurate problem.
Therefore, need a kind of all can be able to realize under wide frequency ranges and wide change in duty cycle range of condition accurately and effective ratio compared with duty ratio comparative approach.
Summary of the invention
The invention provides a kind of duty ratio comparison circuit based on single-wire-protocol and method, under enough wide in range frequency range and change in duty cycle scope, realize duty ratio accurately and rapidly compare.
The present invention is based on the duty ratio comparison circuit of single-wire-protocol, comprise: input connects the edge sense circuit, up counter and the subtract counter that input pwm signal, wherein the input end of clock of up counter and subtract counter is also connected with counting clock, signal after detection is input in described up counter and subtract counter by edge sense circuit, and up counter is connected output pulse signal after carrier adder through latch respectively with the output of subtract counter.
Edge sense circuit is for detecting rising edge and the trailing edge of input pwm signal; Up counter is used for the counting timing when input pwm signal is low level state; Subtract counter is used for the counting timing when input pwm signal is high level state; The count results of up counter and subtract counter latches by latch, until export data during a PWM end cycle; The data that carrier adder receives latch output carry out phase add operation, and carry signal is light modulation data bit signal.
The present invention utilizes high frequency clock to count timing, carries out sample count respectively to low and high level, and recycling carrier adder realizes comparing function to true form and the add operation of radix-minus-one complement phase.Because counter does not exist too low or the too high and situation that is that cannot compare of charging voltage in the simulation manner of comparison of traditional circuit, the numeric ratio of the frequency range of any width therefore can be realized in theory comparatively.
Further, described up counter is positive sequence up counter, can according to the frequency of the frequency of counting clock and pwm signal and duty cycle range, and the setting count cycle, by 00 ... 0 counts up to 11 ... 1; Described subtract counter is backward subtract counter, also according to the frequency of counting clock and the frequency of pwm signal and duty cycle range setting count cycle, by 11 ... 1 counts up to 00 ... 0.
Further, up counter comprises at least 2 plus coujnt modules, normally by multiple plus coujnt module composition.
On this basis, the quantity of the subtraction count module in subtract counter and the quantity of described plus coujnt module adapt.
Further, described carrier adder comprises at least 2 carry addition modules, and signal exports after all carry addition modules after a reverser again.
Present invention also offers a kind of duty ratio comparative approach for foregoing circuit, comprise: the counting clock frequency that up counter and subtract counter are set by counting clock, by edge sense circuit, the rising edge of input pwm signal and trailing edge are detected respectively, and export narrow pulse signal, in order to control the enable and reset function of up counter and subtract counter, by latch, data are latched again, export data when a PWM end cycle and export after carrier adder carries out phase add operation to described data.
Further, according to the proportionate relationship between the up counter arranged and the counting clock frequency of subtract counter, light modulation data bit is arranged accordingly.Such as, setting corresponding light modulation data bit when pwm signal duty ratio is greater than 50% is 1, and setting corresponding light modulation data bit when pwm signal duty ratio is less than 50% is 0.If the counting clock changing up counter and subtract counter is the proportionate relationship of a certain setting, then can change above-mentioned definition.Such as, if the counting clock frequency of subtract counter is 2 times of up counter clock frequency, namely the light modulation data bit that definable is new: when pwm signal 0 state maintenance time is more than 2 times of 1 state maintenance time, can set corresponding light modulation data bit is 0, otherwise is defined as 1.
Concrete, the counting mode of described up counter and subtract counter is: the pwm signal of input is through edge sense circuit, respectively at rising edge and the trailing edge generation pulse signal of pwm signal, pulse enable signal up counter corresponding to PWM trailing edge starts counting, now subtract counter is reset mode, stop counting, counting clock is fixing counting clock signal; Pulse enable signal subtract counter corresponding to PWM rising edge starts counting, and enumeration data corresponding when being low level by pwm signal in up counter (light modulation data bit corresponding when such as duty ratio is less than 50%) sends into latches, up counter is resetted simultaneously, stop counting; When the trailing edge of next pwm signal arrives, subtract counter stops counting, and enumeration data when being high level by pwm signal in subtract counter (light modulation data bit corresponding when such as duty ratio is greater than 50%) sends into latches.
Further, when after a PWM end cycle, the enumeration data of up counter and the enumeration data of subtract counter all unlock in latch, send into carrier adder and carry out add operation, be output signal after highest order carry signal is anti-phase.
The present invention is based on duty ratio comparison circuit and the method for single-wire-protocol, due to there is not traditional circuit simulation manner of comparison in too low or the too high and situation that is that cannot compare of charging voltage, compare therefore, it is possible to realize duty ratio accurately and rapidly under enough wide in range frequency range and change in duty cycle scope.
Below in conjunction with the embodiment of embodiment, foregoing of the present invention is described in further detail again.But this should be interpreted as that the scope of the above-mentioned theme of the present invention is only limitted to following example.Without departing from the idea case in the present invention described above, the various replacement made according to ordinary skill knowledge and customary means or change, all should comprise within the scope of the invention.
Accompanying drawing explanation
Fig. 1 is the block diagram of the duty ratio comparison circuit that the present invention is based on single-wire-protocol.
Fig. 2 is the circuit diagram of Fig. 1.
Fig. 3 is the circuit diagram of the input pwm signal edge sense circuit of Fig. 2.
Fig. 4 is the waveform schematic diagram that the light modulation data bit of the single-wire-protocol of embodiment is determined.
Embodiment
The present invention is based on the duty ratio comparison circuit of single-wire-protocol as shown in Figure 1, comprise: input connects the edge sense circuit, up counter and the subtract counter that input pwm signal, wherein the input end of clock of up counter and subtract counter is also connected with counting clock, signal after detection is input in described up counter and subtract counter by edge sense circuit, and up counter is connected output pulse signal after carrier adder through latch respectively with the output of subtract counter.
As shown in Figure 2, described up counter is positive sequence up counter, by multiple plus coujnt module composition, can according to the frequency of the frequency of counting clock and pwm signal and duty cycle range, and the setting count cycle, by 00 ... 0 counts up to 11 ... 1; Subtract counter is backward subtract counter, also according to the frequency of counting clock CLK and the frequency of pwm signal and duty cycle range setting count cycle, by 11 ... 1 counts up to 00 ... 0.The quantity of the subtraction count module in subtract counter and the quantity of described plus coujnt module adapt.Carrier adder comprises multiple carry addition module, and signal exports after all carry addition modules after a reverser again.
In the present embodiment, definition sets corresponding light modulation data bit when pwm signal duty ratio is greater than 50% be 1, and setting corresponding light modulation data bit when pwm signal duty ratio is less than 50% is 0.In Fig. 2, PWM is input as external PWM signal, through edge sense circuit, the pulse signal of about 50ns is produced respectively at the rising edge of pwm signal and trailing edge, count up counter (by multiple plus coujnt module composition) corresponding to top in pulse enable signal Fig. 2 circuit of PWM trailing edge, subtract counter (by multiple subtraction count module composition) now below Fig. 2 circuit is reset mode, and stop counting, counting clock CLK is fixing counting clock signal.Start counting corresponding to the subtract counter below pulse enable signal Fig. 2 circuit of PWM rising edge, and the enumeration data in up counter when being 0 by PWM sends into latches, is resetted by up counter simultaneously, stops counting.When a PWM end cycle, the enumeration data of up counter and the enumeration data of subtract counter unlock in latch, send into carrier adder and carry out add operation, be output signal after highest order carry signal is anti-phase.The principle of above-mentioned 50% duty ratio criterion is described for 5-bit counter below.Up counter counts and the highlyest counts up to 11111 by 00000, and subtract counter counting by 11111 is up to 00000.If it is 10us that one group of PWM input signal trailing edge starts to maintain 0 level time, maintaining 1 level time is 12us, and counting clock frequency is 2MHz.Then start plus coujnt at trailing edge, count up to and occur rising edge, amount to several 20 clocks, namely count up to 10100 by 00000, when PWM rising edge starts to carry out subtraction count, amount to several 24 clocks, namely count up to 01000 by 11111, send 10100 and 01000 into carrier adder and carry out add operation, obtain 11100, carry is 0, and anti-phase rear output is 1, is this PWM cycle determined light modulation data bit.From this routine condition, if PWM receives rear maintenance high level time to be 10us, then this cycle is 50% duty ratio just, and namely subtract counter counts up to 01011, if be added 010110 with up counter data 10100, just be 11111, carry signal is 0, knownly counts up to before 01011 at subtract counter, and the carry of carrier adder is for being 1, also namely this situation is the critical value that duty ratio compares just, conforms to analysis.
Fig. 3 is the circuit diagram of edge sense circuit in Fig. 2, this circuit detects output branch road by trailing edge and rising edge detection output branch road is formed, article two, branch road has included reverser and the NOR gate of series connection, detects signal in output branch road also will export after a reverser after NOR gate at rising edge.This circuit can detect the trailing edge of pwm signal and rising edge respectively, by setting suitable capacitance on each branch road, can produce the high level pulse signal of 50ns, for carrying out enable and reset operation to up counter and subtract counter.
As shown in Figure 4, setting corresponding light modulation data bit when defining pwm signal duty ratio and being greater than 50% is 1, setting corresponding light modulation data bit when pwm signal duty ratio is less than 50% is 0, light modulation data in the single-wire-protocol that definable is complete, these data also can be used as the use of the logic function that other agreements define.In the diagram, T1, T2 represent two PWM input clock cycles respectively, and ta1 is maintained the low level time in one-period, and ta2 is the time being maintained high level in one-period; Tb1 is maintained the low level time in second period, and tb2 is the time being maintained high level in second period.Can find out, in one-period, ta1<ta2, namely the high level duty ratio in this cycle is greater than 1, and therefore this cycle corresponds to data " 1 "; In second period, tb1>tb2, namely the high level duty ratio in this cycle is less than 1, and therefore this cycle corresponds to data " 0 ", so analogize, complete digital dimming data or other logic function data can be defined according to the PWM data of input.
The all or part of step realizing said method embodiment can have been come by the hardware that program command is relevant, and handling procedure can be stored in a computer read/write memory medium, when program performs, performs the step comprising said method embodiment; Storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Claims (8)
1. based on the duty ratio comparison circuit of single-wire-protocol, its feature comprises: input connects the edge sense circuit of input pwm signal, up counter and subtract counter, wherein the input end of clock of up counter and subtract counter is also connected with counting clock, signal after detection is input in described up counter and subtract counter by edge sense circuit, up counter is connected output pulse signal after carrier adder through latch respectively with the output of subtract counter, described carrier adder comprises at least 2 carry addition modules, signal exports after all carry addition modules after a reverser again.
2., as claimed in claim 1 based on the duty ratio comparison circuit of single-wire-protocol, it is characterized by: described up counter is positive sequence up counter, described subtract counter is backward subtract counter.
3., as claimed in claim 1 based on the duty ratio comparison circuit of single-wire-protocol, it is characterized by: up counter comprises at least 2 plus coujnt modules.
4., as claimed in claim 3 based on the duty ratio comparison circuit of single-wire-protocol, it is characterized by: the quantity of the subtraction count module in subtract counter and the quantity of described plus coujnt module adapt.
5. for the duty ratio comparative approach of circuit described in claim 1, its feature comprises: the counting clock frequency being arranged up counter and subtract counter by counting clock, by edge sense circuit, the rising edge of input pwm signal and trailing edge are detected respectively, and export narrow pulse signal, in order to control the enable and reset function of up counter and subtract counter, by latch, data are latched again, export data when a PWM end cycle and export after carrier adder carries out phase add operation to described data.
6. duty ratio comparative approach as claimed in claim 5, is characterized by: according to the proportionate relationship between the up counter arranged and the counting clock frequency of subtract counter, arrange accordingly light modulation data bit.
7. duty ratio comparative approach as claimed in claim 5, it is characterized by: the counting mode of described up counter and subtract counter is: the pwm signal of input is through edge sense circuit, respectively at rising edge and the trailing edge generation pulse signal of pwm signal, pulse enable signal up counter corresponding to PWM trailing edge starts counting, now subtract counter is reset mode, stop counting, counting clock is fixing counting clock signal; Pulse enable signal subtract counter corresponding to PWM rising edge starts counting, and enumeration data corresponding when being low level by PWM in up counter sends into latches, is resetted by up counter simultaneously, stops counting; When the trailing edge of next pwm signal arrives, subtract counter stops counting, and enumeration data when being high level by pwm signal in subtract counter sends into latches.
8. the duty ratio comparative approach as described in claim 5 to 7 any one, it is characterized by: when after a PWM end cycle, the enumeration data of up counter and the enumeration data of subtract counter all unlock in latch, send into carrier adder and carry out add operation, after highest order carry signal is anti-phase, be output signal.
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Citations (4)
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| US5905406A (en) * | 1996-04-30 | 1999-05-18 | Switched Reluctance Drives Limited | Demodulator for a pulse width modulated signal and method |
| CN1713095A (en) * | 2004-06-24 | 2005-12-28 | 松下电器产业株式会社 | PWM circuit control method |
| CN102237847A (en) * | 2010-04-22 | 2011-11-09 | 安森美半导体贸易公司 | Motor drive circuit |
| CN102497710A (en) * | 2011-12-30 | 2012-06-13 | 成都芯源系统有限公司 | LED phase-shift dimming circuit and method thereof |
-
2013
- 2013-11-11 CN CN201310558032.9A patent/CN103633963B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5905406A (en) * | 1996-04-30 | 1999-05-18 | Switched Reluctance Drives Limited | Demodulator for a pulse width modulated signal and method |
| CN1713095A (en) * | 2004-06-24 | 2005-12-28 | 松下电器产业株式会社 | PWM circuit control method |
| CN102237847A (en) * | 2010-04-22 | 2011-11-09 | 安森美半导体贸易公司 | Motor drive circuit |
| CN102497710A (en) * | 2011-12-30 | 2012-06-13 | 成都芯源系统有限公司 | LED phase-shift dimming circuit and method thereof |
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