CN201689650U - Drive circuit for liquid crystal display - Google Patents
Drive circuit for liquid crystal display Download PDFInfo
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- CN201689650U CN201689650U CN2010202173799U CN201020217379U CN201689650U CN 201689650 U CN201689650 U CN 201689650U CN 2010202173799 U CN2010202173799 U CN 2010202173799U CN 201020217379 U CN201020217379 U CN 201020217379U CN 201689650 U CN201689650 U CN 201689650U
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Abstract
The utility model provides a drive circuit for a liquid crystal display comprising an initial direct current conversion unit initiating signals in the circuit required by other moulds except the direct current conversion unit, a detection unit detecting whether the initial direct current conversion unit has to-be-outputted signals which can be any signal required by all other moulds except the direct current conversion unit, an energy using unit providing signals to the drive circuit required by other moulds except the direct current conversion unit when the detection unit detects that the initial direct current conversion unit has to-be-outputted signals and a backup direct current conversion unit applied to provide signals to the drive circuit required by other moulds except the direct current conversion unit when the detection unit detects that the initial direct current conversion unit does not have to-be-outputted signals. The drive circuit of the utility model can render reliable and stable performances to ensure a liquid crystal display (LED) functions well.
Description
Technical field
The utility model embodiment relates to the LCD Technology field, relates in particular to a kind of liquid crystal display drive circuit.
Background technology
Be illustrated in figure 1 as the structural representation of prior art liquid crystal display drive circuit, can comprise gate driver circuit 1, dc conversion modules (being commonly referred to the DC/DC modular converter in this area) 3 and other modules 4 except dc conversion modules, other modules 4 except dc conversion modules can comprise various modules such as gate driver circuit 1, source electrode drive circuit 2 and gamma electric voltage generation module 6.Gate driver circuit 1 is used to drive the grid line on the LCD (Liquid Crystal Display) array substrate, source electrode drive circuit 2 is used to drive the data line on the LCD (Liquid Crystal Display) array substrate, gamma electric voltage generation module 6 is used to generate the required gamma electric voltage signal of source electrode drive circuit 2, dc conversion modules 3 is used to gate driver circuit 1 that grid cut-in voltage signal (being commonly referred to the VGH signal in this area) and gate off voltage signal (being commonly referred to the VGL signal in this area) are provided, and is provided for generating the analog voltage signal (being commonly referred to the AVDD signal in this area) of gamma electric voltage signal for gamma electric voltage generation module 6.Dc conversion modules 3 can also provide various desired signals for other modules in the liquid crystal display-driving module.
AVDD signal, VGL signal and VGH signal etc. are most important for the normal demonstration of LCD, and any one signal can't normally be exported the demonstration that all can influence LCD.In some particular application, Military Application such as navigation, aviation occasion for example, high for the normal display requirement of LCD, in case LCD breaks down, consequence is hardly imaginable.
It is problem demanding prompt solution in the prior art that the high liquid crystal display drive circuit of a kind of stability is provided.
The utility model content
The utility model provides a kind of liquid crystal display drive circuit at problems of the prior art, and stability is high, can guarantee the normal demonstration of LCD.
The utility model provides a kind of liquid crystal display drive circuit, comprises dc conversion modules, and described dc conversion modules comprises:
Be used to other modules except described dc conversion modules in the described liquid crystal display drive circuit that the initial dc conversion unit of desired signal is provided;
Be used to detect the detecting unit whether described initial dc conversion unit has measured signal output, described detecting unit is connected with described initial dc conversion unit, and described measured signal is any one in other module desired signals except described dc conversion modules in the described liquid crystal display drive circuit;
Being used for detecting described initial dc conversion unit at described detecting unit has under the situation of measured signal output, the signal that described initial dc conversion unit is provided sends to the unit that enables of other modules except described dc conversion modules in the described liquid crystal display drive circuit, describedly enables that other modules except dc conversion modules are connected in unit and described detecting unit, initial dc conversion unit and the described liquid crystal display drive circuit;
Being used for detecting described initial dc conversion unit at described detecting unit does not have under the situation of measured signal output, other modules in described liquid crystal display drive circuit except dc conversion modules provide the backup dc conversion unit of desired signal, and other modules in described backup dc conversion unit and described detecting unit and the described liquid crystal display drive circuit except dc conversion modules are connected.
Can also comprise the power supply starting signal generation unit that is used for behind the power initiation of LCD, producing enabling signal;
Described detecting unit comprises the clock signal generation unit, first d type flip flop, second d type flip flop, 3d flip-flop and the four d flip-flop that are used for clocking, first or door, second or door and not gate;
Described first or the door two input ends be connected with the power supply starting signal generation unit with described initial dc conversion unit respectively;
The CP input end of described first d type flip flop with described first or the door output terminal be connected, the D input end is used for the input high level signal;
The D input end of described second d type flip flop is connected with the Q output terminal of described first d type flip flop, and the CP input end is connected with described clock signal generation unit;
The D input end of described 3d flip-flop is connected with the Q output terminal of described second d type flip flop, and the CP input end is connected with described clock signal generation unit;
The D input end of described four d flip-flop is connected with the Q output terminal of described 3d flip-flop, and the Q output terminal of described the 4th trigger is connected with standby dc conversion unit with the described unit that enables;
The input end of described not gate is connected with described clock signal generation unit, and output terminal is connected with the CLRN input end of described first d type flip flop;
Described second or the door two input ends be connected with the power supply starting signal generation unit with described clock signal generation unit respectively, output terminal is connected with the CP input end of described four d flip-flop.
Wherein, described power supply starting signal generation unit comprises:
Be used for behind the power initiation of LCD, producing the power supply starting signal generation subelement of enabling signal;
Be used for described power supply starting signal is generated the filtering subelement that power supply starting signal that subelement generates carries out filtering, described filtering subelement respectively with described power supply starting signal generate subelement, second or input end of door and first or an input end of door be connected.
Described filtering subelement comprises the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop and the 8th d type flip flop;
The D input end of described the 5th d type flip flop generates subelement with described power supply starting signal and is connected, and the CP input end is connected with described clock signal generation unit;
The D input end of described the 6th d type flip flop is connected with the Q output terminal of described the 5th d type flip flop, and the CP input end is connected with described clock signal generation unit;
The D input end of described the 7th d type flip flop is connected with the Q output terminal of described the 6th d type flip flop, and the CP input end is connected with described clock signal generation unit;
The D input end of described the 8th d type flip flop is connected with the Q output terminal of described the 7th d type flip flop, the CP input end is connected with described clock signal generation unit, the Q output terminal of described the 8th d type flip flop with described second or input end of door and first or an input end of door be connected.
Described clock signal generation unit comprises:
Be used to provide the crystal oscillator of the signal of reference frequency, be connected with the CP input end of described second d type flip flop, the CP input end of 3d flip-flop, the CP input end of the 5th d type flip flop, the CP input end of the 6th d type flip flop, the CP input end of the 7th d type flip flop and the CP input end of the 8th d type flip flop;
The frequency that is used for signal that described crystal oscillator is produced is carried out the first frequency division subelement that first frequency division is handled, the described first frequency division subelement and described crystal oscillator, second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
The described first frequency division subelement comprises:
Be used for first counter that the signal of described crystal oscillator output is counted;
First comparer that is used for the size of the count value of more described first counter and first preset value;
Be used for the 9th d type flip flop with the signal lag of described first comparer output, the D input end of described the 9th d type flip flop is connected with the output terminal of described first comparer, the CP input end is connected with described crystal oscillator, the PRN input end is used for the input high level signal, the CLRN input end is used for the input high level signal, the clear terminal of Q output terminal and described first counter, described second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
Described clock signal generation unit comprises:
Be used to provide the crystal oscillator of the signal of reference frequency, be connected with the CP input end of described second d type flip flop, the CP input end of 3d flip-flop, the CP input end of the 5th d type flip flop, the CP input end of the 6th d type flip flop, the CP input end of the 7th d type flip flop and the CP input end of the 8th d type flip flop;
The frequency that is used for signal that described crystal oscillator is produced is carried out the first frequency division subelement that first frequency division is handled, and the described first frequency division subelement is connected with described crystal oscillator;
Be used for the signal that the described first frequency division subelement carries out after first frequency division is handled is carried out the second frequency division subelement that second frequency division is handled, the described second frequency division subelement is connected with the described first frequency division subelement;
Be used for the signal that the described second frequency division subelement carries out after second frequency division is handled is carried out the three frequency division subelement that three frequency division is handled, described three frequency division subelement respectively with the described second frequency division subelement, second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
The described first frequency division subelement comprises:
Be used for first counter that the signal of described crystal oscillator output is counted;
First comparer that is used for the size of the count value of more described first counter and first preset value;
Be used for the 9th d type flip flop with the signal lag of described first comparer output, the D input end of described the 9th d type flip flop is connected with the output terminal of described first comparer, the CP input end is connected with described crystal oscillator, the PRN input end is used for the input high level signal, the CLRN input end is used for the input high level signal, and the Q output terminal is connected with the clear terminal of described first counter;
The described second frequency division subelement comprises:
Be used for second counter that the signal of described the 9th d type flip flop Q output terminal output is counted;
Second comparer that is used for the size of the count value of more described second counter and second preset value;
Be used for the tenth d type flip flop with the signal lag of described second comparer output, the D input end of described the tenth d type flip flop is connected with the output terminal of described second comparer, the CP input end is connected with described crystal oscillator, the PRN input end is used for the input high level signal, the CLRN input end is used for the input high level signal, and the Q output terminal is connected with the clear terminal of described second counter; Described three frequency division subelement comprises:
Be used for the 3rd counter that the signal of the Q output terminal of described the tenth d type flip flop output is counted;
The 3rd comparer that is used for the size of the count value of more described the 3rd counter and the 3rd preset value;
Be used for the 11 d type flip flop with the signal lag of described the 3rd comparer output, the D input end of described the 11 d type flip flop is connected with the output terminal of described the 3rd comparer, the CP input end is connected with described crystal oscillator, the PRN input end is used for the input high level signal, the CLRN input end is used for the input high level signal, the clear terminal of Q output terminal and described the 3rd counter, described second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
The described unit that enables can be the 54HC245 chip.
Can also comprise: second not gate, the 3rd not gate and Sheffer stroke gate;
The input end of described second not gate is connected with described detecting unit, and output terminal is connected with the described unit that enables;
The input end of described the 3rd not gate is connected with described detecting unit;
Two input ends of described Sheffer stroke gate are connected with the power supply starting signal generation unit with the output terminal of described the 3rd not gate respectively, and output terminal is connected with described backup dc conversion unit.
The liquid crystal display drive circuit that the utility model provides, in dc conversion modules, adopted the backup dc conversion unit to be used as the backup units of initial dc conversion unit, can't normally export under the situation of measured signal in initial dc conversion unit, the backup dc conversion unit also can replace the required signal of each module outside the initial dc conversion unit output LCD processing dc conversion modules, thereby guarantee that LCD can normally show, reduce LCD owing to various signals can't normally be exported the probability of the fault appearance that causes, improved the stability of the driving circuit of LCD.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do one to the accompanying drawing of required use in embodiment or the description of the Prior Art below introduces simply, apparently, accompanying drawing in describing below is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Figure 1 shows that the structural representation of prior art liquid crystal display drive circuit;
Figure 2 shows that the structural representation of the utility model liquid crystal display drive circuit;
Figure 3 shows that the structural representation of the utility model liquid crystal display drive circuit embodiment one;
Figure 4 shows that the sequential chart of each signal of structure shown in Figure 3;
Figure 5 shows that the concrete structure synoptic diagram of power supply starting signal generation unit among Fig. 3;
Figure 6 shows that the structural representation of filtering subelement among Fig. 5;
Figure 7 shows that the structural representation of the utility model liquid crystal display drive circuit embodiment two;
Figure 8 shows that the structural representation of the first frequency division subelement among Fig. 7;
Figure 9 shows that the structural representation of the utility model liquid crystal display drive circuit embodiment three;
Figure 10 shows that the structural representation of the second frequency division subelement among Fig. 9;
Figure 11 shows that the structural representation of three frequency division subelement among Fig. 9;
Figure 12 shows that the structural representation of the utility model liquid crystal display drive circuit embodiment four.
Embodiment
For the purpose, technical scheme and the advantage that make the utility model embodiment clearer, below in conjunction with the accompanying drawing among the utility model embodiment, technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
Be illustrated in figure 2 as the structural representation of the utility model liquid crystal display drive circuit, this liquid crystal display drive circuit comprises dc conversion modules 3 and other the various modules 4 except dc conversion modules, and dc conversion modules 3 comprises: initial dc conversion unit 31, detecting unit 32, enable unit 33 and backup dc conversion unit 34.Initial dc conversion unit 31 is used to that the module of other except dc conversion modules 4 provides desired signal in the liquid crystal display drive circuit.Detecting unit 32 is connected with initial dc conversion unit 31, detect initial dc conversion unit 31 whether measured signal output is arranged, detecting unit 32 is connected with initial dc conversion unit 31, measured signal is any one in the module of other except dc conversion modules 4 desired signals in the liquid crystal display drive circuit, it for example can be the AVDD signal, can be the VGH signal, also can be the VGL signal, also can be other each signals.Preferably, can be the bigger signal of probability that normally to export in numerous signals of initial dc conversion unit 31 generations.Enable that other modules 4 except dc conversion modules are connected in unit 33 and detecting unit 32, initial dc conversion unit 31 and the liquid crystal display drive circuit, being used for detecting initial dc conversion unit 32 at detecting unit 32 has under the situation of measured signal output, and the signal that initial dc conversion unit 31 is provided sends to that the module of other except dc conversion modules 4 provides desired signal in the liquid crystal display drive circuit.Other modules 4 in backup dc conversion unit 34 and detecting unit 32 and the liquid crystal display drive circuit except dc conversion modules are connected, being used for detecting initial dc conversion unit 31 at detecting unit 32 does not have under the situation of measured signal output, and other modules 4 in liquid crystal display drive circuit except dc conversion modules provide desired signal.
The principle of work of liquid crystal display drive circuit as shown in Figure 2 is as follows:
The required various signals of each module in the initial dc conversion unit 31 output LCD, no matter in these signals which can't normally be exported, all will cause LCD normally to show, whether can select in these signals any one as measured signal so, detecting initial dc conversion unit 31 has measured signal output.If there is not measured signal output, so definite initial dc conversion unit can't normally be exported the required signal of each module in the liquid crystal display drive circuit, can start the required signal of each module in the backup dc conversion unit 34 output liquid crystal display drive circuits.If measured signal output is arranged, the signal that can determine initial dc conversion unit 31 outputs so is normal, do not need to start backup dc conversion unit 34, the various signals that initial dc conversion unit 31 produces can be offered each module in the LCD by enabling unit 33.
The liquid crystal display drive circuit that the utility model provides, in dc conversion modules, adopted the backup dc conversion unit to be used as the backup units of initial dc conversion unit, can't normally export under the situation of measured signal in initial dc conversion unit, the backup dc conversion unit also can replace the required signal of each module outside the initial dc conversion unit output LCD processing dc conversion modules, thereby guarantee that LCD can normally show, reduce LCD owing to various signals can't normally be exported the probability of the fault appearance that causes, improved the stability of the driving circuit of LCD.
Be illustrated in figure 3 as the structural representation of the utility model liquid crystal display drive circuit embodiment one, for convenience of explanation, the structure of mainly having drawn detecting unit among Fig. 3, the annexation of all the other each modules do not provide schematic structural drawing in detail with reference to Fig. 2 among Fig. 3.Among this embodiment, liquid crystal display drive circuit also comprises the power supply starting signal generation unit 5 that is used for producing enabling signal behind the power initiation of LCD.Detecting unit 32 comprises clock signal generation unit 321, first d type flip flop 322, second d type flip flop 323,3d flip-flop 324, four d flip-flop 325, first or door 326, second or door 327 and not gate 328.First or door two input ends (being labeled as 326a and 326b) of 326 is connected with power supply starting signal generation unit 5 with initial dc conversion unit respectively, promptly first or 326 two input end 326a and 326b import measured signal and power supply starting signal BOOT respectively.Among each embodiment below the utility model, be that the AVDD signal is that example illustrates with measured signal.The CP input end 322a of first d type flip flop 322 is connected with first or door 326 output terminal 326c, and D input end 322b is used for input high level signal VCC (each embodiment of the present utility model, high level signal is represented with VCC).The D input end 323b of second d type flip flop 323 is connected with the Q output terminal 322c of first d type flip flop 322, and CP input end 323a is connected with clock signal generation unit 321.The D input end 324b of 3d flip-flop 324 is connected with the Q output terminal 323c of second d type flip flop 323, and CP input end 324a is connected with clock signal generation unit 321.The D input end 325b of four d flip-flop 325 is connected with the Q output terminal 324c of 3d flip-flop 324, the Q output terminal 325c of the 4th trigger 325 with enable unit 33 and backup dc conversion unit 34 (not shown among Fig. 2 enable unit 33 and back up dc conversion unit 34) and be connected.The input end 328a of not gate 328 is connected with clock signal generation unit 321, and output terminal 328b is connected with the CLRN input end 322d of first d type flip flop 322.Second or door two input ends (being labeled as 327a and 327b respectively) of 327 be connected with power supply starting signal generation unit 5 with clock signal generation unit 321 respectively, output terminal 327c is connected with the CP input end 325a of four d flip-flop 325.
Be illustrated in figure 4 as the sequential chart of each signal of structure shown in Figure 3, HAVE represents the signal of the Q output terminal output of four d flip-flop, and SIGNAL represents measured signal, and CLK is the clock signal of crystal oscillator output, also is a reference signal.The CLK signal is carried out frequency division, can produce the clock signal of various frequencies, for example, it can be the clock signal (among the application's the embodiment this clock signal being represented with CLK1 μ s) of 1 μ s in the generation cycle, it also can be that ((among the application's the embodiment this clock signal being represented with CLK1ms) also can be the clock signal (among the application's the embodiment this clock signal being represented with CLK1s) of 1s in the generation cycle for the clock signal of 1ms in the generation cycle.The principle of work of detecting unit is described below in conjunction with Fig. 3 and Fig. 4.
Among Fig. 3, the CP input end of second d type flip flop 323 and the 3rd trigger 324 can input signal CLK, the input end of not gate and second or an input end of door can input signal CLK1 μ s.
If initial dc conversion unit can normally be exported measured signal, so first or the signal of the output terminal output of door be high level.The signal of the D input end output of first d type flip flop is a high level, as long as the clock signal of the CP input end of first d type flip flop input becomes after the high level, the Q output terminal of first d type flip flop will be exported high level signal.Under the most initial state, first or the power supply starting signal BOOT (representing power supply starting signal with BOOT among the utility model embodiment) of door input be high level, so signal t is a high level.Subsequently, signal t is being cleared when CLK1 μ s signal arrives again, and promptly signal t becomes low level.10 μ s to 50 μ s during this period of time in, the signal CLK1 μ s that signal t and clock signal generation unit produce is consistent, all does periodic variation, signal t is the inversion signal of clock signal clk 1 μ s.
Signal i is the signal of the Q output terminal output of 3d flip-flop, and signal i is than signal t two clocks (i.e. 2 CLK signal periods) of having delayed time, and the cycle of these two signals is consistent, and this is that time-lag action owing to second d type flip flop and 3d flip-flop causes.Signal i is exactly in fact 2 clocks of inversion signal time-delay signal afterwards of clock signal clk 1 μ s.
Signal o is a signal that is input to the CP input end of four d flip-flop, signal o is by second or the output terminal output of door, second or the door input end input clock signal CLK1 μ s, so signal o is identical with clock signal clk 1 μ s, and signal i is 2 clocks of inversion signal time-delay signal afterwards of clock signal clk 11 μ s, when the rising edge of signal o arrived so, signal i just in time was in high level, so the signal of the Q output terminal of four d flip-flop output keeps high level.That is to say that detecting unit detects initial dc conversion unit can normally export measured signal AVDD.
If initial dc conversion unit can not normally be exported measured signal AVDD, promptly first or the signal of that input end input that is used to import measured signal AVDD of door become low level, so first or the signal of the output terminal output of door still be high level.The signal of the D input end input of first d type flip flop also is a high level, and signal t also is a high level.
When the high level of clock signal CLK1 μ s arrived, first d type flip flop was cleared (the clear terminal CLRN of first d type flip flop is connected with first not gate, and the input end input clock signal CLK1 μ s of first not gate).After being cleared, because the signal of the CP input end of first d type flip flop input does not have rising edge, so in the ensuing time, signal t keeps low level, this signal t becomes signal i after time-delay, signal i also is a low level so, and the output signal of such four d flip-flop keeps low level.That is to say that detecting unit detects initial dc conversion unit can not normally export measured signal AVDD.
As can be seen from the above description, CLK1 μ s signal is actually a sampled signal, the signal of the measured signal of promptly sampling, and the cycle of CLK1 μ s signal has determined the speed of sampling.Other sampling rate if desired, then the input end of not gate and second or an input end of door can import the signal in other cycles, for example, can import CLK1s signal or CLK1ms signal.
Be illustrated in figure 5 as the concrete structure synoptic diagram of power supply starting signal generation unit among Fig. 3, power supply starting signal generation unit 5 comprises that power supply starting signal generates subelement 5a and filtering subelement 5b.Power supply starting signal generates subelement 5a and is used for producing enabling signal behind the power initiation of LCD.Filtering subelement 5b is used for that power supply starting signal is generated the power supply starting signal that subelement 5a generates and carries out filtering, filtering subelement 5b respectively with power supply starting signal generate subelement 5a, second or input end of door and first or an input end of door be connected.
Be illustrated in figure 6 as the structural representation of filtering subelement among Fig. 5, wherein, filtering subelement 5b can comprise the 5th d type flip flop 51, the 6th d type flip flop 52, the 7th d type flip flop 53 and the 8th d type flip flop 54.The D input end 51b of the 5th d type flip flop 51 generates subelement 5a with power supply starting signal and is connected, and CP input end 51a is connected with clock signal generation unit 321.The D input end 52b of the 6th d type flip flop 52 is connected with the Q output terminal 51c of the 5th d type flip flop 51, and CP input end 52a is connected with clock signal generation unit 321.The D input end 53b of the 7th d type flip flop 53 is connected with the Q output terminal 53c of the 6th d type flip flop 53, and CP input end 53a is connected with clock signal generation unit 321.The D input end 54b of the 8th d type flip flop 54 is connected with the Q output terminal 53c of the 7th d type flip flop 53, CP input end 54a is connected with clock signal generation unit 321, the Q output terminal 54c of the 8th d type flip flop 54 with second or input end of door and first or an input end of door be connected.The CP input end of the 5th d type flip flop 51, the 6th d type flip flop 52, the 7th d type flip flop 53 and the 8th d type flip flop 54 these several d type flip flops can be imported the CLK signal that crystal oscillator produces.
Be illustrated in figure 7 as the structural representation of the utility model liquid crystal display drive circuit embodiment two, for convenience of explanation, the structure of mainly having drawn the clock signal generation unit among Fig. 7, the annexation of all the other each modules can not provide schematic structural drawing with reference to figure 1 or Fig. 2 among Fig. 7.
Among the embodiment shown in Figure 7, clock signal generation unit 321 comprises the crystal oscillator 321a and the first frequency division subelement 321b.Crystal oscillator 321a is used to provide the signal of reference frequency, is connected with the CP input end of second d type flip flop, the CP input end of 3d flip-flop, the CP input end of the 5th d type flip flop, the CP input end of the 6th d type flip flop, the CP input end of the 7th d type flip flop and the CP input end of the 8th d type flip flop.The frequency that the first frequency division subelement 321b is used for signal that crystal oscillator 321a is produced is carried out first frequency division and is handled, the first frequency division subelement 321b and crystal oscillator 321a, second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
Be illustrated in figure 8 as the structural representation of the first frequency division subelement among Fig. 7, the first frequency division subelement 321b can comprise first counter 3211, first comparer 3212 and the 9th d type flip flop 3213.First counter 3211 is connected with crystal oscillator 321a, is used for the signal of crystal oscillator output is counted.First comparer 3212 is used for first comparer of the size of the count value of comparison first counter 3211 and first preset value.The 9th d type flip flop 3213 is used for the signal lag with 3212 outputs of first comparer.The D input end 3213a of the 9th d type flip flop 3213 is connected with the output terminal 3212b of first comparer 3212, CP input end 3213b is connected with crystal oscillator 321a, it is CP input end 3213b input CLK signal, PRN input end 3213c is used for input high level signal VCC, CLRN input end 3213d is used for input high level signal VCC, the clear terminal 3211a of Q output terminal 3213e and first counter, second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
First frequency division that the size of first preset value is carried out according to the first frequency division subelement needs is handled and is decided, if it is the signal of crystal oscillator output need be carried out Fractional-N frequency that first frequency division is handled, first preset value is exactly N so, for example, if it is the signal of crystal oscillator output need be carried out 10 frequency divisions that first frequency division is handled, first preset value is exactly 10 so.When the count value of first counter reached 10, first comparator output signal became high level, and the duration is the one-period of the signal of crystal oscillator output.When the rising edge of the signal of the 11st crystal oscillator output arrives, the count value of first counter and first preset value are unequal, so signal of the first comparer output low level, the output signal of the 9th d type flip flop also becomes low level, and the low level signal of the 9th d type flip flop output is with first counter O reset, first counter is counted the signal of crystal oscillator output again, and in during counting again, the output of the 9th d type flip flop keeps low level.Like this, the first frequency division subelement carries out 10 frequency divisions with regard to having realized with the signal of crystal oscillator output.
Among Fig. 8, what the first frequency division subelement was handled the back generation can be CLK μ s signal, and so, in conjunction with Fig. 7, Fig. 8 and Fig. 3, the CLK signal can be produced by crystal oscillator, and CLK μ s signal is produced by the first frequency division subelement.
Be illustrated in figure 9 as the structural representation of the utility model liquid crystal display drive circuit embodiment three, for convenience of explanation, the structure of mainly having drawn the clock signal generation unit among Fig. 9, the annexation of all the other each modules can not provide schematic structural drawing with reference to figure 1 or Fig. 2 among Fig. 9.
Among this embodiment, clock signal generation unit 321 comprises crystal oscillator 321a, the first frequency division subelement 321b, the second frequency division subelement 321c and three frequency division subelement 321d.This embodiment compares with embodiment shown in Figure 7, has increased by two frequency division subelements, can be different from CLK μ s signal the generation cycle, and among this embodiment, different among the connected mode of the first frequency division subelement and Fig. 7.Among Fig. 9, crystal oscillator 321a is used to provide the signal of reference frequency.The first frequency division subelement 321b is used for that the frequency of the signal of crystal oscillator 321a generation is carried out first frequency division to be handled, and the first frequency division subelement 321b is connected with crystal oscillator 321a.The second frequency division subelement 321c is used for the signal that the first frequency division subelement 321b carries out after first frequency division is handled is carried out the processing of second frequency division, and the second frequency division subelement 321c is connected with the first frequency division subelement 321b.Three frequency division subelement 321d is used for that the second frequency division subelement 321c is carried out signal after second frequency division is handled to carry out three frequency division and handles, three frequency division subelement 321d respectively with the second frequency division subelement 321c, second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
The structure of the first frequency division subelement can be identical with Fig. 8 among Fig. 9, if the first frequency division subelement shown in Figure 8 is applied to Fig. 9, then the Q output terminal of the 9th d type flip flop can be not with second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate, but be connected with the second frequency division subelement 321c with the clear terminal 3211a of first counter.
Figure 10 shows that the structural representation of the second frequency division subelement among Fig. 9, the second frequency division subelement 321c comprises second counter 3214, second comparer 3215 and the tenth d type flip flop 3216.Second counter 3214 is used for the signal of the 9th d type flip flop 3213 outputs is counted, the CP input end 3214b of second counter 3214 is connected with the Q output terminal 3213e of the 9th d type flip flop 3213, and promptly the CP input end 3214b of second counter 3214 imports the signal of the Q output terminal 3213e generation of the 9th d type flip flop 3213.Second comparer 3215 is used for the count value of comparison second counter 3214 and the size of second preset value.The tenth d type flip flop 3216 is used for the signal lag with 3215 outputs of second comparer, the D input end 3216a of the tenth d type flip flop 3216 is connected with the output terminal 3214b of second comparer 3214, CP input end 3216b is connected with crystal oscillator 321a, be the signal CLK that CP input end 3216b input crystal oscillator produces, PRN input end 3216c is used for input high level signal VCC, CLRN input end 3216d is used for input high level signal VCC, and Q output terminal 3216e is connected with the clear terminal 3214a of second counter.
Be the structural representation of three frequency division subelement among Fig. 9 as shown in figure 11, three frequency division subelement 321d comprises the 3rd counter 3217, the 3rd comparer 3218 and the 11 d type flip flop 3219.The 3rd counter 3217 is used for the signal of the tenth d type flip flop 3216 outputs is counted, the CP input end 3217b of the 3rd counter 3217 is connected with the Q output terminal 3216e of the tenth d type flip flop 3216, promptly the CP input end of the 3rd counter 3217 is imported the signal (for example, the signal of the Q output terminal of the tenth d type flip flop 3216e generation is CLK1ms) of the Q output terminal 3216e generation of the tenth d type flip flop 3216.The 3rd comparer 3218 is used for the count value of comparison the 3rd counter 3217 and the size of the 3rd preset value.The 11 d type flip flop 3219 is used for the signal lag with 3218 outputs of the 3rd comparer, the D input end 3219a of the 11 d type flip flop 3219 is connected with the output terminal 3218a of the 3rd comparer 3218, CP input end 3219b is connected with crystal oscillator 321a, PRN input end 3219c is used for input high level signal VCC, CLRN input end 3219d is used for input high level signal VCC, the clear terminal 3217a of Q output terminal 3219e and the 3rd counter, second or door except with input end that the power supply starting signal generation unit is connected input end and the input connection of not gate.
The frequency division principle of the second frequency division subelement, three frequency division subelement is identical with the first frequency division subelement, repeats no more.
Be the structural representation of the utility model liquid crystal display drive circuit embodiment four as shown in figure 12, among this embodiment, enabling unit 33 is 54HC245 chips, this chip is the effective chip of low level, promptly this chip enable input end 33a input low level signal the time, this chip operate as normal, when enabling input end 33a input high level signal, this chip is not worked.
Enable characteristic based on this of 54HC245 chip, in structure shown in Figure 3, increased by second not gate 35, the 3rd not gate 36 and Sheffer stroke gate 37.The input end 35a of second not gate 35 is connected with detecting unit 32, output terminal 35b with enable unit 33 and be connected, specifically be to be connected with the input end 33a that enables that enables unit 33.The input end 36a of the 3rd not gate 36 is connected with detecting unit 32.Two input end 37a of Sheffer stroke gate 37 are connected with power supply starting signal generation unit 5 with the output terminal 36b of the 3rd not gate 36 respectively with 37b, and output terminal 37c is connected with backup dc conversion unit 34.
The principle of work of driving circuit as shown in figure 12 is: if detecting unit 32 detects the abnormal output AVDD of initial dc conversion unit 31 signal, VGH signal or VGL signal, detecting unit 32 output low level signals so, this low level signal enables unit 33 and does not work through becoming high level signal after second not gate 35.The low level signal of detecting unit 32 outputs is through being input among the input end 37a of Sheffer stroke gate 37 after the 3rd not gate 36, another input end 37b input power supply starting signal BOOT of Sheffer stroke gate 37, Sheffer stroke gate 37 outputs is exactly the signal of high level like this, backup dc conversion unit 34 is started working, output AVDD signal, VGH signal or VGL signal.
If detecting initial dc conversion unit 31, detecting unit 32 can normally export AVDD signal, VGH signal or VGL signal, detecting unit 32 is exported high level signals so, this high level signal is through becoming low level signal after second not gate 35, enable unit 33 operate as normal, AVDD signal, VGH signal or the VGL signal that initial dc conversion unit 31 generates can be offered gate driver circuit, source electrode drive circuit or gamma electric voltage generation module so enable unit 33.The high level signal of detecting unit 32 outputs is through being input among the input end 37a of Sheffer stroke gate 37 after the 3rd not gate 36, another input end 37b input power supply starting signal BOOT of Sheffer stroke gate 37, Sheffer stroke gate 37 outputs is exactly low level signal like this, and backup dc conversion unit 34 can not be worked.
The liquid crystal display drive circuit that the utility model provides, in dc conversion modules, adopted the backup dc conversion unit to be used as the backup units of initial dc conversion unit, can't normally export under the situation of measured signal in initial dc conversion unit, the backup dc conversion unit also can replace the required signal of each module outside the initial dc conversion unit output LCD processing dc conversion modules, thereby guarantee that LCD can normally show, reduce LCD owing to various signals can't normally be exported the probability of the fault appearance that causes, improved the stability of the driving circuit of LCD.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of programmed instruction, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above embodiment only in order to the explanation the technical solution of the utility model, is not intended to limit; Although the utility model is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (10)
1. a liquid crystal display drive circuit comprises dc conversion modules, it is characterized in that, described dc conversion modules comprises:
Be used to other modules except described dc conversion modules in the described liquid crystal display drive circuit that the initial dc conversion unit of desired signal is provided;
Be used to detect the detecting unit whether described initial dc conversion unit has measured signal output, described detecting unit is connected with described initial dc conversion unit, and described measured signal is any one in other module desired signals except described dc conversion modules in the described liquid crystal display drive circuit;
Being used for detecting described initial dc conversion unit at described detecting unit has under the situation of measured signal output, the signal that described initial dc conversion unit is provided sends to the unit that enables of other modules except described dc conversion modules in the described liquid crystal display drive circuit, describedly enables that other modules except dc conversion modules are connected in unit and described detecting unit, initial dc conversion unit and the described liquid crystal display drive circuit;
Being used for detecting described initial dc conversion unit at described detecting unit does not have under the situation of measured signal output, other modules in described liquid crystal display drive circuit except dc conversion modules provide the backup dc conversion unit of desired signal, and other modules in described backup dc conversion unit and described detecting unit and the described liquid crystal display drive circuit except dc conversion modules are connected.
2. liquid crystal display drive circuit according to claim 1 is characterized in that, also comprises the power supply starting signal generation unit that is used for producing enabling signal behind the power initiation of LCD;
Described detecting unit comprises the clock signal generation unit, first d type flip flop, second d type flip flop, 3d flip-flop and the four d flip-flop that are used for clocking, first or door, second or door and not gate;
Described first or the door two input ends be connected with the power supply starting signal generation unit with described initial dc conversion unit respectively;
The CP input end of described first d type flip flop with described first or the door output terminal be connected, the D input end is used for the input high level signal;
The D input end of described second d type flip flop is connected with the Q output terminal of described first d type flip flop, and the CP input end is connected with described clock signal generation unit;
The D input end of described 3d flip-flop is connected with the Q output terminal of described second d type flip flop, and the CP input end is connected with described clock signal generation unit;
The D input end of described four d flip-flop is connected with the Q output terminal of described 3d flip-flop, and the Q output terminal of described the 4th trigger is connected with standby dc conversion unit with the described unit that enables;
The input end of described not gate is connected with described clock signal generation unit, and output terminal is connected with the CLRN input end of described first d type flip flop;
Described second or the door two input ends be connected with the power supply starting signal generation unit with described clock signal generation unit respectively, output terminal is connected with the CP input end of described four d flip-flop.
3. liquid crystal display drive circuit according to claim 2 is characterized in that, described power supply starting signal generation unit comprises:
Be used for behind the power initiation of LCD, producing the power supply starting signal generation subelement of enabling signal;
Be used for described power supply starting signal is generated the filtering subelement that power supply starting signal that subelement generates carries out filtering, described filtering subelement respectively with described power supply starting signal generate subelement, second or input end of door and first or an input end of door be connected.
4. liquid crystal display drive circuit according to claim 3 is characterized in that, described filtering subelement comprises the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop and the 8th d type flip flop;
The D input end of described the 5th d type flip flop generates subelement with described power supply starting signal and is connected, and the CP input end is connected with described clock signal generation unit;
The D input end of described the 6th d type flip flop is connected with the Q output terminal of described the 5th d type flip flop, and the CP input end is connected with described clock signal generation unit;
The D input end of described the 7th d type flip flop is connected with the Q output terminal of described the 6th d type flip flop, and the CP input end is connected with described clock signal generation unit;
The D input end of described the 8th d type flip flop is connected with the Q output terminal of described the 7th d type flip flop, the CP input end is connected with described clock signal generation unit, the Q output terminal of described the 8th d type flip flop with described second or input end of door and first or an input end of door be connected.
5. according to the described liquid crystal display drive circuit of arbitrary claim among the claim 2-4, it is characterized in that described clock signal generation unit comprises:
Be used to provide the crystal oscillator of the signal of reference frequency, be connected with the CP input end of described second d type flip flop, the CP input end of 3d flip-flop, the CP input end of the 5th d type flip flop, the CP input end of the 6th d type flip flop, the CP input end of the 7th d type flip flop and the CP input end of the 8th d type flip flop;
The frequency that is used for signal that described crystal oscillator is produced is carried out the first frequency division subelement that first frequency division is handled, the described first frequency division subelement and described crystal oscillator, second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
6. liquid crystal display drive circuit according to claim 5 is characterized in that, the described first frequency division subelement comprises:
Be used for first counter that the signal of described crystal oscillator output is counted;
First comparer that is used for the size of the count value of more described first counter and first preset value;
Be used for the 9th d type flip flop with the signal lag of described first comparer output, the D input end of described the 9th d type flip flop is connected with the output terminal of described first comparer, the CP input end is connected with described crystal oscillator, the PRN input end is used for the input high level signal, the CLRN input end is used for the input high level signal, the clear terminal of Q output terminal and described first counter, described second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
7. according to the described liquid crystal display drive circuit of arbitrary claim among the claim 2-4, it is characterized in that described clock signal generation unit comprises:
Be used to provide the crystal oscillator of the signal of reference frequency, be connected with the CP input end of described second d type flip flop, the CP input end of 3d flip-flop, the CP input end of the 5th d type flip flop, the CP input end of the 6th d type flip flop, the CP input end of the 7th d type flip flop and the CP input end of the 8th d type flip flop;
The frequency that is used for signal that described crystal oscillator is produced is carried out the first frequency division subelement that first frequency division is handled, and the described first frequency division subelement is connected with described crystal oscillator;
Be used for the signal that the described first frequency division subelement carries out after first frequency division is handled is carried out the second frequency division subelement that second frequency division is handled, the described second frequency division subelement is connected with the described first frequency division subelement;
Be used for the signal that the described second frequency division subelement carries out after second frequency division is handled is carried out the three frequency division subelement that three frequency division is handled, described three frequency division subelement respectively with the described second frequency division subelement, second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
8. liquid crystal display drive circuit according to claim 7 is characterized in that, the described first frequency division subelement comprises:
Be used for first counter that the signal of described crystal oscillator output is counted;
First comparer that is used for the size of the count value of more described first counter and first preset value;
Be used for the 9th d type flip flop with the signal lag of described first comparer output, the D input end of described the 9th d type flip flop is connected with the output terminal of described first comparer, the CP input end is connected with described crystal oscillator, the PRN input end is used for the input high level signal, the CLRN input end is used for the input high level signal, and the Q output terminal is connected with the clear terminal of described first counter;
The described second frequency division subelement comprises:
Be used for second counter that the signal of described the 9th d type flip flop Q output terminal output is counted;
Second comparer that is used for the size of the count value of more described second counter and second preset value;
Be used for the tenth d type flip flop with the signal lag of described second comparer output, the D input end of described the tenth d type flip flop is connected with the output terminal of described second comparer, the CP input end is connected with described crystal oscillator, the PRN input end is used for the input high level signal, the CLRN input end is used for the input high level signal, and the Q output terminal is connected with the clear terminal of described second counter; Described three frequency division subelement comprises:
Be used for the 3rd counter that the signal of the Q output terminal of described the tenth d type flip flop output is counted;
The 3rd comparer that is used for the size of the count value of more described the 3rd counter and the 3rd preset value;
Be used for the 11 d type flip flop with the signal lag of described the 3rd comparer output, the D input end of described the 11 d type flip flop is connected with the output terminal of described the 3rd comparer, the CP input end is connected with described crystal oscillator, the PRN input end is used for the input high level signal, the CLRN input end is used for the input high level signal, the clear terminal of Q output terminal and described the 3rd counter, described second or door except with input end that the power supply starting signal generation unit is connected input end and the input end connection of not gate.
9. liquid crystal display drive circuit according to claim 6 is characterized in that, the described unit that enables is the 54HC245 chip.
10. liquid crystal display drive circuit according to claim 9 is characterized in that, also comprises: second not gate, the 3rd not gate and Sheffer stroke gate;
The input end of described second not gate is connected with described detecting unit, and output terminal is connected with the described unit that enables;
The input end of described the 3rd not gate is connected with described detecting unit;
Two input ends of described Sheffer stroke gate are connected with the power supply starting signal generation unit with the output terminal of described the 3rd not gate respectively, and output terminal is connected with described backup dc conversion unit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202173799U CN201689650U (en) | 2010-05-27 | 2010-05-27 | Drive circuit for liquid crystal display |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010202173799U CN201689650U (en) | 2010-05-27 | 2010-05-27 | Drive circuit for liquid crystal display |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103279440A (en) * | 2013-05-10 | 2013-09-04 | 北京宇航系统工程研究所 | Bus communication method between single-machine modules |
| CN109448655A (en) * | 2018-12-26 | 2019-03-08 | 惠科股份有限公司 | Filter circuit and display device |
-
2010
- 2010-05-27 CN CN2010202173799U patent/CN201689650U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103279440A (en) * | 2013-05-10 | 2013-09-04 | 北京宇航系统工程研究所 | Bus communication method between single-machine modules |
| CN109448655A (en) * | 2018-12-26 | 2019-03-08 | 惠科股份有限公司 | Filter circuit and display device |
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Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150707 Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150707 |
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Effective date of registration: 20150707 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE Technology Group Co., Ltd. Patentee after: Beijing BOE Photoelectricity Science & Technology Co., Ltd. Address before: 100176 Beijing economic and Technological Development Zone, West Central Road, No. 8 Patentee before: Beijing BOE Photoelectricity Science & Technology Co., Ltd. |
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