CN112857401B - High-precision and high-stability frequency scale circuit - Google Patents
High-precision and high-stability frequency scale circuit Download PDFInfo
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- CN112857401B CN112857401B CN202110186084.2A CN202110186084A CN112857401B CN 112857401 B CN112857401 B CN 112857401B CN 202110186084 A CN202110186084 A CN 202110186084A CN 112857401 B CN112857401 B CN 112857401B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C25/00—Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass
- G01C25/005—Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass initial alignment, calibration or starting-up of inertial devices
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
Abstract
The invention relates to a high-precision and high-stability frequency scale circuit, which solves the technical problems of poor precision, poor stability and large volume, and is characterized in that a controller is connected with an FPGA unit, a high-precision clock source is connected to any frequency divider in the FPGA unit, the any frequency divider in the FPGA unit is connected with a control accumulator and a shaping circuit, and the control accumulator controls any frequency divider through control logic; the shaping circuit is connected with the driving circuit array through the recovery switch unit; the recovery switch unit is controlled by the gating control unit; the controller is used for receiving the control instruction to complete the frequency setting of the output signal and enable the output signal; the FPGA unit is used for receiving a set frequency value, carrying out frequency division processing on the high-precision clock source and outputting a set frequency standard signal.
Description
Technical Field
The invention relates to the field of testing of high-precision I/F conversion circuits of inertial navigation systems, in particular to a high-precision and high-stability frequency scale circuit.
Background
The high-precision and high-stability frequency scale signal is provided in the test of the high-precision I/F conversion circuit of the inertial navigation system. The performance index of the I/F conversion circuit, which is an important component in the inertial navigation system, directly determines the accuracy of the navigation system, so the inertial navigation system must strictly test the performance parameters of the I/F conversion circuit in the development process. The testing of the I/F conversion circuit has become a very important component in the production process of the inertial navigation product.
At present, the testing of high-precision I/F conversion circuits by various research institutes of inertial navigation systems is carried out by adopting foreign signal generators to provide high-precision and high-stability frequency standard signals, and the signal generators are large in size and inconvenient to integrate. The invention provides a high-precision and high-stability frequency scale circuit, which is used for solving the problems.
Disclosure of Invention
The invention aims to solve the technical problems of poor precision, poor stability and large volume in the prior art. The high-precision and high-stability frequency standard circuit has the characteristics of high precision, high stability and small volume.
In order to solve the technical problems, the technical scheme is as follows:
a high accuracy, high stability frequency scale circuit, the high accuracy, high stability frequency scale circuit includes: the device comprises a controller, a high-precision clock source, an FPGA unit, a shaping circuit, a recovery switch unit, a driving circuit array and a gating control unit; the controller is connected with the FPGA unit, the high-precision clock source is connected to any frequency divider in the FPGA unit, any frequency divider in the FPGA unit is connected with the control accumulator and the shaping circuit, and the control accumulator controls any frequency divider through the control logic; the shaping circuit is connected with the driving circuit array through the recovery switch unit; the recovery switch unit is controlled by the gating control unit; the controller is used for receiving the control instruction to complete the frequency setting of the output signal and enable the output signal; the FPGA unit is used for receiving a set frequency value, carrying out frequency division processing on the high-precision clock source and outputting a set frequency standard signal.
In the invention, the output control of the frequency scale signal is realized by adopting a mode that an FPGA processor carries out frequency division on a high-precision clock source. The controller is responsible for receiving the control command that analytic host computer sent, accomplishes the frequency setting to the output signal, enables the output signal. The FPGA processor reads the set frequency value, frequency division processing of the high-precision clock source is completed through the control logic, any frequency divider and the accumulator, the set frequency standard signal is output, the signal is shaped through the shaping circuit, and finally the driving circuit drives the output. Wherein, the shaping circuit and the driving circuit can adopt the existing scheme.
In the above scheme, for optimization, further, the driving circuit array includes a plurality of driving sub-circuits, and each driving sub-circuit is a spare branch; the number of electronic components contained in each driving sub-circuit is N, and N is a positive integer greater than 1; each electronic component is provided with a fault detection unit for detecting a fault, and the gating control unit includes: the gating of the driving sub-circuit is controlled by a recovery switch; the recovery switch is controlled by a recovery switch control signal register; the recovery switch control signal register is connected with a fault counter, and the fault counter is connected with a normal counter; the function checker is connected with an electronic component state register, and the electronic component state register is connected with an electronic component counter and a recovery switch control signal register; the recovery switch control signal register controls the recovery switch to complete the switching of the fault driving sub-circuit, so as to realize fault recovery; the gate control unit further comprises an excitation signal generator; after the fault counter, the normal counter and the electronic component counter are connected with an OR gate together, the OR gate outputs a repair completion signal; the fault counter outputs the fault number and the fault carry of the driving electronic components, the normal counter outputs the normal number and the normal carry of the electronic components, and the electronic component counter outputs the number of the electronic components; the electronic component state diagnosis result is stored in an electronic component state register; the electronic component counter starts to count all the electronic components from the first electronic component in a traversing manner; the function checker calculates the state diagnosis result of the electronic component by receiving the checking information of the electronic component and the response signal fed back by the electronic component fault detection unit and outputs the state diagnosis result to the electronic component state register.
In the optimization scheme, the number, normal number and fault number of each component or core component in the driving sub-circuit are detected regularly, and when the fault number reaches a certain degree, namely the use of the driving sub-circuit can be influenced by testing in advance, fault recovery is started, namely other driving sub-circuits are switched in a gating mode. The normal number and the fault number may refer to the physical number of the components or the number of the fault indexes, and the schemes of the normal number and the fault indexes are the same, and only the detection means are different, but the existing detection method and device can be adopted.
Further, the counter is a synchronous counter with counting, holding, setting and carry output functions.
Furthermore, the input end of the function checker is connected with a detection signal of the fault detection unit; the function checker comprises a comparator, an AND gate, an OR gate, a first D trigger and a second D trigger;
one end of the first D trigger is connected with the AND gate, the other end of the first D trigger is connected with the comparator, the input of the other end of the AND gate is connected with the reset end and the input end of the AND gate connected with the second D trigger, one end of the output of the AND gate is connected with the OR gate, and the other end of the output of the AND gate is connected with the logic 0;
one end of the first D trigger is connected with an AND gate, the other end of the first D trigger is connected with a comparator, the input of the other end of the AND gate is connected with a reset end and the input end of the AND gate connected with the first D trigger, the output end of the AND gate is connected with an OR gate, and the other end of the AND gate is connected with a logic 1;
the input of the comparator is check information; and when the detection result is the same as the verification information, outputting logic 1, otherwise, outputting logic 0.
Further, any frequency divider comprises a control frequency dividing unit, and an even frequency divider, an odd frequency divider, a fractional frequency divider and a fractional frequency divider which are connected with the control frequency dividing unit.
The invention has the beneficial effects that: the method adopts the FPGA processor to carry out frequency division on a high-precision clock source, realizes the output control of frequency scale signals, and has better stability than the prior circuit. The frequency scale circuit mainly comprises a controller, an FPGA processor, a high-precision clock source, a shaping circuit, a driving circuit and the like. The controller is responsible for receiving the control command that analytic host computer sent, accomplishes the frequency setting to the output signal, enables the output signal. The FPGA processor reads the set frequency value, frequency division processing of the high-precision clock source is completed through the control logic, any frequency divider and the accumulator, the set frequency standard signal is output, the signal is shaped through the shaping circuit, and finally the driving circuit drives the output. The frequency scale circuit has the advantages that the output frequency scale can be set randomly, the precision is high, the stability is high, the frequency precision is superior to 1E-6, and the 12-hour stability is superior to 5E-8.
Drawings
The invention is further illustrated with reference to the following figures and examples.
Fig. 1 is a schematic diagram of a high-precision and high-stability frequency scale circuit.
Fig. 2, a schematic diagram of a gating control unit.
Fig. 3, a schematic diagram of a counter.
Fig. 4, a schematic diagram of a function checker.
Fig. 5, an arbitrary divider schematic.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1
This embodiment provides a high accuracy, high stability frequency standard circuit, as shown in fig. 1, the high accuracy, high stability frequency standard circuit includes: the device comprises a controller, a high-precision clock source, an FPGA unit, a shaping circuit, a recovery switch unit, a driving circuit array and a gating control unit; the controller is connected with the FPGA unit, the high-precision clock source is connected to any frequency divider in the FPGA unit, any frequency divider in the FPGA unit is connected with the control accumulator and the shaping circuit, and the control accumulator controls any frequency divider through the control logic; the shaping circuit is connected with the driving circuit array through the recovery switch unit; the recovery switch unit is controlled by the gating control unit; the controller is used for receiving the control instruction to complete the frequency setting of the output signal and enable the output signal; the FPGA unit is used for receiving a set frequency value, carrying out frequency division processing on the high-precision clock source and outputting a set frequency standard signal.
In this embodiment, the output control of the frequency scale signal is realized by performing frequency division on the high-precision clock source by using the FPGA processor. The controller is responsible for receiving the control command that analytic host computer sent, accomplishes the frequency setting to the output signal, enables the output signal. The FPGA processor reads the set frequency value, frequency division processing of the high-precision clock source is completed through the control logic, any frequency divider and the accumulator, the set frequency standard signal is output, the signal is shaped through the shaping circuit, and finally the driving circuit drives the output. Wherein, the shaping circuit and the driving circuit can adopt the existing scheme.
As shown in fig. 2, the driving circuit array includes a plurality of driving sub-circuits, each of which is a backup branch; the number of electronic components contained in each driving sub-circuit is N, and N is a positive integer greater than 1; each electronic component is provided with a fault detection unit for detecting a fault, and the gating control unit includes: the gating of the driving sub-circuit is controlled by a recovery switch; the recovery switch is controlled by a recovery switch control signal register; the recovery switch control signal register is connected with a fault counter, and the fault counter is connected with a normal counter; the function checker is connected with an electronic component state register, and the electronic component state register is connected with an electronic component counter and a recovery switch control signal register; the recovery switch control signal register controls the recovery switch to complete the switching of the fault driving sub-circuit, so as to realize fault recovery; the gate control unit further comprises an excitation signal generator; after the fault counter, the normal counter and the electronic component counter are connected with an OR gate together, the OR gate outputs a repair completion signal; the fault counter outputs the fault number and the fault carry of the driving electronic components, the normal counter outputs the normal number and the normal carry of the electronic components, and the electronic component counter outputs the number of the electronic components; the electronic component state diagnosis result is stored in an electronic component state register; the electronic component counter starts to count all the electronic components from the first electronic component in a traversing manner; the function checker calculates the state diagnosis result of the electronic component by receiving the checking information of the electronic component and the response signal fed back by the electronic component fault detection unit and outputs the state diagnosis result to the electronic component state register.
In the optimization scheme, the number, the normal number and the fault number of each component or core component in the driving sub-circuit are detected at regular time, and when the fault number reaches a certain degree, namely the use of the driving sub-circuit can be influenced by testing in advance, fault recovery is started, namely other driving sub-circuits are switched in a gating mode. The normal number and the fault number may refer to the physical number of the components or the number of the fault indexes, and the schemes of the normal number and the fault numbers are the same, and only different detection means are adopted, but the existing detection method and device can be adopted.
As shown in fig. 3, the counter is a synchronous counter with counting, holding, setting and carry outputting functions.
As shown in fig. 4, the input terminal of the function checker is connected to the detection signal of the fault detection unit;
the function checker comprises a comparator, an AND gate, an OR gate, a first D trigger and a second D trigger;
one end of the first D trigger is connected with the AND gate, the other end of the first D trigger is connected with the comparator, the input of the other end of the AND gate is connected with the reset end and the input end of the AND gate connected with the second D trigger, one end of the output of the AND gate is connected with the OR gate, and the other end of the output of the AND gate is connected with the logic 0;
one end of the first D trigger is connected with the AND gate, the other end of the first D trigger is connected with the comparator, the input of the other end of the AND gate is connected with the reset end and the input end of the AND gate connected with the first D trigger, one end of the output of the AND gate is connected with the OR gate, and the other end of the output of the AND gate is connected with the logic 1;
the input of the comparator is check information; and when the detection result is the same as the verification information, outputting logic 1, otherwise, outputting logic 0.
As shown in fig. 5, any frequency divider includes a control frequency dividing unit, and an even frequency divider, an odd frequency divider, a fractional frequency divider, and a fractional frequency divider connected to the control frequency dividing unit. Integer division when B =00, odd division of duty cycle 50 when B =01, fractional division when B =10, fractional division when B = 11. M, K controls the division factor and duty cycle of the integer division. The fractional division M, N adjusts the integer portion and the fractional portion, respectively. During fractional frequency division, K adjusts the integer part, M and N adjust the denominator and the numerator values, and although the number of preset ports is large, the adjustability is good.
In the embodiment, a mode of frequency division of a high-precision clock source by using an FPGA processor is provided, so that output control of a frequency scale signal is realized, and the stability of the frequency scale signal is superior to that of the existing circuit. The frequency scale circuit mainly comprises a controller, an FPGA processor, a high-precision clock source, a shaping circuit, a driving circuit and the like. The controller is responsible for receiving the control command that analytic host computer sent, accomplishes the frequency setting to the output signal, enables the output signal. The FPGA processor reads the set frequency value, frequency division processing of the high-precision clock source is completed through the control logic, any frequency divider and the accumulator, the set frequency standard signal is output, the signal is shaped through the shaping circuit, and finally the driving circuit drives the output. The frequency scale circuit has the advantages that the output frequency scale can be set randomly, the precision is high, the stability is high, the frequency precision is superior to 1E-6, and the 12-hour stability is superior to 5E-8.
Although the illustrative embodiments of the present invention have been described above to enable those skilled in the art to understand the present invention, the present invention is not limited to the scope of the embodiments, and it is apparent to those skilled in the art that all the inventive concepts using the present invention are protected as long as they can be changed within the spirit and scope of the present invention as defined and defined by the appended claims.
Claims (4)
1. The utility model provides a high accuracy, high stability frequency scale circuit which characterized in that: the high accuracy, high stability frequency scale circuit includes: the device comprises a controller, a high-precision clock source, an FPGA unit, a shaping circuit, a recovery switch unit, a driving circuit array and a gating control unit; the controller is connected with the FPGA unit, the high-precision clock source is connected to any frequency divider in the FPGA unit, any frequency divider in the FPGA unit is connected with the control accumulator and the shaping circuit, and the control accumulator controls any frequency divider through the control logic; the shaping circuit is connected with the driving circuit array through the recovery switch unit; the recovery switch unit is controlled by the gating control unit; the driving circuit array comprises a plurality of driving sub-circuits, and each driving sub-circuit is a standby branch circuit; the number of electronic components contained in each driving sub-circuit is N, and N is a positive integer greater than 1; each electronic component is provided with a fault detection unit for detecting a fault, and the gating control unit includes: the gating of the driving sub-circuit is controlled by a recovery switch; the recovery switch is controlled by a recovery switch control signal register; the recovery switch control signal register is connected with a fault counter, and the fault counter is connected with a normal counter; the function checker is connected with an electronic component state register, and the electronic component state register is connected with an electronic component counter and a recovery switch control signal register; the recovery switch control signal register controls the recovery switch to complete the switching of the fault driving sub-circuit, so as to realize fault recovery; the gate control unit further comprises an excitation signal generator; after the fault counter, the normal counter and the electronic component counter are connected with an OR gate together, the OR gate outputs a repair completion signal; the fault counter outputs the fault number and the fault carry of the driving electronic components, the normal counter outputs the normal number and the normal carry of the electronic components, and the electronic component counter outputs the number of the electronic components; the electronic component state diagnosis result is stored in an electronic component state register; the electronic component counter starts to count all the electronic components from the first electronic component in a traversing way; the function checker calculates the state diagnosis result of the electronic component by receiving the checking information of the electronic component and the response signal fed back by the electronic component fault detection unit and outputs the state diagnosis result to the electronic component state register;
the controller is used for receiving the control instruction to complete the frequency setting of the output signal and enable the output signal;
the FPGA unit is used for receiving a set frequency value, carrying out frequency division processing on the high-precision clock source and outputting a set frequency standard signal.
2. A high accuracy, high stability frequency scale circuit according to claim 1, wherein: the counter is a synchronous counter with counting, maintaining, setting and carry output functions.
3. A high accuracy, high stability frequency scale circuit according to claim 1, wherein: the input end of the function checker is connected with a fault detection unit detection signal;
the function checker comprises a comparator, an AND gate, an OR gate, a first D trigger and a second D trigger;
one end of the first D trigger is connected with the AND gate, the other end of the first D trigger is connected with the comparator, the input of the other end of the AND gate is connected with the reset end and the input end of the AND gate connected with the second D trigger, one end of the output of the AND gate is connected with the OR gate, and the other end of the output of the AND gate is connected with the logic 0;
one end of the first D trigger is connected with the AND gate, the other end of the first D trigger is connected with the comparator, the input of the other end of the AND gate is connected with the reset end and the input end of the AND gate connected with the first D trigger, one end of the output of the AND gate is connected with the OR gate, and the other end of the output of the AND gate is connected with the logic 1;
the input of the comparator is check information; and when the detection result is the same as the verification information, outputting logic 1, otherwise, outputting logic 0.
4. A high accuracy, high stability frequency scale circuit according to claim 1, wherein: the arbitrary frequency divider comprises a control frequency dividing unit, and an even frequency divider, an odd frequency divider, a fractional frequency divider and a fractional frequency divider which are connected with the control frequency dividing unit.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106093567A (en) * | 2016-06-01 | 2016-11-09 | 深圳先进技术研究院 | A kind of high-precision wide frequency-domain frequency measures system and frequency measurement method |
| CN109765828A (en) * | 2019-02-25 | 2019-05-17 | 成都芯进电子有限公司 | A kind of reluctance type sensors chip sequential control circuit and control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI243538B (en) * | 2004-07-30 | 2005-11-11 | Realtek Semiconductor Corp | Apparatus for generating testing signals |
| CN1992529A (en) * | 2005-12-31 | 2007-07-04 | 郑州威科姆电子科技有限公司 | Method for synthesizing high accuracy digital time-frequency standard |
| CN102435842B (en) * | 2011-09-20 | 2014-08-13 | 武汉理工大学 | Device for comparing double-mode frequency scales and measuring frequency stability |
| CN112332845B (en) * | 2020-11-04 | 2023-06-09 | 南京理工大学 | High-precision current frequency conversion circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106093567A (en) * | 2016-06-01 | 2016-11-09 | 深圳先进技术研究院 | A kind of high-precision wide frequency-domain frequency measures system and frequency measurement method |
| CN109765828A (en) * | 2019-02-25 | 2019-05-17 | 成都芯进电子有限公司 | A kind of reluctance type sensors chip sequential control circuit and control method |
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