CN203399082U - Numerical-field clock recovery generating device - Google Patents
Numerical-field clock recovery generating device Download PDFInfo
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- CN203399082U CN203399082U CN201320213805.5U CN201320213805U CN203399082U CN 203399082 U CN203399082 U CN 203399082U CN 201320213805 U CN201320213805 U CN 201320213805U CN 203399082 U CN203399082 U CN 203399082U
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Abstract
The utility model discloses a numerical-field clock recovery generating device. The numerical-field clock recovery generating device comprises an input reference clock sampling unit, a counter unit, a state machine unit and a recovery clock outputting unit. The input reference clock sampling unit conducts sampling on an input reference clock by using a high-frequency calibration clock, obtains a logic level of the current input reference clock, and outputs the logic level to the counter unit. The counter unit conducts counting on the current input reference clock by using the high-frequency calibration clock under the condition that the logic level of the current input reference clock does not change. The state machine unit conducts counting on the high-frequency calibration clock, conducts comparison on a threshold which is determined according to the input reference clock, the high-frequency calibration clock and preset frequency multiplication coefficients at the same time, and outputs control instructions to the recovery clock outputting unit to output a recovery clock.
Description
Technical field
The utility model relates to a kind of recovered clock generating apparatus of numeric field.
Background technology
Stable clock is the precondition of synchronous digital circuit normal operation, produces as required frequency, the satisfactory clock of phase place, is one of object of Clock Design.Usually, can use frequency divider to obtain low-frequency clock from high frequency clock, in order to obtain high frequency clock from low-frequency clock, typically use the analog circuits such as PLL.Tradition is used the method for analog circuitry processes clock to have the shortcomings such as power consumption is high, area is large, not only the R&D cycle long, cost is high, has a big risk, and depends on concrete technology storehouse, is difficult to transplanting.
Utility model content
The utility model provides a kind of clock recovery generating apparatus of numeric field, in order to solve that prior art adopts the method for analog circuitry processes clock and the power consumption that produces is high, area is large, the R&D cycle is long, cost is high, have a big risk and depend on concrete technology storehouse, be difficult to the problem of transplanting.
For solving the problems of the technologies described above, the clock recovery generating apparatus of implementing numeric field of the present utility model comprises input reference clock sampling unit, counter unit, state machine unit and output recovered clock unit, wherein input reference clock sampling unit is sampled to input reference clock with high frequency calibration clock, and obtain the logic level of current input reference clock and export counter unit to, this counting unit is in the situation that the logic level of current input reference clock is constant, utilize high frequency calibration clock to count current input reference clock, and state machine unit is counted high frequency calibration clock, simultaneously with according to input reference clock, high frequency calibration clock and the definite threshold values of predefined Clock Multiplier Factor compare, and export control command to exporting recovered clock unit with output recovered clock.
According to above-mentioned principal character, input reference clock sampling unit receives input reference clock and high frequency calibration clock, it utilizes high frequency calibration clock to sample to input reference clock, obtain the number in corresponding high frequency clock cycle in each input reference clock cycle, and send state machine unit and counter unit to.
According to above-mentioned principal character, this input reference clock sampling unit is used deburring circuit or other circuit for eliminating metastable states, obtain the logic level of current input reference clock, and export the current logic level of input reference clock to counter unit and state machine unit.
According to above-mentioned principal character, counter unit comprises counting unit and judging unit, wherein counting unit is in the situation that the logic level of current input reference clock is constant, continue counting, from 1 to the number in definite corresponding high frequency clock cycle in input reference clock cycle of input reference clock sampling unit, count, and judging unit according to the value output counter sign of counting unit with state of a control machine unit, in the specific implementation, this counter sign is greater than, is less than two kinds of Status Flags.
According to above-mentioned principal character, state machine unit comprises sequence circuit and combinational circuit, sequence circuit is preserved the logic level of the current input reference clock of input reference clock unit output, and combinational circuit carries out logical operation according to the logic level of the control command of the output of current state machine unit, counter sign, current input reference clock, while determining the next clock cycle, export the state of recovered clock.
The clock recovery generating apparatus of numeric field of the present utility model, is only used generic logic hardware to realize to obtain according to configuration faster than input reference clock, and output recovered clock that also can be slower than input reference clock, has simplified hardware configuration.Meanwhile, than conventional analog circuits PLL phase-locked loop, realize and more to economize power consumption, area is also less, particularly all uses Digital Logic java standard library to realize, easily transplant, be easy to design verification, R&D cycle short, there is very high use value effect.
Accompanying drawing explanation
Fig. 1 is for implementing the circuit theory schematic diagram of clock recovery generating apparatus of the present utility model.
Embodiment
Below with reference to accompanying drawing, to implementing the clock recovery generating apparatus of numeric field of the present utility model, be described in further detail.
Referring to Fig. 1, the clock recovery generating apparatus of implementing numeric field of the present utility model comprises input reference clock sampling unit, counter unit, state machine unit and output recovered clock unit.
Input reference clock sampling unit receives input reference clock and high frequency calibration clock, it utilizes high frequency calibration clock to sample to input reference clock, obtain corresponding how many high frequency clock cycles in each input reference clock cycle, be designated as m, and send state machine unit and counter unit to.Wherein this input reference clock sampling unit specifically can be used deburring circuit or other circuit for eliminating metastable states, obtain the logic level of current input reference clock, and export the current logic level of input reference clock to counter unit and state machine unit.
Counter unit receives current logic level and the high frequency calibration clock of input reference clock of input reference clock sampling unit output, wherein counter unit comprises counting unit and judging unit, wherein counting unit is in the situation that the logic level of current input reference clock is constant, continue counting, from 1 to m, count, wherein m derives from input reference clock sampling unit sampling unit, and judging unit according to the value output counter sign of counting unit with state of a control machine unit, in the specific implementation, this counter sign is greater than, be less than two kinds of Status Flags.Whether counter unit is mainly to change by detecting the frequency of input reference clock, thereby the work upper limit of set condition machine makes to export recovered clock along with input reference clock is followed variation, specifically can be with reference to following example.
State machine unit comprises sequence circuit and combinational circuit, sequence circuit is preserved the logic level of the current input reference clock of input reference clock unit output, and combinational circuit according to the control command of the output of current state machine unit (as described later, output is " maintaining " or " upset " control command), the logic level of counter sign, current input reference clock carries out logical operation, determines that the next one exports the state of recovered clock during the clock cycle.If its specifically counter be greater than or equal to the corresponding threshold value of the input reference clock of sampling last time, output signal is to control the upset of output recovered clock; If the currency of counter is less than the corresponding threshold value of the input reference clock of sampling last time, state machine unit is counted high frequency calibration clock, according to input reference clock, high frequency calibration clock and predefined Clock Multiplier Factor, determine a threshold values, thereby " maintaining " still " upset " control command is exported in judgement simultaneously.
Output recovered clock unit is to depend on the control signal of current state machine and export recovered clock.This corresponding clock cycle of output recovered clock can be faster than input reference clock, also can be slower than input reference clock.
Below for example the course of work of above-mentioned each unit is described: in concrete enforcement, for example high frequency calibration clock is 200MHz, input reference clock is 5MHz, need 4 frequencys multiplication (being that Clock Multiplier Factor is 4) just can obtain the output recovered clock of 20MHz: the corresponding clock cycle is respectively 5/200/50ns, so corresponding 40 high frequencies of each input reference clock are calibrated the clock cycle, and corresponding 10 high frequencies calibration clock cycle of each output recovered clock, so the half period of corresponding output recovered clock is 5 high frequency calibration clock cycle, counter unit since 1 to 40 cycle count, and according to above-mentioned high frequency, calibrate clock in state machine unit, input reference clock, Clock Multiplier Factor N determines whether that the threshold values overturning is that 5(is corresponding 5 high frequencies calibration clock cycle), state machine unit counting high frequency calibration clock, in the 5th all after date output " upset " order, the upset of output recovered clock unit controls output recovered clock, experience again 5 high frequency calibration clock cycle, from the 5th to the 10th, to the 10th high frequency calibration clock cycle, state machine unit is exported " upset " order again, controlling output recovered clock overturns again, thereby obtain a complete output recovered clock cycle.From 10 to 15 similar from 1 to 5 processes, the like, after counting down to 40, counter unit can reset into 1, obtain so altogether 4 output recovered clock cycles.
If suppose that again high frequency calibration clock is 200MHz, input reference clock changes to 1MHz, needs 4 frequencys multiplication just can obtain the output recovered clock of 4MHz; The corresponding clock cycle is respectively 5/1000/250ns, corresponding 200 high frequencies calibration clock cycle of each input reference clock, corresponding 50 high frequencies calibration clock cycle of each output recovered clock; The half period of corresponding output recovered clock is 25 high frequency calibration clock cycle.
In actual applications, as long as high frequency calibration clock is enough fast, even input clock frequency dynamic change, output clock also can be followed variation, guarantees proportionate relationship, is similar to analog circuit PLL(freq_in_ref x N=freq_out_gen).This Parameter N is the configuration input parameter to state machine unit, i.e. Clock Multiplier Factor.
In the specific implementation, each above functional unit includes combinational circuit and sequence circuit, and wherein combinational circuit consists of NAND gate, NOR gate and not gate or other gate devices, and sequence circuit consists of shift unit and register, in this prior art, there is description more, no longer describe in detail herein.
Because input reference clock is likely completely asynchronous with high frequency calibration clock, so must first will utilize sampling unit, after synchronous, obtain each " corresponding 40 high frequencies calibration clock cycle of current input reference clock ", the input of bonding state machine unit " 4 frequency multiplication " configuration parameter, known " corresponding 10 high frequencies calibration clock cycle of each output recovered clock ", and the half period of 5 corresponding output of high frequency calibration clock cycle recovered clock, so thereby whether state machine unit determines to make output recovered clock to overturn by the counting high frequency calibration clock cycle.The logic of sampling unit stable output is supplied with counter unit use simultaneously, and counter unit obtains count status, state of a control machine unit.State machine unit is controlled output recovered clock.
The clock recovery generating apparatus of numeric field of the present utility model, is only used generic logic hardware to realize to obtain according to configuration faster than input reference clock, and output recovered clock that also can be slower than input reference clock, has simplified hardware configuration.Meanwhile, than conventional analog circuits PLL phase-locked loop, realize and more to economize power consumption, area is also less, particularly all uses Digital Logic java standard library to realize, easily transplant, be easy to design verification, R&D cycle short, there is very high use value effect.
Claims (4)
1. the clock recovery generating apparatus of a numeric field, comprise input reference clock sampling unit, counter unit, state machine unit and output recovered clock unit, wherein input reference clock sampling unit is sampled to input reference clock with high frequency calibration clock, and obtain the logic level of current input reference clock and export counter unit to, this counting unit is in the situation that the logic level of current input reference clock is constant, utilize high frequency calibration clock to count current input reference clock, and state machine unit is counted high frequency calibration clock, simultaneously with according to input reference clock, high frequency calibration clock and the definite threshold values of predefined Clock Multiplier Factor compare, and export control command to exporting recovered clock unit with output recovered clock.
2. the clock recovery generating apparatus of numeric field as claimed in claim 1, it is characterized in that: this input reference clock sampling unit is used deburring circuit for eliminating metastable state, obtain the logic level of current input reference clock, and export the current logic level of input reference clock to counter unit and state machine unit.
3. the clock recovery generating apparatus of numeric field as claimed in claim 1, it is characterized in that: counter unit comprises counting unit and judging unit, wherein counting unit is in the situation that the logic level of current input reference clock is constant, continue counting, from 1 to the number in definite corresponding high frequency clock cycle in input reference clock cycle of input reference clock sampling unit, count, and judging unit according to the value output counter sign of counting unit with state of a control machine unit, in the specific implementation, this counter sign is greater than, is less than two kinds of Status Flags.
4. the clock recovery generating apparatus of numeric field as claimed in claim 1, it is characterized in that: state machine unit comprises sequence circuit and combinational circuit, sequence circuit is preserved the logic level of the current input reference clock of input reference clock unit output, and combinational circuit carries out logical operation according to the logic level of the control command of the output of current state machine unit, counter sign, current input reference clock, while determining the next clock cycle, export the state of recovered clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320213805.5U CN203399082U (en) | 2013-04-24 | 2013-04-24 | Numerical-field clock recovery generating device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320213805.5U CN203399082U (en) | 2013-04-24 | 2013-04-24 | Numerical-field clock recovery generating device |
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| CN203399082U true CN203399082U (en) | 2014-01-15 |
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| CN201320213805.5U Expired - Lifetime CN203399082U (en) | 2013-04-24 | 2013-04-24 | Numerical-field clock recovery generating device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219984A (en) * | 2013-04-24 | 2013-07-24 | 上海华力创通半导体有限公司 | Numerical-field clock recovery generating device |
| CN104639042A (en) * | 2014-12-24 | 2015-05-20 | 聚辰半导体(上海)有限公司 | Low-power-consumption adjustable frequency multiplier |
-
2013
- 2013-04-24 CN CN201320213805.5U patent/CN203399082U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103219984A (en) * | 2013-04-24 | 2013-07-24 | 上海华力创通半导体有限公司 | Numerical-field clock recovery generating device |
| CN103219984B (en) * | 2013-04-24 | 2016-12-07 | 上海华力创通半导体有限公司 | The clock recovery generating means of numeric field |
| CN104639042A (en) * | 2014-12-24 | 2015-05-20 | 聚辰半导体(上海)有限公司 | Low-power-consumption adjustable frequency multiplier |
| CN104639042B (en) * | 2014-12-24 | 2017-11-17 | 聚辰半导体(上海)有限公司 | Low-power consumption is adjustable frequency multiplier |
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| C14 | Grant of patent or utility model | ||
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| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 201702, Qingpu District, Shanghai, Shanghai Qing Ping highway 1362, 1, 1, C District, room 133 Patentee after: SHANGHAI HWACHIP SEMICONDUCTOR CO.,LTD. Address before: 4, building 3, building 88, 201203 Darwin Road, Shanghai, Pudong New Area Patentee before: SHANGHAI HWACHIP SEMICONDUCTOR CO.,LTD. |
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| TR01 | Transfer of patent right |
Effective date of registration: 20211122 Address after: 100193 room 118, 1f, building B 18, yard 8, Dongbeiwang West Road, Haidian District, Beijing Patentee after: Beijing Huali Zhifei Technology Co.,Ltd. Address before: 201702 room 133, Zone C, floor 1, building 1, No. 1362, Huqingping highway, Qingpu District, Shanghai Patentee before: SHANGHAI HWACHIP SEMICONDUCTOR CO.,LTD. |
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| CX01 | Expiry of patent term |
Granted publication date: 20140115 |
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| CX01 | Expiry of patent term |