CN104639042B - Low-power consumption is adjustable frequency multiplier - Google Patents
Low-power consumption is adjustable frequency multiplier Download PDFInfo
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- CN104639042B CN104639042B CN201410812616.9A CN201410812616A CN104639042B CN 104639042 B CN104639042 B CN 104639042B CN 201410812616 A CN201410812616 A CN 201410812616A CN 104639042 B CN104639042 B CN 104639042B
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Abstract
The present invention discloses a kind of adjustable frequency multiplier of low-power consumption, comprising：Clock circuit, produce and export clock signal and sampled clock signal；Adjustment circuit is sampled, it receives external reference clock and the sampled clock signal of clock circuit output, and reference clock is sampled by sampled clock signal, and the number of high level, is exported as sampled signal in sampling gained reference clock；Clock stable decision circuitry, it receives the sampled signal of sampling adjustment circuit output, the number of output sampling clock control signal regulation sampled reference clock high level, also exports enable signal control sampling adjustment circuit opening and closing.Present invention adds sampling adjustment circuit and clock stable decision circuitry, after clock stable, the sampling adjustment circuit part of the inside can be completely turned off, no longer work, so as to reach stable performance and reduce the requirement of power consumption, and the relatively easy complexity easily realized, reduce design of this circuit.
Description
Technical field
The present invention relates to a kind of frequency multiplier circuit, and in particular to a kind of adjustable frequency multiplier of low-power consumption.
Background technology
With the fast development of integrated circuit, the application of digital-analog mix-mode chip is also more and more extensive, and clock is this kind of chip
Essential part.
Simultaneously as the raising of arithmetic speed requirement, the requirement also more and more higher, and its stability to clock frequency
It is its essential requirement.
The frequency multiplier circuit used at present uses phaselocked loop to do, but phase-locked loop circuit is more complicated, does in the presence of certain
Difficulty, and power consumption can also increase.
The content of the invention
The present invention provides a kind of adjustable frequency multiplier of low-power consumption, realizes stable performance and reduces the requirement of power consumption, while relatively
It is simple easily to realize, reduce the complexity of design.
To achieve the above object, the present invention provides a kind of adjustable frequency multiplier of low-power consumption, is characterized in, the frequency multiplier includes：
Clock circuit, it produces and exports clock signal and sampled clock signal；Clock signal is the adjustable frequency multiplication of low-power consumption
The clock output of device；
Adjustment circuit is sampled, it receives external reference clock and the sampled clock signal of clock circuit output, by adopting
Sample clock signal is sampled to reference clock, and the number of high level, is exported as sampled signal in sampling gained reference clock；
Clock stable decision circuitry, it receives the sampled signal of sampling adjustment circuit output, output sampling clock control letter
Number regulation sampled reference clock high level number, also export enable signal control sampling adjustment circuit opening and closing；
The number that high level is obtained when clock stable decision circuitry judgment standard clock sampling is more than default number threshold value,
Clock stable decision circuitry control clock circuit reduces the output frequency of sampled clock signal, reduces sampled clock signal sampling base
The number of punctual clock high level；Or obtained when clock stable decision circuitry judgment standard clock sampling high level number it is small
In default number threshold value, the output frequency of clock stable decision circuitry control clock circuit increase sampled clock signal, increase
The number of sampled clock signal sampled reference clock high level；
The number that high level is obtained when sampled reference clock is equal to default number threshold value, clock circuit stable oscillation stationary vibration output
Clock signal, and the enable signal of clock stable decision circuitry output high level, the clock input of driving sampling adjustment circuit
High level is fixed as, closes sampling adjustment circuit.
Above-mentioned clock circuit includes：
Current control oscillator, it receives initial impressed current source, produces and export the first clock signal；
Frequency-halving circuit, its inlet circuit connect the output end of current control oscillator, receive the first clock signal, defeated
Go out two divided-frequency clock signal；The two divided-frequency clock signal exports as the clock of the adjustable frequency multiplier of low-power consumption；
Circular shift register, it receives two divided-frequency clock signal, exports sampled clock signal.
The above-mentioned adjustable frequency multiplier of low-power consumption also includes：
First OR circuit, it is electrically connected between frequency-halving circuit and circular shift register；First OR circuit
Input receives the two divided-frequency clock signal of frequency-halving circuit output and the enable signal of clock stable decision circuitry output, or fortune
Second clock is exported after calculation to circular shift register, circular shift register is using second clock as inputting, when output samples
Clock signal is to sampling adjustment circuit；
Second OR circuit, its input receive reference clock and the enable signal of clock stable decision circuitry output, or
The 3rd clock is exported after computing to sampling adjustment circuit；
When the adjustable frequency multiplier stable oscillation stationary vibration output clock signal of low-power consumption, the enable signal output of clock stable decision circuitry
High level, drive second clock and the 3rd clock to be fixed as high level, close sampling adjustment circuit.
Above-mentioned clock circuit also includes：
Rising edge sample circuit, its input receive the 3rd clock, and clock end receives second clock, rising edge sample circuit
In second clock rising edge to the 3rd clock sampling, rising edge sampled signal is exported；
Trailing edge sample circuit, its input receive the 3rd clock, and clock end receives second clock, trailing edge sample circuit
In second clock trailing edge to the 3rd clock sampling, trailing edge sampled signal is exported.
Above-mentioned clock circuit also includes：
Rising edge sample circuit, its input receive reference clock, and clock end receives two divided-frequency clock signal, and rising edge is adopted
Sample circuit samples in two divided-frequency rising edge clock signal to reference clock, exports rising edge sampled signal；
Trailing edge sample circuit, its input receive reference clock, and clock end receives two divided-frequency clock signal, and trailing edge is adopted
Sample circuit samples in two divided-frequency clock signal trailing edge to reference clock, exports trailing edge sampled signal.
Above-mentioned sampling adjustment circuit includes：
3rd OR circuit, its input receive rising edge sampled signal, trailing edge sampled signal and the 3rd clock, or defeated
Enter end and receive output end output reset signal after rising edge sampled signal, trailing edge sampled signal and reference clock, or computing；
Sample circuit, it receives the 3rd clock, reset signal and sampled clock signal, or receives reference clock, resets letter
Number and sampled clock signal；Sample circuit exports sampled signal after being sampled to the high level of reference clock；
Latch cicuit, it receives the sampled signal of sample circuit output, and the 3rd clock or reference clock by reverse
Caused reverse clock, the complete sampled signal of latch circuit latches sample circuit output, and export adopting by latch
Sample signal.
If above-mentioned sample circuit includes main line rising edge d type flip flop, when the D ends per road rising edge d type flip flop receive the 3rd
Clock or reference clock, clock end receive sampled clock signal, reset end and receive reset signal, output end output sampled signal.
If above-mentioned latch cicuit includes main line rising edge d type flip flop, the D ends per road rising edge d type flip flop receive sampling electricity
The sampled signal of road output, it is defeated by reversely caused reverse clock, output end that clock end receives the 3rd clock or reference clock
Go out the sampled signal by latch.
Above-mentioned clock stable decision circuitry includes：
Voltage-controlled current source, its circuit of output terminal connection clock circuit, the clock signal of control clock circuit output and sampling
The frequency size of clock signal；
Adder, it receives the sampled signal of sampling adjustment circuit output, the number of output reference clock high level；
First logic circuit, it receives the number of the reference clock high level of adder output；When reference clock samples
Number to high level is more than default number threshold value, and the first logic circuit control voltage-controlled current source reduces clock signal and sampling
The output frequency of clock signal；The number for sampling to obtain high level when reference clock is less than default number threshold value, the first logic
The output frequency of circuit control voltage-controlled current source increase clock signal and sampled clock signal；When reference clock samples to obtain high electricity
Flat number is equal to default number threshold value, and the first logic circuit control voltage-controlled current source keeps clock signal and sampling clock letter
Number output frequency it is constant.
Above-mentioned clock stable decision circuitry includes：
Voltage-controlled current source, its circuit of output terminal connection clock circuit, the clock signal of control clock circuit output and sampling
The frequency size of clock signal；
Adder, it receives the sampled signal of sampling adjustment circuit output, the number of output reference clock high level；
First logic circuit, it receives the number of the reference clock high level of adder output；When reference clock samples
Number to high level is more than default number threshold value, and the first logic circuit control voltage-controlled current source reduces clock signal and sampling
The output frequency of clock signal, the number for sampling to obtain high level when reference clock are less than default number threshold value, the first logic
The output frequency of circuit control voltage-controlled current source increase clock signal and sampled clock signal；When reference clock samples to obtain high electricity
Flat number is equal to default number threshold value, and the first logic circuit control voltage-controlled current source keeps clock signal and sampling clock letter
Number output frequency it is constant；
Second logic circuit, its inlet circuit connect the first logic circuit, and circuit of output terminal connects the first OR circuit
With the second OR circuit, the number for sampling to obtain high level when reference clock is equal to default number threshold value, the second logic circuit
Statistics reference clock samples to obtain number of the number equal to default number threshold value of high level, when the number of statistics reaches default
Frequency threshold value, the second logic circuit is the enable signal for exporting high level to the first OR circuit and the second OR circuit.
The adjustable frequency multiplier of low-power consumption of the present invention is compared with the clock circuit of prior art, the advantage is that, the present invention adds
Sampling adjustment circuit and clock stable decision circuitry, after clock stable, the sampling adjustment circuit part of the inside can be with complete
It is fully closed fall, no longer work, so as to reach stable performance and reduce power consumption requirement, and this circuit it is relatively easy easily realize, reduce
The complexity of design.
Brief description of the drawings
Fig. 1 is the circuit theory diagrams of the adjustable frequency multiplier of low-power consumption of the present invention；
Fig. 2 is the specific oscillogram of circular shift register；
Fig. 3 is the example waveform figure that sampled reference clock is realized in sampling adjustment circuit.
Embodiment
Below in conjunction with accompanying drawing, specific embodiment of the invention is further illustrated.
The invention discloses a kind of adjustable frequency multiplier of low-power consumption, the low-power consumption is adjustable, and frequency multiplier includes：Clock circuit, sampling
Adjustment circuit and clock stable decision circuitry.
Clock circuit is used to produce and export clock signal and sampled clock signal；Clock signal is the adjustable frequency multiplication of low-power consumption
The clock output of device.
Sampling adjustment circuit is used for the sampled clock signal for receiving external reference clock and clock circuit output, by adopting
Sample clock signal is sampled to reference clock, and the number of high level, is exported as sampled signal in sampling gained reference clock；
Clock stable decision circuitry is used for the sampled signal for receiving sampling adjustment circuit output, output sampling clock control letter
Number regulation sampled reference clock high level number, also export enable signal control sampling adjustment circuit opening and closing；
The number that high level is obtained when clock stable decision circuitry judgment standard clock sampling is more than default number threshold value,
Clock stable decision circuitry control clock circuit reduces the output frequency of sampled clock signal, reduces sampled clock signal sampling base
The number of punctual clock high level；Or obtained when clock stable decision circuitry judgment standard clock sampling high level number it is small
In default number threshold value, the output frequency of clock stable decision circuitry control clock circuit increase sampled clock signal, increase
The number of sampled clock signal sampled reference clock high level；
The number that high level is obtained when sampled reference clock is equal to default number threshold value, clock circuit stable oscillation stationary vibration output
Clock signal, and the enable signal of clock stable decision circuitry output high level, the clock input of driving sampling adjustment circuit
High level is fixed as, closes sampling adjustment circuit.
As shown in figure 1, be a kind of embodiment of the adjustable frequency multiplier of low-power consumption, it can be with clock multiplier, when frequency multiplication is to benchmark
2m times of clock, m round numbers and m>1, and sampling adjustment circuit and clock stable decision circuitry are added, after clock stable,
Sampling adjustment circuit part can be completely turned off, and no longer be worked, and reached stable performance and reduced the requirement of power consumption, and this circuit phase
Easily realized to simple, reduce the complexity of design.
Wherein, m is exactly the high level number threshold value that default reference clock samples to obtain.
When the high level number that reference clock samples to obtain is equal to default threshold value m, then illustrate the height electricity of reference clock
The flat time is equal to m times of sampling clock cycle, then and the cycle of reference clock is equal to 2 times of reference clock high level time,
That is 2m times of the cycle of reference clock equal to sampling clock cycle, then the frequency of sampling clock is exactly the 2m of reference clock frequency
Times, so the frequency of clock signal is equal to sample clock frequency, i.e. the frequency of clock signal is also 2m times of reference clock frequency,
Whole frequency multiplier circuit is exactly to realize this 2m times.
Adjustable magnification refers to that circuit designers can be gone to set this m value, that is, set reference clock according to the requirement of oneself
Sampling obtains the preset value of high level number, and whole circuit only needs to change some parameters relevant with m in circuit, such as samples electricity
The number, the digit of circular shift register etc. of rising edge d type flip flop in road and latch cicuit, i.e. m values are to rely on circuit to need
Setting is asked, obtained frequency multiplication multiple is exactly 2m times of reference clock frequency.
The low-power consumption is adjustable, and frequency multiplier includes：Clock circuit, sampling adjustment circuit and clock stable decision circuitry.
Clock circuit includes：Current control oscillator, frequency-halving circuit, circular shift register, rising edge sample circuit,
Trailing edge sample circuit.
The first clock signal clk1 all the way is produced by current control oscillator first, this current control oscillator accesses one
Initial impressed current source, to produce an initial clock（That is the first clock signal clk1）.
Frequency-halving circuit inlet circuit connects the output end of current control oscillator, and the output of frequency-halving circuit is connected to
Circular shift register.Frequency-halving circuit receives the first clock signal clk1, and two divided-frequency is carried out to the first clock signal clk1, the
One clock signal clk1 can obtain two divided-frequency clock signal clk2 after two divided-frequency, in order to obtain dutycycle as 50%
Clock, so may insure followed by sampling calculate accuracy.Two divided-frequency clock signal clk2 can as low-power consumption
Adjust the clock output OUT of frequency multiplier.
The adjustable frequency multiplier of low-power consumption disclosed by the invention also includes first OR circuit 1, first OR circuit 1
It is electrically connected between frequency-halving circuit and circular shift register.It is defeated that the input of first OR circuit 1 receives frequency-halving circuit
The enable signal E of two divided-frequency clock signal clk2 and clock stable the decision circuitry output gone out, second is exported after progress or computing
Clock clk2a is to circular shift register.
The adjustable frequency multiplier of low-power consumption disclosed by the invention also includes second OR circuit 2, second OR circuit 2
Input receives the enable signal E of reference clock refclk and clock stable decision circuitry output, carry out or computing after export the
Three clock refclka are to sampling adjustment circuit.
Above-mentioned two divided-frequency clock signal clk2 and enable signal E is carried out or computing obtains second clock clk2a, and benchmark
Clock refclk and enable signal E is carried out or computing obtains the 3rd clock refclka, then is respectively transmitted to next stage.So do
Purpose be to ensure caused by the adjustable frequency multiplier of low-power consumption that final output clock OUT is stable, while also reduce power consumption, that is, work as
Circuit reach it is anticipated that times yupin effect and can stablize after, enable signal E will become high level, two divided-frequency clock signal
The second clock clk2a obtained after clk2 and enable signal E or computing, and reference clock refclk and enable signal E or computing
The 3rd clock refclka obtained afterwards, will become high level, the sampling tune with second clock clk2a as clock below
The clock of whole circuit all keeps a fixed level, i.e., this fractional-sample adjustment circuit is stopped, and so samples adjustment circuit
It would not fluctuate, while be cooperated with the 3rd clock refclka with similar functions（Following 3rd clock refclka's
Concrete function）, to ensure the stable effect of the adjustable frequency multiplier circuit of whole low-power consumption, simultaneously because without clock, sampling adjustment
Circuit is stopped, and low-power consumption is adjustable, and the whole circuit power consumption of frequency multiplier will substantially reduce.Enable signal E signals are reset originally
（reset）When be low level, so just start when do not interfere with the adjustable frequency multiplier circuit normal work of low-power consumption.
As shown in Fig. 2 being the specific oscillogram of circular shift register, the circular shift register is that a rising edge moves
One circular shift register of position, circular shift register is using second clock clk2a as input, if during the sampling of output main line
Clock signal is to sampling adjustment circuit.The series of this circular shift register is to determine that multiple is set as by the multiple of frequency multiplication
2m times, then series is exactly m+2 levels.Therefore sampled clock signal specifically includes in the present embodiment：Q1、Q2、……、Qm、Qm+1、Qm+
2, the reason for circular shift register takes m+2 here, illustrates in following sampling adjustment circuits.This m+2 sampling clock letter
An input clock cycle is differed number successively, input clock cycle is second clock clk2a cycle T 2 herein, and each
The cycle of sampled clock signal is T2*（m+2）.
Rising edge sample circuit uses a rising edge d type flip flop, and its input receives the 3rd clock refclka, clock
End receives second clock clk2a, and rising edge sample circuit is used in second clock clk2a rising edges to the 3rd clock refclka
Sampling, output rising edge sampled signal Qup.
Trailing edge sample circuit uses a trailing edge d type flip flop, and its input receives the 3rd clock refclka, clock
End receives second clock clk2a, and trailing edge sample circuit is used for the clk2a under second clock and dropped along to the 3rd clock refclka
Sampling, output trailing edge sampled signal Qdown.
Here, second clock clk2a is by above-mentioned two d type flip flop（Rising edge sample circuit, trailing edge sample circuit）When
Make clock access, to be sampled to the 3rd clock refclka, due to two d type flip flops be respectively rising edge d type flip flop and
Trailing edge d type flip flop, the output signal after sampling are rising edge sampled signal Qup and trailing edge sampled signal Qdown respectively.
Here rising edge sample circuit can also be directly accessed reference clock refclk and two divided-frequency with trailing edge sample circuit
Clock signal clk2, it is specially：
Rising edge sample circuit uses a rising edge d type flip flop, and its input receives reference clock refclk, clock end
Two divided-frequency clock signal clk2 is received, rising edge sample circuit is in two divided-frequency clock signal clk2 rising edges to reference clock
Refclk is sampled, output rising edge sampled signal Qup.
Trailing edge sample circuit uses a trailing edge d type flip flop, and its input receives reference clock refclk, clock end
Two divided-frequency clock signal clk2 is received, trailing edge sample circuit is in two divided-frequency clock signal clk2 trailing edges to reference clock
Refclk is sampled, output trailing edge sampled signal Qdown.
In the present embodiment, enable signal E is eliminated so that the adjustable frequency multiplier of low-power consumption in the embodiment can be realized defeated
Go out the function of stabilizing clock, but can not be adopted by the clock of enable signal E fixed sample adjustment circuits after realizing clock stable
The function that sample adjustment circuit is stopped.
As shown in figure 1, sampling adjustment circuit includes：3rd OR circuit 3, circuit connect the 3rd OR circuit 3 and exported
The sample circuit at end connects the latch cicuit of sample circuit output end with circuit.
When the input of 3rd OR circuit 3 receives rising edge sampled signal Qup, trailing edge sampled signal Qdown and the 3rd
Clock refclka, or input receive rising edge sampled signal Qup, trailing edge sampled signal Qdown and reference clock refclk,
Or output end output reset signal reseta after computing.
Sample circuit is used to receive the 3rd clock refclka, reset signal reset and sampled clock signal, or receives base
Punctual clock refclk, reset signal reset and sampled clock signal.Sample circuit is carried out to the number of the high level of reference clock
Sampled signal is exported after sampling.
Latch cicuit is used for the sampled signal for receiving sample circuit output, and the 3rd clock refclka or reference clock
Refclk is by reversely caused reverse clock, the complete sampled signal that the latch circuit latches sample circuit exports, and defeated
Go out the sampled signal by latch.
In specific embodiment, the input of the 3rd OR circuit 3 receives reference clock refclk and enable signal E or computing
The 3rd clock refclka, rising edge sampled signal Qup, the trailing edge sampled signal Qdown obtained afterwards.3rd clock refclka
With rising edge sampled signal Qup, trailing edge sampled signal Qdown three progress or computing, reference clock refclk and enabled letter
Number E or purpose of computing is carried out with above-mentioned two divided-frequency clock signal clk2 and enable signal E or computing obtains second clock clk2a
Function phase it is same, i.e., after circuit stability reaches effect, enable signal E becomes high level, reference clock refclk and enable signal E
Or the 3rd clock refclka after computing becomes high level, make the clock circuit relevant with this 3rd clock refclka clock
Turn off, to reach the effect for reducing power consumption and circuit stability.
3rd clock refclka, rising edge sampled signal Qup, trailing edge sampled signal Qdown three pass through the 3rd OR gate
The signal obtained after circuit 3 or computing samples the sample circuit of adjustment circuit as the RESET signal of following one-level sample circuit
It is that low level is reset（reset）, and after reset, the output signal of sample circuit is low level, so once the 3rd clock
Refclka becomes high level, and sample circuit begins to sample, only after the 3rd clock refclka becomes low level and by
When two clock clk2a rising edges and trailing edge all sample low level, for this sample circuit just by reset, output signal is low
Level, the purpose that this reset signal is so set are to be latched into complete sampling to be advantageous to the latch cicuit of next stage
Signal, it can specifically be explained in latch cicuit.
Here due to the 3rd clock refclka, become after low level will be by second clock clk2a rising edges and trailing edge all
Low level is sampled, so second clock clk2a frequency must be greater than 2 times of the 3rd clock refclka frequency, so as to
It is required that two divided-frequency clock signal clk2 frequency must be greater than 2 times of reference clock refclk frequency, i.e. the first clock letter
Number clk1 frequency is greater than 4 times of reference clock refclk frequencies.
This one-level sample circuit m+2 rising edge d type flip flop it can be seen in fig. 1 that be made up of, sampled clock signal
It is Q1, Q2 ... ..., Qm, Qm+1, Qm+2 respectively, is that the 3rd clock refclka high level is sampled, what is adopted
High level is recorded, it is anticipated that high level be m high level occur, if the obtained high level number of sampling reaches pre-
If value m, then illustrating the frequency of clock signal, frequency multiplication is to 2m times of reference clock, so employing m+2 in this sample circuit
Individual rising edge d type flip flop, two rising edge d type flip flops are had more to guarantee to fully achieve our expection.So in order to true
The integrality of whole computing is protected, the series value of above-mentioned circular shift register is m+2.
As shown in figure 3, it is the example waveform figure that sampling circuit samples are realized, in this figure, m values are m=5.
The sampled signal that sampling circuit samples obtain enters the latch cicuit of next stage, and this one-level latch cicuit is the 3rd
Clock refclka trailing edge is latched, due to believe in the sampling that this grade of latch cicuit obtains to upper level sample circuit
After number latching, upper level sample circuit could reset reset, so the replacement reset signals of upper level sample circuit are by the
The signal obtained after three clock refclka, rising edge sampled signal Qup, trailing edge sampled signal Qdown three or computing, make
For the reset signals of sample circuit, to ensure that the sampled signal can completely sampled is arrived by the latch circuit latches of next stage.
Latch cicuit is also to be made up of m+2 rising edge d type flip flop, and the clock of latch cicuit is that the 3rd clock refclka passes through one-level
The signal obtained after phase inverter, so latch cicuit is latched in the 3rd clock refclka trailing edge.
As shown in figure 1, clock stable decision circuitry includes adder；Circuit connects the first logic of adder output
Circuit LG1；Circuit connects the second logic circuit LG2 and D/A converting circuit DAC of the first logic circuit LG1 output ends, circuit
The voltage-controlled current source of D/A converting circuit DAC output ends is connected, voltage-controlled current source circuit of output terminal is connected to current controlled oscillator
Device.Second logic circuit LG2 exports enable signal E respectively to the first OR circuit 1 and the input of the second OR circuit 2.
Voltage-controlled current source circuit of output terminal connects clock circuit, for controlling clock signal and the sampling of clock circuit output
The frequency size of clock signal.
Adder is used for the sampled signal for receiving sampling adjustment circuit output, the number of output reference clock high level.
First logic circuit is used for the number for receiving the reference clock high level of adder output；When reference clock samples
Number to high level is more than default number threshold value, and the first logic circuit control voltage-controlled current source reduces clock signal and sampling
The output frequency of clock signal, the number for sampling to obtain high level when reference clock are less than default number threshold value, the first logic
The output frequency of circuit control voltage-controlled current source increase clock signal and sampled clock signal；When reference clock samples to obtain high electricity
Flat number is equal to default number threshold value, and the first logic circuit control voltage-controlled current source keeps clock signal and sampling clock letter
Number output frequency it is constant；
Second logic circuit is used for inlet circuit and connects the first logic circuit, and circuit of output terminal connects the first OR circuit
With the second OR circuit, the number for sampling to obtain high level when reference clock is equal to default number threshold value, the second logic circuit
Statistics reference clock samples to obtain number of the number equal to default number threshold value of high level, when the number of statistics reaches default
Frequency threshold value, the second logic circuit is the enable signal for exporting high level to the first OR circuit and the second OR circuit.
In specific embodiment, the output signal after latch circuit latches can be sent to adder, adder
Output is D1, D2 ... ..., Dm, the number of the high level in Dm+1, Dm+2.
The logic function that the output of adder can be connected to the first logic circuit LG1 input X, LG1 is as follows：During reset,
Output end B is equal to 0, and output end Y is optional, works as X<During m, Y value adds 1, works as X>During m, Y value subtracts 1, and as X=m, Y value keeps constant
And B values plus 1.During reset, Y value can determine according to reference clock refclk frequency and m value, that is, work as reference clock
When refclk frequency and bigger m value, Y value is bigger.The purpose for the arrangement is that whole circuit is set to reach us faster
Be expected and settle out, shorten adjustment time.
First logic circuit LG1 output end Y be linked into D/A converting circuit DAC produce a stable voltage, first
The output Y of logic circuit is data signal, and D/A converting circuit DAC functions are exactly that this data signal is converted into analog voltage
Value, analog voltage could control voltage-controlled current source to change the frequency of clock signal.
D/A converting circuit DAC is the increase with input data values, D/A converting circuit DAC output voltage value also with
Increase, D/A converting circuit DAC output are connected to the input of voltage-controlled current source, and this voltage-controlled current source is that input voltage is higher,
Output current value is bigger, and output current is sent to the input electricity of current control oscillator after being added with additional initial current source
End is flowed, the input current of current control oscillator is bigger, and oscillator frequency will be higher, and the output of oscillator then can be by two points
Frequency is sampled again carries out whole loop adjustment, and two divided-frequency clock signal clk2 is the output end OUT of whole frequency multiplier circuit.
The logic function that first logic circuit LG1 output B is linked into the second logic circuit LG2 input C, LG2 is：
Output end E is low level during reset, during work, as input C<When 10, E is low level, as C=10 or C>When 10, E is high electricity
It is flat.
Second logic circuit LG2 function is exactly：When circuit stability, i.e., the 3rd clock refclka high level is sampled
The number arrived is m values, and when ten extraction carry out m values, enable signal E will become high level, make entirely to sample adjustment circuit
Second clock clk2a and the 3rd refclka all become fixed level, i.e., entirely sampling adjustment circuit is stopped, whole times
Frequency circuit is also by steady operation.
To sum up, the function of the adjustable frequency multiplier circuit of low-power consumption of the present invention is exactly that fast the first clock caused by oscillator is believed
Two divided-frequency clock signal clk2 after number clk1 frequency dividing goes to sample slow reference clock refclk, if sampled reference clock
The high level number that refclk high level obtains is less than（It is more than）Expected m values, the i.e. frequency of oscillator are less than（It is more than）It is expected that
During value, DAC（Digital-to-analogue conversion）Input data values will increase（Reduce）, output voltage values can also increase（Reduce）, then pressure
The output current of control current source can also increase（Reduce）, the output frequency of current control oscillator can also increase（Reduce）So as to increase
Greatly（Reduce）Two divided-frequency clock signal clk2, so circulation is carried out always, until second clock clk2a is to the 3rd clock
The number that refclka high level samples to obtain is equal to m values, and has ten times and adopted then, illustrates that circuit has tended towards stability, at this moment
Enable signal E can become high level, turn off the clock second clock clk2a and the 3rd clock of whole sampling adjustment circuit
Refclka, at this moment the adjustable frequency multiplier of whole low-power consumption thoroughly settle out, current control oscillator according to it is anticipated that ideal
Frequency stabilization shakes, simultaneously because entirely sampling adjustment circuit is all turned off, only remains oscillating circuit, so whole circuit
Power consumption will substantially reduce.
Patent of the present invention gives a simple adjustable frequency multiplier circuit of low-power consumption easily realized, and stable performance, multiple
Responsible designer requires to be adjusted, and adjustment circuit gets up simply will easily realize using sample circuit, design, and
Some very flexible strict logic controls are employed in adjustment circuit, it is ensured that circuit has reached simplified and correct simultaneously, by
In after frequency multiplier is stable, the whole adjustment circuit clock that samples all is turned off, and its stability has obtained effective control, power consumption
It is greatly reduced.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (9)
1. a kind of adjustable frequency multiplier of low-power consumption, it is characterised in that the frequency multiplier includes：
Clock circuit, it produces and exports clock signal and sampled clock signal；Clock signal is the adjustable frequency multiplier of low-power consumption
Clock exports；
Adjustment circuit is sampled, it receives external reference clock and the sampled clock signal of clock circuit output, when passing through sampling
Clock signal samples to reference clock, obtains the number of high level in reference clock, is exported as sampled signal；
Clock stable decision circuitry, it receives the sampled signal of sampling adjustment circuit output, adjusted by sampling clock control signal
The number of high level and output in reference clock are saved, also exports enable signal control sampling adjustment circuit opening and closing；
When the number of high level in clock stable decision circuitry judgment standard clock is more than default number threshold value, clock stable is sentenced
Deenergizing control clock circuit reduces the output frequency of sampled clock signal, reduces high in sampled clock signal sampled reference clock
The number of level；Or when the number of high level in clock stable decision circuitry judgment standard clock is less than default number threshold
Value, the output frequency of clock stable decision circuitry control clock circuit increase sampled clock signal, increase sampled clock signal are adopted
The number of high level in sample reference clock；
When the number of high level in reference clock is equal to default number threshold value, clock circuit stable oscillation stationary vibration exports clock signal,
And clock stable decision circuitry exports the enable signal of high level, the clock input of driving sampling adjustment circuit is fixed as high electricity
It is flat, close sampling adjustment circuit；
The sampling adjustment circuit includes：
3rd OR circuit, its input receive rising edge sampled signal, trailing edge sampled signal and the 3rd clock, or input
Output end output reset signal after reception rising edge sampled signal, trailing edge sampled signal and reference clock, or computing；
Sample circuit, it receives the 3rd clock, reset signal and sampled clock signal, or receive reference clock, reset signal and
Sampled clock signal；Sample circuit exports sampled signal after being sampled to the number of high level in reference clock；
Latch cicuit, it receives the sampled signal of sample circuit output, and the 3rd clock or reference clock by reversely producing
Reverse clock, the latch circuit latches sample circuit output complete sampled signal, and export by latch sampling letter
Number.
2. the adjustable frequency multiplier of low-power consumption as claimed in claim 1, it is characterised in that the clock circuit includes：
Current control oscillator, it receives initial impressed current source, produces and export the first clock signal；
Frequency-halving circuit, its inlet circuit connect the output end of current control oscillator, receive the first clock signal, output two
Sub-frequency clock signal；The two divided-frequency clock signal exports as the clock of the adjustable frequency multiplier of low-power consumption；
Circular shift register, it receives two divided-frequency clock signal, exports sampled clock signal.
3. the adjustable frequency multiplier of low-power consumption as claimed in claim 2, it is characterised in that the adjustable frequency multiplier of low-power consumption also wraps
Contain：
First OR circuit, it is electrically connected between frequency-halving circuit and circular shift register；First OR circuit inputs
End receives the two divided-frequency clock signal of frequency-halving circuit output and the enable signal of clock stable decision circuitry output, or after computing
Second clock is exported to circular shift register, circular shift register is using second clock as input, output sampling clock letter
Number to sampling adjustment circuit；
Second OR circuit, its input receive reference clock and the enable signal of clock stable decision circuitry output, or computing
The 3rd clock is exported afterwards to sampling adjustment circuit；
When the adjustable frequency multiplier stable oscillation stationary vibration output clock signal of low-power consumption, the high electricity of enable signal output of clock stable decision circuitry
It is flat, drive second clock and the 3rd clock to be fixed as high level, close sampling adjustment circuit.
4. the adjustable frequency multiplier of low-power consumption as claimed in claim 3, it is characterised in that the clock circuit also includes：
Rising edge sample circuit, its input receive the 3rd clock, and clock end receives second clock, and rising edge sample circuit is in the
Two rising edge clocks export rising edge sampled signal to the 3rd clock sampling；
Trailing edge sample circuit, its input receive the 3rd clock, and clock end receives second clock, and trailing edge sample circuit is in the
Two clock falling edges export trailing edge sampled signal to the 3rd clock sampling.
5. the adjustable frequency multiplier of low-power consumption as claimed in claim 2, it is characterised in that the clock circuit also includes：
Rising edge sample circuit, its input receive reference clock, and clock end receives two divided-frequency clock signal, rising edge sampling electricity
Road samples in two divided-frequency rising edge clock signal to reference clock, exports rising edge sampled signal；
Trailing edge sample circuit, its input receive reference clock, and clock end receives two divided-frequency clock signal, trailing edge sampling electricity
Road samples in two divided-frequency clock signal trailing edge to reference clock, exports trailing edge sampled signal.
6. the adjustable frequency multiplier of low-power consumption as claimed in claim 1, it is characterised in that if the sample circuit rises comprising main line
Along d type flip flop, the D ends per road rising edge d type flip flop receive the 3rd clock or reference clock, and clock end receives sampling clock letter
Number, reset end and receive reset signal, output end output sampled signal.
7. the adjustable frequency multiplier of low-power consumption as claimed in claim 1, it is characterised in that if the latch cicuit rises comprising main line
Along d type flip flop, the D ends per road rising edge d type flip flop receive the sampled signal of sample circuit output, and clock end receives the 3rd clock
Or reference clock passes through the sampled signal latched by reversely caused reverse clock, output end output.
8. the adjustable frequency multiplier of low-power consumption as claimed in claim 1, it is characterised in that the clock stable decision circuitry includes：
Voltage-controlled current source, its circuit of output terminal connection clock circuit, the clock signal and sampling clock of control clock circuit output
The frequency size of signal；
Adder, it, which is received, samples the sampled signal that adjustment circuit exports, the number of high level in output reference clock；
First logic circuit, it receives the number of high level in the reference clock of adder output；When high level in reference clock
Number be more than default number threshold value, the first logic circuit control voltage-controlled current source reduces clock signal and sampled clock signal
Output frequency；When the number of high level in reference clock is less than default number threshold value, the first logic circuit controls voltage-controlled electricity
Stream source increases the output frequency of clock signal and sampled clock signal；When the number of high level in reference clock is equal to default
Number threshold value, the first logic circuit control voltage-controlled current source keep the output frequency of clock signal and sampled clock signal constant.
9. the adjustable frequency multiplier of low-power consumption as claimed in claim 3, it is characterised in that the clock stable decision circuitry includes：
Voltage-controlled current source, its circuit of output terminal connection clock circuit, the clock signal and sampling clock of control clock circuit output
The frequency size of signal；
Adder, it, which is received, samples the sampled signal that adjustment circuit exports, the number of high level in output reference clock；
First logic circuit, it receives the number of high level in the reference clock of adder output；When high level in reference clock
Number be more than default number threshold value, the first logic circuit control voltage-controlled current source reduces clock signal and sampled clock signal
Output frequency, when the number of high level in reference clock is less than default number threshold value, the first logic circuit controls voltage-controlled electricity
Stream source increases the output frequency of clock signal and sampled clock signal；When the number of high level in reference clock is equal to default
Number threshold value, the first logic circuit control voltage-controlled current source keep the output frequency of clock signal and sampled clock signal constant；
Second logic circuit, its inlet circuit connect the first logic circuit, and circuit of output terminal connects the first OR circuit and the
Two OR circuits, when the number of high level in reference clock is equal to default number threshold value, and the second logic circuit counts benchmark
The number of high level is equal to the number of default number threshold value in clock, when the number of statistics reaches default frequency threshold value, second
Logic circuit is the enable signal for exporting high level to the first OR circuit and the second OR circuit.
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| CN111092600B (en) * | 2020-01-15 | 2021-06-01 | 电子科技大学 | FPGA frequency doubling method based on phase superposition method |
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Address after: 201203 No. 12, Lane 647, Songtao Road, Shanghai China (Shanghai) Free Trade Pilot Area, Pudong New Area, Shanghai Patentee after: Juchen Semiconductor Co., Ltd. Address before: 201203 No. 12, Lane 647, Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Patentee before: Giantec Semiconductor Inc. |