CN103684445B - Multiphase high-resolution phaselocked loop - Google Patents

Abstract

A kind of high-resolution phaselocked loop, described high-resolution phaselocked loop includes an input frequency divider, a phase discriminator being connected with described parametric frequency divider, a low pass filter being connected with described phase discriminator, a voltage controlled oscillator being connected with described low pass filter, a leggy loop divider being connected with described voltage controlled oscillator and described phase frequency detector, an output frequency divider being connected with described sub-controlled oscillator.Described high-resolution phaselocked loop provides high-resolution low noise clock signal, and described leggy loop divider provides high-resolution feedback signal for described phase frequency detector.The present invention improves the resolution of pll output signal in the case of reducing loop analysis difficulty and reducing resource overhead.

Description

Multiphase high-resolution phaselocked loop

Technical field

The present invention relates to frequency retrieval and synthetic technology, be specifically related to a kind of multiphase high-resolution Phaselocked loop.

Background technology

Phaselocked loop, in modern electronic technology, is widely used.Utilize in the microprocessor Phaselocked loop provides high-quality system clock for system.Phaselocked loop skill is utilized at wireless communication field Art carries out Up/Down Conversion, modulation /demodulation etc..

Phaselocked loop basic structure is by phase frequency detector (FPD), low pass filter (LPF), pressure Controlled oscillator (VCO).Phase discriminator generation one and phase contrast voltage linearly；Low Bandpass filter is used for suppressing the radio-frequency component of phase discriminator output voltage；Voltage controlled oscillator is in low pass filtered Vibration output respective frequencies signal under the control of ripple device output voltage signal；Loop divider (1/N) Feedback clock is provided for phase frequency detector；Insert between input reference clock and phase frequency detector One input frequency divider (1/Q), the outfan at voltage controlled oscillator inserts an output frequency divider (1/M), To improve resolution；When input is fr with reference to s clock frequency, output frequency fout is:

$f_{\mathrm{out}}=\frac{f_r*N}{q*M}$

Output resolution ratio according to above formula phaselocked loop is determined by variable Q and M, can regulate Q, M Output frequency resolution is controlled with the value of N.Generally come by the value of regulation Q, M and N It is extremely limited for improving resolution；Regulation Q improves resolution, and essence is to reduce input mirror The frequency of the reference clock of phase device, the lowest reference frequency requires the band that low pass filter is less Width, reduces loop bandwidth, increases output noise；If regulation M improves output resolution ratio, Voltage controlled oscillator output frequency will be made to be accomplished by raising, and voltage controlled oscillator output frequency is to have the upper limit , and high output frequency causes the increase of power consumption；The resolution that regulation Q and M obtains It is extremely limited.In actual application, generally require higher resolution, traditional structure Phaselocked loop cannot meet demand.Occurred in that later bimodulus decimal frequency divider structure phaselocked loop and The phaselocked loop of delta sigma structure.

Bimodulus fractional frequency division principle makes certain many meter of several cycles exactly in several dividing cycle Or count a number less, thus in the meansigma methods of the output frequency of a period of time inner ring road frequency divider it is The result of corresponding fractional frequency division.A/B to be realized divides, and exports A within B cycle The individual cycle can be achieved with fractional frequency division.But A cycle is not essentially equal, and loop divides Frequently the output signal of device has the biggest jitter.The advantage of this structure is to improve output frequency Resolution, it is achieved simple；Shortcoming is that loop cannot suppress the low frequency having fractional frequency division to produce to make an uproar Sound, therefore output signal to noise ratio is bigger；

The principle of Delta_sigma phaselocked loop Delta_sigma manipulator produces loop divide Ratio, pushes the noise of loop divider to high band, and the noise of high frequency is by the low pass in phaselocked loop Wave filter suppresses.Delta_sigma phaselocked loop is widely used in wireless communications. Delta_sigma phaselocked loop advantage is that output resolution ratio is high, and noise is low；Shortcoming is loop design Analyzing excessively complicated, Delta_sigma manipulator there is also the problem of stability, design work Measure the biggest；

Summary of the invention

In view of the foregoing, it is necessary to provide one design to analyze simple, it is easy to accomplish, possess High score resolution, the phaselocked loop of low noise.

A kind of high-resolution phaselocked loop, described high-resolution phaselocked loop include a parametric frequency divider, One phase discriminator being connected with described parametric frequency divider, a low-pass filtering being connected with described phase discriminator Device, a voltage controlled oscillator being connected with described low pass filter, one with described voltage controlled oscillator and Leggy loop divider that described phase frequency detector is connected, one it is connected with described sub-controlled oscillator Output frequency divider.Described high-resolution phaselocked loop provides high-resolution low noise clock signal, Described leggy loop divider provides high-resolution feedback signal for described phase frequency detector. It is defeated that the present invention improves phaselocked loop in the case of reducing loop analysis difficulty and reducing resource overhead Go out the resolution of signal.

The present invention completes loop divide mainly by leggy frequency divider, obtains higher dividing Resolution and do not introduce the feedback signal of the highest noise；Ensure that phaselocked loop low noise high-resolution is defeated Go out；Leggy loop divider simple in construction is easily achieved；

Accompanying drawing explanation

Fig. 1 is multiphase high-resolution phaselocked loop.

Fig. 2 is leggy loop divider.

Detailed description of the invention

In Fig. 1: DIVQ. inputs frequency divider；PD. phase discriminator；LP. low pass filter；VCO. Voltage controlled oscillator；DIVM. output frequency divider；DIVNK. leggy loop divider；

In Fig. 2: dual-mode frequency divider；Phase controller；D type flip flop DFF₀、DFF₁、DFF₂、 DFF_K-1;MUX. MUX；

Below in conjunction with the accompanying drawings the present invention is elaborated.

Multiphase high-resolution phaselocked loop, core concept utilize voltage controlled oscillator output many Phase signal carries out the fractional frequency division of zero jitter.So have only to solve how to obtain leggy letter Number and how to utilize leggy to carry out the fractional frequency division of zero jitter.

In described Fig. 1, input signal fin is connected with input frequency device, input frequency divider carry out 1/Q Frequency dividing；The output of input frequency divider is connected with phaselocked loop phase frequency detector reference signal end；Phase demodulation The outfan of device is connected with the input of low pass filter, low pass filter filter high frequency and make an uproar Sound；The outfan of low pass filter is connected with the input of voltage controlled oscillator, and voltage controlled oscillator is adopted With ring oscillator, it is provided that multi-phase clock signal exports；The leggy of voltage controlled oscillator output Clock signal P₀-P_K-1A road be connected with the input of output frequency divider, output frequency divider enter Export after row 1/M frequency dividing；The multiphase clock of the multi-phase clock signal of voltage controlled oscillator output Signal CLKP₀-CLKP_k-1Being connected with the input of leggy loop divider, leggy divides Device utilizes multi-phase signals to carry out N+j/K frequency dividing；The outfan of leggy frequency divider and phaselocked loop The feedback end of phase discriminator is connected.

In described Fig. 2, decimal frequency dividing control word and zero phase clock signal clk P0 and bimodulus divide Frequently the input of device is connected；The output signal of dual-mode frequency divider is respectively and d type flip flop The D end of DFF0-DFFK-1 is connected；Multi-phase clock signal CLKP0-CLKPK-1 is respectively and D The CK end that the D end of trigger DFF0-DFFK-1 is connected is connected；Fractional frequency division control word is with double The output signal of mould frequency divider is connected with the input of phase controller；The output of phase controller End is connected with the SEL end of MUX MUX;The Q end of d type flip flop DFF0-DFFK-1 divides It is not connected with the A0-AK-1 end of MUX；Finally exported by DEC_OUT；

VCO in phaselocked loop uses ring oscillator to be easy for the leggy that can obtain needing Signal.Ring oscillator is made up of some stage gain circuit.Each node of these gain circuitries Obtained signal frequency is the same, but they exist phase contrast.Suitably choose gain circuitry Progression can be readily available the multi-phase signals that many designs need, and improves for leggy frequency divider Multi-phase signals；

Leggy fractional frequency division is the emphasis of the present invention, and its performance directly affects the property of phaselocked loop Energy.First with dual-mode frequency divider to multi-phase signals CLKP₀Do N+j/K fractional frequency division；Double Mould refers to N and N+1；Utilize leggy handoff technique offset dual-mode frequency divider increase or reduce one The individual cycle.Dual-mode frequency divider can utilize following methods to realize: designs a depositor DEC to little Number j is overlapped, and when the value of DEC is more than 1, mould takes N+1, and depositor DEC is clear simultaneously Zero, calculate ready for next time, remaining situation mould takes N；Work as CLKP₀-CLKP_K-1To double The sampling of mould output signal of frequency divider obtains the K road signal that frequency equal adjacent phase difference is 2*pi/K (DIVP₀-DIVP_k-1)。DIVP₀-DIVP_k-1The adjacent periods of signal is not likely to be essentially equal , there is the biggest jitter.Utilize phase controller to produce Phase-switching control word, then pass through MUX selects corresponding signal output.Phase-switching controller principle is: i is for currently selecting signal The subscript of DIVP, then it is next that to select signal be that DIVPx is (as i+j < x=i+j during k-1;When During i+j >=k-1, x=i+j-k).Final output signal (DIV_DEC) is cycle all phases Deng zero jitter signal.DIV_DEC is the N+j/K fractional frequency signal of CLKP.DIV_DEC Send into phase discriminator, obtain high-resolution output signal.Leggy loop divider can complete 1/k+N to (k-1)/k+N divides, then output input signal resolution improves k times.

The present invention utilizes the decimal of zero jitter that leggy handoff technique completes loop divider to divide Frequently, improve the output resolution ratio of this phaselocked loop and ensure low noise output.

Claims (1)

1. a multiphase high-resolution phaselocked loop, it is characterised in that: include a parametric frequency divider, a phase frequency detector being connected with described parametric frequency divider, One low pass filter being connected with described phase frequency detector, a voltage controlled oscillator being connected with described low pass filter, one with described voltage controlled oscillator and Described phase frequency detector be connected leggy loop divider, an output frequency divider being connected with described voltage controlled oscillator；Voltage controlled oscillator uses annular Agitator, ring oscillator is made up of some stage gain circuit, and the signal frequency obtained by each node of these gain circuitries is the same, but they There is phase contrast, the progression suitably choosing gain circuitry can obtain the multi-phase clock signal that design needs, and provides many for leggy loop divider Phase clock signal, the multi-phase clock signal CLKP of voltage controlled oscillator output₀-CLKP_K-1It is connected with the input of leggy loop divider, many Phase loop frequency divider utilizes multi-phase clock signal to carry out N+j/K frequency dividing, and the multi-phase clock signal utilizing voltage controlled oscillator to export carries out zero jitter Fractional frequency division, the outfan of leggy loop divider is connected with the feedback end of phase frequency detector；

Described leggy loop divider includes double-mold frequency divider；The one Phase-switching controller being connected with described dual-mode frequency divider；K and described bimodulus The d type flip flop DFF that frequency divider is connected₀、DFF₁、DFF₂、……、DFF_K-1；The one selector MUX being connected with described trigger；

Fractional frequency division control word and zero phase clock signal clk P₀All be connected with the input of dual-mode frequency divider, the output signal of dual-mode frequency divider respectively with The D end of each d type flip flop connects, multi-phase clock signal CLKP₀-CLKP_K-1Correspondingly with d type flip flop DFF₀-DFF_K-1CK end be connected； Fractional frequency division control word is connected with the input of Phase-switching controller with the output signal of dual-mode frequency divider, and the outfan of Phase-switching controller is with many The SEL end of road selector MUX is connected, d type flip flop DFF₀-DFF_K-1Q end correspondingly with the A of MUX MUX₀-A _K-1End is connected； Leggy loop divider is to multi-phase clock signal CLKP₀Doing N+j/K fractional frequency division, bimodulus refers to N and N+1, utilizes leggy handoff technique to offset The cycle that dual-mode frequency divider increases or reduces；

Dual-mode frequency divider utilizes following methods to realize: designs a depositor DEC and is overlapped decimal j, and when the value of DEC is more than 1, mould takes N+1, with Time depositor DEC reset, for next time calculate ready, remaining situation mould takes N；Work as CLKP₀-CLKP_K-1Dual-mode frequency divider output signal is adopted Sample obtains the K road signal DIVP that frequency equal adjacent phase difference is 2*pi/K₀-DIVP_K-1, DIVP₀-DIVP_K-1The adjacent periods of signal has been not likely to be The most equal, there is the biggest jitter, utilize Phase-switching controller to produce Phase-switching control word, then select corresponding signal to export by MUX, Phase-switching controller principle is: i is the subscript of the DIVP currently selecting signal, then next selection signal is DIVP_x(as i+j ＜ k-1 x=i+j； As i+j >=k-1, x=i+j-k), final output signal DIV_DEC is equal zero jitter signal of each cycle, and DIV_DEC is CLKP's N+j/K fractional frequency signal, sends DIV_DEC into phase frequency detector, obtains high-resolution output signal, and leggy loop divider completes 1/k+N Dividing to (k-1)/k+N, output input signal resolution improves k times.