JP4217500B2 - Clock abnormality detection circuit and detection method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock abnormality detection circuit and a detection method therefor, and more particularly, to a clock abnormality detection circuit that detects a duty ratio abnormality and a discontinuous period abnormality of an electronic circuit clock.
[0002]
[Prior art]
Many electronic circuits operate on the basis of a clock signal. An electronic circuit that operates on the basis of a clock signal is designed on the assumption that the clock signal is always output at a constant period and duty ratio. However, the clock signal generation circuit may output an abnormal signal due to aging or failure. At this time, the electronic circuit cannot recognize the clock signal and operate normally. Therefore, in an electronic circuit, it is general to provide a circuit for detecting an abnormality of the clock signal, or to calibrate the clock signal generation circuit periodically to take measures against malfunction caused by the clock signal. .
[0003]
As one clock abnormality detection method, as disclosed in Patent Document 1, there is a conventional technique for detecting a discontinuous period abnormality or duty ratio abnormality of a clock signal. FIG. 5 shows a circuit configuration diagram of the prior art. Reference numeral 501 denotes an inspection clock. Reference numeral 502 denotes a one-cycle delay circuit. Reference numeral 503 denotes a comparison circuit that takes an exclusive OR of the clock 501 to be inspected and the one-cycle delay circuit 502. Reference numeral 504 denotes a counter which is added by the clock input of the clock signal 505 corresponding to the output data of the comparison circuit 503. Reference numeral 506 denotes a latch circuit that detects a discontinuous clock period abnormality or an abnormality when the duty ratio changes in the clock 501 to be inspected due to the overflow of the counter 504.
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-24037
[Problems to be solved by the invention]
However, in the above-mentioned prior patent, since the signal waveform obtained by delaying the clock to be tested and the clock to be tested by one cycle is compared by the exclusive OR circuit, noise is likely to be generated in the signal waveform at the signal change point. There is a mechanism for ignoring pulses within a certain period to eliminate this noise, but it is necessary to adjust the setting of the pulse period that is the object of noise removal. In some cases, the clock is determined to be normal, or the normal clock to be inspected is determined to be abnormal.
[0006]
Also, the noise elimination mechanism uses the exclusive OR of the signal waveform obtained by delaying the clock to be tested and the clock to be tested by one cycle as an input to the counter, and inputs the clock to the counter at a certain cycle. Recognize abnormal inspection clock duty ratio and discontinuous periodic abnormality. Therefore, it is necessary to prepare a clock with a sufficiently short period for the clock input of the counter with respect to the clock to be inspected.
[0007]
The present invention solves the conventional problem, has delay means for delaying the clock to be tested by a predetermined time, and stores a state after a predetermined time of the clock to be tested at an output signal edge of the delay means. By having a clock state storage means and a determination means for detecting an abnormality of the clock to be inspected from the output of the clock state storage means, a special clock input is not required in addition to the clock to be inspected. An object of the present invention is to provide a clock abnormality detection circuit and a method for detecting the abnormality, which are characterized by detecting an abnormality.
[0008]
[Means for Solving the Problems]
The present invention includes delay means for delaying a clock to be inspected by a predetermined time, clock state storage means for storing a state of the clock to be inspected after the lapse of the predetermined time based on an output signal of the delay means, and the clock state Determining means for comparing and determining an output of the storage means and an expected output value of the clock to be inspected after the predetermined time has elapsed to detect an abnormality of the clock to be inspected, wherein the determination means comprises the clock state storage means And an output based on the output signal of the delay means, and a counter means for counting the occurrence of the inspected clock abnormality, the delay means differing from each other by a certain fixed time. A clock comprising a plurality of sets of the clock state storage means and the counter means, and a counter comparison means for comparing the outputs of the plurality of counter means. Tsu is a click abnormality detection circuit.
[0011]
Furthermore, the present invention is a clock abnormality detection circuit having programmable delay means capable of freely setting the delay time of the delay means.
[0012]
The present invention provides a delay step for delaying the clock to be tested by a predetermined time, a storage step for storing the state of the clock to be tested after the predetermined time has elapsed based on the delayed signal, and a state stored in the storage step And a determination step of detecting an abnormality of the clock to be inspected by comparing and determining an output of the clock to be inspected and an output expected value after the predetermined time has elapsed, and the determination step outputs the output of the storage step. The delay step, the storing step, and the counting step, each having an input and adding based on the delayed signal to count occurrences of abnormal clocks to be inspected, each having a different fixed time to be delayed a plurality of sets of a, and click with the counter comparison step for comparing the output of the result of counting a plurality of said counting step Tsu is a click abnormality detection method.
[0014]
According to the present invention, it is possible to detect and determine the state of the clock to be inspected after a certain period using only the clock to be inspected, and it is possible to detect a duty ratio abnormality or a discontinuous period abnormality of the clock to be inspected.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described.
An embodiment of a clock abnormality detection circuit and a detection method thereof according to the present invention will be described with reference to FIGS. FIG. 1 is an explanatory diagram of an example of a system configuration diagram of the clock abnormality detection circuit according to the first embodiment. FIG. 2 is an explanatory diagram of an example of a signal waveform in the circuit when the duty ratio of the clock to be tested according to the first embodiment is 1: 1. FIG. 3 is an explanatory diagram of an example of a signal waveform in the circuit when the duty ratio of the clock to be inspected according to the first embodiment is 7: 1. FIG. 4 is an explanatory diagram of an example of a signal waveform in the circuit when the duty ratio of the clock to be inspected according to the first embodiment is 1: 7.
[0016]
Example 1 will be described. FIG. 1 shows an example of the system configuration of this embodiment. Reference numeral 101 denotes a clock to be inspected, which is an input of a clock abnormality detection circuit. Reference numeral 102 denotes a ¼ period delay circuit which delays the clock 101 to be inspected by ¼ period (fixed time). Reference numeral 103 denotes a 3/4 cycle delay circuit, which delays the clock 101 to be inspected by 3/4 cycle (fixed time). Reference numerals 104 and 105 denote flip-flops, which store (latch) the clock 101 to be inspected at the output edges of the 1/4 cycle delay circuit 102 and the 3/4 cycle delay circuit 103. A NOT circuit 106 inverts the output of the flip-flop 104. Reference numerals 107 and 108 denote counters which add at the output edges of the 1/4 cycle delay circuit 102 and the 3/4 cycle delay circuit 103 according to the input data. By comparing and determining the outputs of the clock state storage means 104 and 105 and the expected output value after a lapse of a predetermined time of the inspection clock, it is possible to detect an abnormality of the inspection target clock.
[0017]
When the clock 101 to be inspected changes from HIGH to LOW during one period, if the data changes from HIGH to LOW by the end of a quarter period, the LOW data is stored (latched) in the flip-flop 104, and NOT. By inverting by the circuit 106, HIGH data is output from the NOT circuit 106, and it can be seen that the duty ratio of the clock 101 to be inspected is larger than 1: 3 by adding the value of the counter 107. In this way, the abnormality of the clock 101 to be inspected can be detected.
[0018]
Similarly, if the clock to be inspected 101 remains HIGH even after 3/4 period elapses, HIGH data is stored (latched) in the flip-flop 105, and the value of the counter 108 is added to the object to be inspected. It can be seen that the duty ratio of the clock 101 is greater than 3: 1. Thereby, the abnormality of the clock 101 to be inspected can be detected.
[0019]
The cyclic delay circuits 102 and 103 are configured by a delay circuit in which the number of cascaded stages of inverter circuits is adjusted to a predetermined number, a delay circuit configured by a logic gate and CR (capacitor and resistor), an inductor and a capacitor. A desired delay circuit can be easily obtained by adjusting the number of stages and the tap position with the delay circuit.
[0020]
Then, by configuring the system of FIG. 1 with programmable delay circuits (having means for selecting the number of stages and tap positions) that can freely set the delay time for the 1/4 cycle delay circuit 102 and the 3/4 cycle delay circuit 103, By sequentially changing the settings of the programmable delay circuit, it is possible to specify the point at which the clock 101 to be tested transitions from HIGH to LOW, and to specify the duty ratio of the clock 101 to be tested.
[0021]
FIG. 2 shows signal waveforms when the duty ratio and period of the clock to be inspected are normal. 201 is the signal waveform of the clock to be inspected, and 202 and 203 are the outputs of the 1/4 cycle delay circuit 102 and 3/4 cycle delay circuit 103, respectively. 204 is an output signal waveform of the flip-flop 104, and 205 is an output signal of the NOT circuit 106. Reference numeral 206 denotes an output of the flip-flop 105. Reference numeral 207 represents the count value of the counter 107, and 208 represents the count value of the counter 108. In this case, since the count value of the counter 107 is 0 and the count value of the counter 108 is also 0, there is no abnormality in the clock.
[0022]
FIG. 3 shows a signal waveform when a duty ratio abnormality occurs in the clock to be inspected. Reference numeral 301 denotes a signal waveform of the clock to be inspected, and there is a duty ratio abnormality in the second cycle and the fourth cycle. Reference numerals 302 and 303 denote outputs of the quarter cycle delay circuit 102 and the 3/4 cycle delay circuit 103, respectively. Reference numeral 304 denotes an output signal waveform of the flip-flop 104, and reference numeral 305 denotes an output signal of the NOT circuit 106. Reference numeral 306 denotes an output of the flip-flop 105. Reference numeral 307 denotes a count value of the counter 107, and reference numeral 308 denotes a count value of the counter 108. In this case, the count value of the counter 107 is 1, while the count value of the counter 108 is 1, so that it can be seen that there is an abnormality in the clock.
[0023]
FIG. 4 shows signal waveforms when the clock to be inspected has a discontinuous periodic abnormality. Reference numeral 401 denotes a signal waveform of the clock to be inspected, and there are discontinuous periodic abnormalities in the second cycle and the fourth cycle. Reference numerals 402 and 403 denote outputs of the quarter cycle delay circuit 102 and the 3/4 cycle delay circuit 103, respectively. 404 is an output signal waveform of the flip-flop 104, and 405 is an output signal of the NOT circuit 106. Reference numeral 406 denotes an output of the flip-flop 105. Reference numeral 407 denotes a counter 107 count, and reference numeral 408 denotes a counter 108 count. In this case, since the count of the counter 107 is 1 and the count of the counter 108 is 2, it can be seen that there is an abnormality in the clock.
[0024]
In the first embodiment, by using the counters 107 and 108, when a duty ratio abnormality occurs as shown in FIG. 3 or when a cycle abnormality occurs as shown in FIG. 4, FIG. 3 (duty ratio abnormality) In this case, the count values of the two counters are added with the same value, but in the case of FIG. 4 (period abnormality), the count values of the two counters are added with different values. By detecting and comparing, the type of abnormality can be selected. As a result, it is possible to take measures against the clock abnormality of the clock generation circuit and to analyze the abnormality.
[0025]
Further, by providing a plurality of sets of delay means, clock state storage means and counter means, each of which has a different delay time, and a counter comparison means for comparing the outputs of the counter means, It is possible to detect abnormalities.
[0026]
【The invention's effect】
As described in the embodiment, according to the present invention, the clock to be tested is delayed by a predetermined time, and the state of the clock to be tested is stored in a flip-flop that uses the delayed signal as a clock input. Without preparing a simple clock, it is possible to detect the state of the clock to be inspected after a certain time, and to detect a clock duty ratio abnormality or a discontinuous periodic abnormality.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of an example of a system configuration diagram of a clock abnormality detection circuit according to a first embodiment;
FIG. 2 is an explanatory diagram showing an example of a signal waveform in the circuit when the duty ratio of the clock to be inspected according to the first embodiment is 1: 1.
FIG. 3 is an explanatory diagram showing an example of a signal waveform in the circuit when the duty ratio of the clock to be inspected is 7: 1 according to the first embodiment.
FIG. 4 is an explanatory diagram illustrating an example of a signal waveform in the circuit when the duty ratio of the clock to be inspected according to the first embodiment is 1: 7.
FIG. 5 is an explanatory diagram of a conventional system configuration example.
[Explanation of symbols]
101 Clock to be tested 102 1/4 cycle delay circuit 103 3/4 cycle delay circuit 104, 105 flip-flop circuit 106 NOT circuit 107, 108 counter

Claims (3)

Delay means for delaying the clock to be tested by a predetermined time, clock state storage means for storing the state of the clock to be tested after the lapse of the predetermined time based on an output signal of the delay means, and output of the clock state storage means wherein a determination means for comparing determines the output expectation value after the lapse of the predetermined time of the inspection clock for detecting an abnormality of the inspection clock and,
The determination means has a counter means for taking the output from the clock state storage means as an input and counting the occurrence of the inspected clock abnormality by performing addition based on the output signal of the delay means;
A plurality of sets of the delay means, the clock state storage means, and the counter means, each of which has a different delay time, and a counter comparison means for comparing the outputs of the counter means. An abnormal clock detection circuit.   2. The clock abnormality detection circuit according to claim 1, further comprising programmable delay means capable of freely setting a delay time of the delay means. A delay step for delaying the clock to be inspected by a predetermined time; a storage step for storing the state of the clock to be inspected after the lapse of the predetermined time based on the delayed signal; an output of the state stored in the storing step; A determination step of comparing and determining an expected output value of the clock after the predetermined time has elapsed and detecting an abnormality of the clock to be inspected,
The determination step includes a counting step of taking the output of the storing step as an input and counting the occurrence of the inspected clock abnormality by performing addition based on the delayed signal;
A plurality of sets each including a delay step, a storage step, and a counting step each having a different fixed time to be delayed are provided, and a counter comparing step that compares outputs of the results counted in the plurality of counting steps is provided. A clock error detection method.

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