CN109580975A - A kind of speed detector based on pwm signal, processing circuit and chip - Google Patents
A kind of speed detector based on pwm signal, processing circuit and chip Download PDFInfo
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- CN109580975A CN109580975A CN201811501749.9A CN201811501749A CN109580975A CN 109580975 A CN109580975 A CN 109580975A CN 201811501749 A CN201811501749 A CN 201811501749A CN 109580975 A CN109580975 A CN 109580975A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P3/00—Measuring linear or angular speed; Measuring differences of linear or angular speeds
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02K—DYNAMO-ELECTRIC MACHINES
- H02K11/00—Structural association of dynamo-electric machines with electric components or with devices for shielding, monitoring or protection
- H02K11/20—Structural association of dynamo-electric machines with electric components or with devices for shielding, monitoring or protection for measuring, monitoring, testing, protecting or switching
Abstract
The present invention discloses a kind of speed detector based on pwm signal, processing circuit and chip, the speed detector is applied to provide impulse sampling speed for external electric system, and the speed detector includes rising edge detection circuit, pulsewidth counter and intermediate value averaging module；The input end of clock of the rising edge detection circuit is connect with the input end of clock of the pulsewidth counter, the output end of the rising edge detection circuit is connect with the reset terminal (reset) of the pulsewidth counter, and the data output end of the pulsewidth counter connects the data input pin of the intermediate value averaging module.The speed detector expands the function of traditional pwm signal output circuit, improves the precision that pulse signal tests the speed.
Description
Technical field
The present invention relates to signal modulation technique field, be related to a kind of speed detector based on pwm signal, processing circuit and
Chip.
Background technique
PWM (Pulse Width Modulation) technology is in industrial automation, robot, precise numerical control machine, boat
The numerous areas such as empty space flight are used widely.Servo control system needs to generate the pwm signal driving of variable duty ratio
IGBT, IPM constant power device；The kinetic control systems such as robot or numerically-controlled machine tool can between motion control card and servo-driver
Pass through the pwm signal of changeable frequency, transmission location control instruction.PWM and PFM is two kinds of control modes of DC/DC switch, this kind of
Technology is usually used in some analog circuits or peripheral motor is controlled.As the integrated level of IC is higher and higher.It is most of on the market
Pwm circuit there are many kinds of implementation, but these circuit universal functionalities are single, and the functions such as do not test the speed, and do not utilize by adopting
Sample feeds back to control the revolving speed of electric system.
Summary of the invention
In order to overcome the problems referred above, the invention proposes a kind of speed detectors based on pwm signal.
A kind of speed detector based on pwm signal, the speed detector are applied to provide arteries and veins for external electric system
Sample rate is rushed, speed detector includes rising edge detection circuit, pulsewidth counter and intermediate value averaging module；Rising edge detection electricity
The input end of clock on road is connect with the input end of clock of pulsewidth counter, the output end and pulsewidth counter of rising edge detection circuit
Reset terminal (reset) connection, the data input pin of the data output end connection intermediate value averaging module of pulsewidth counter, intermediate value is flat
Output end of the data output end of equal module as speed detector, the input terminal of rising edge detection circuit is as speed detector
Data input pin.
Further, the rising edge detection circuit includes a d type flip flop and one and door, the input terminal of d type flip flop
(D) input terminal with door, the reversed-phase output of d type flip flop are connectedAnother input terminal of connection and door；The pulsewidth meter
The clock end of number devices is connected with the clock end of d type flip flop, the output with the output end of door as the rising edge detection circuit
End, input terminal of the input terminal of d type flip flop as the rising edge detection circuit.
Further, the clock that the bit wide numerical value power of the 2 pulsewidth counter is greater than the pulsewidth counter inputs
The ratio of the signal frequency of the input terminal of the signal frequency at end and the d type flip flop.
A kind of processing circuit of pwm signal, the processing circuit are applied to the electric system outside adjusting, the processing circuit
Including PWM sample detecting module and PWM generation module；The input end of clock of PWM sample detecting module and PWM generation module when
Clock input terminal is connected；PWM sample detecting module includes step-length counting submodule, signal pre-divider, filter, the first clock
Pre-divider and the speed detector, wherein the signal input part of filter is inputted as the signal of PWM sample detecting module
End, output end of the speed signal output end of the speed detector as PWM sample detecting module；PWM sample detecting module
Internal connection relationship is: the signal output end of filter divides with the data input pin and signal of step-length counting submodule in advance simultaneously
The input end of clock of frequency device connects, and the output terminal of clock of signal pre-divider is connected with the data input pin of the speed detector
It connects；The input end of clock of speed detector is connected with the output terminal of clock of the first clock pre-divider；PWM generation module includes
Second clock pre-divider and pwm signal generator, the connection relationship of inside modules is: the clock of second clock pre-divider is defeated
Outlet is connected with the data input pin of pwm signal generator, and the input end of clock of second clock pre-divider is generated as PWM
The input end of clock of module, output end of the data output end of pwm signal generator as PWM generation module.
Further, the filter includes the d type flip flop and a comparison output module of the first preset quantity, and first is pre-
If the d type flip flop of quantity constitutes the shift register of a first preset quantity bit, the d type flip flop of the first preset quantity
Clock end is connected to the input end of clock of the filter, and the output end (Q) of the d type flip flop of the first preset quantity is connected respectively to
Compare the data input pin of the first preset quantity of output module, signal of the data input pin of shift register as filter
Input terminal compares signal output end of the data output end as filter of output module.
Further, in the shift register, each d type flip flop other than the d type flip flop of rightmost it is defeated
Outlet (Q) is connected to the input terminal (D) of one d type flip flop in the right, and the output end (Q) of the d type flip flop of rightmost accesses the comparison
One data input pin of output module.
Further, in the shift register, each d type flip flop other than leftmost d type flip flop it is defeated
Outlet (Q) is connected to the input terminal (D) of one d type flip flop in the left side, and the output end (Q) of leftmost d type flip flop accesses the comparison
One data input pin of output module.
Further, first preset quantity is set as 6, so that the filter is by the pwm signal to be processed of input
(PWM_IN) the level shake in less than 5 clock cycle is all filtered as burr, wherein the clock cycle be it is described to
Handle the pulse period of the jitter levels of pwm signal (PWM_IN).
It further, include step-length counter and direction register, direction register inside the step-length counting submodule
Output end connect with the enable end of step-length counter, the terminal count output of step-length counter is as the step-length counting submodule
Output end, data input pin of the counting input end of step-length counter as the step-length counting submodule.
Further, the pwm signal generator includes output frequency divider and comparator, the clock output of output frequency divider
End input terminal compared with one of comparator connects, data of the input terminal of output frequency divider as the pwm signal generator
Input terminal, data output end of the output end of comparator as the pwm signal generator.
A kind of chip, the chip interior include the processing circuit.
Compared with prior art, the speed detector by signal pulsewidth of the counter to sample detecting counted with
Measurement input pwm signal pulsewidth, and intermediate value average treatment is carried out to the pulsewidth numerical value that measurement obtains, thus after output obtains optimization
The impulse speed measured value based on input pwm signal, expand the function of traditional pwm signal output circuit, improve pulse signal
The precision to test the speed.
Detailed description of the invention
Fig. 1 is a kind of speed detector structural schematic diagram based on pwm signal of the embodiment of the present invention.
Fig. 2 is pulse-width samples timing diagram of the speed detector provided in an embodiment of the present invention to input signal.
Fig. 3 is a kind of processing circuit structural schematic diagram of pwm signal of the embodiment of the present invention.
Fig. 4 is the circuit diagram of the filter of the embodiment of the present invention.
Fig. 5 is the circuit diagram of the pwm signal generator of the embodiment of the present invention.
Specific embodiment
Specific embodiments of the present invention will be further explained with reference to the accompanying drawing: as shown in Figure 1, the embodiment of the present invention
A kind of speed detector based on pwm signal is provided, as shown in Figure 1, the speed detector includes rising edge detection circuit, arteries and veins
Wide counter and intermediate value averaging module, the input end of clock of the rising edge detection circuit and the clock of the pulsewidth counter are defeated
Enter end connection, the output end of the rising edge detection circuit is connect with the reset terminal (reset) of the pulsewidth counter, the arteries and veins
The data output end of wide counter connects the data input pin of the intermediate value averaging module.The data of the intermediate value averaging module are defeated
Output end of the outlet as the speed detector.The input terminal of the rising edge detection circuit is as the speed detector
Data input pin.The speed detector is used to the period by measuring the pwm signal PWM_IN to be processed to realize measurement
The velocity amplitude of motor rotation, the time actually measured between two rising edges of the pwm signal PWM_IN to be processed are wide
Degree.
The rising edge detection circuit includes a d type flip flop and one and door, the input terminal D connection of d type flip flop and door
An input terminal, the reversed-phase output of d type flip flopAnother input terminal of connection and door；The clock of the pulsewidth counter
Input terminal is connected with the clock end of d type flip flop, wherein input of the input terminal of d type flip flop as the rising edge detection circuit
End, input end of clock of the clock end of d type flip flop as the rising edge detection circuit.The rising edge detection circuit passes through institute
It states and is connect with the output end of door with the reset terminal reset of the pulsewidth counter.The input terminal D of d type flip flop passes through for receiving
Filter the input pwm signal Encoder1 of scaling down processing；The clock end of d type flip flop is for receiving sub-frequency clock signal Clk_
Div1, the sub-frequency clock signal Clk_div1 are that externally input high frequency clock signal CLK_US divides to obtain.When D is triggered
When the first moment was low level signal, d type flip flop latches to be inputted input pwm signal Encoder1 at the input terminal D of device
Low level signal of the pwm signal Encoder1 at the first moment, by a clock of the sub-frequency clock signal Clk_div1
After period, the reversed-phase output of d type flip flopHigh level signal is exported, if the input terminal D of d type flip flop becomes under synchronization
High level signal is high level signal with two input terminals of door simultaneously, the rising edge detection circuit with door by exporting
High level signal can determine that input pwm signal Encoder1 is rising edge signal at this time, and export to the pulsewidth counter
Reset terminal reset, wherein the output end with the output end of door as the rising edge detection circuit.
Under the driving of the sub-frequency clock signal Clk_div1, when the pulsewidth counter sample detecting to the input
When the rising edge signal of pwm signal Encoder1, counted the rising edge signal as reset signal input, every input
One reset signal, the pulsewidth counter count one according to the pulse number of the sub-frequency clock signal Clk_div1
It is secondary, to obtain the corresponding sub-frequency clock signal Clk_ in a pulse period of the input pwm signal Encoder1
The pulse number of div1.As shown in Fig. 2, the pulsewidth counter often detects one of the input pwm signal Encoder1
Rising edge signal, the sub-frequency clock signal Clk_div1 have passed over 4 clock cycle, and the pulsewidth counter is in original count
Add 4 on the basis of value, as current count value；Between two rising edge signals of the input pwm signal Encoder1, institute
The pulse number for stating sub-frequency clock signal Clk_div1 is 4, and the pulsewidth counter uses 4 sub-frequency clock signal Clk_
The clock cycle of div1 removes the input pwm signal Encoder1 of one pulse period of sampling.In Fig. 2, the input PWM
The arteries and veins for 4 sub-frequency clock signal Clk_div1 that the corresponding dotted line of two rising edge signals of signal Encoder1 is confined
Punching as the standard for the pulsewidth for measuring the input pwm signal Encoder1, and then measures the pwm signal PWM_ to be processed
The corresponding motor speed of IN.Under the conditions of the prior art using clock edge enable signal mode drive the pulsewidth counter into
Row counts, but can have the nonsynchronous problem of clock, and the embodiment of the present invention is driven described by the rising edge detection circuit
Pulsewidth counter counts the pulsewidth of the input pwm signal Encoder1, is really driven by Edge check enable signal
The pulsewidth counter is counted under high frequency clock signal, so that clock is synchronous, improves the input pwm signal
The precision of the pulse period sampling of Encoder1.
Preferably, the bit wide numerical value power of the 2 pulsewidth counter is greater than the input end of clock of the pulsewidth counter
Signal frequency and the d type flip flop input terminal D signal frequency ratio.The first sub-frequency clock signal Clk_div1
Highest input frequency be 80MHz, the first sub-frequency clock signal Clk_div1 is set as under the embodiment of the present invention
20MHz.In order to realize that the first pwm signal Encoder1's described in the first sub-frequency clock signal Clk_div1 synchronized sampling is upper
It rises along signal, the ratio and the arteries and veins of the first sub-frequency clock signal Clk_div1 and the first pwm signal Encoder1
The bit wide of wide counter is there are power side's relationship, when the first pwm signal Encoder1 clock frequency is 32Hz, then described the
The clock frequency of one sub-frequency clock signal Clk_div1 and the ratio of the clock frequency of the first pwm signal Encoder1 are
625000.Because 2 20 power are bigger than 625000,20 bits are set by the bit wide of the pulsewidth counter, thus
The bit wide numerical value power for meeting the 2 pulsewidth counter is greater than the clock frequency of the first sub-frequency clock signal Clk_div1
With the ratio of the clock frequency of the first pwm signal Encoder1；Due to the high frequency clock signal CLK_US maximum clock
Frequency is 80MHz, is 4 times of 20MHz, so when the high frequency clock signal CLK_US mono- frequency dividing obtains the described first frequency dividing
Clock signal Clk_div1, and when the first pwm signal Encoder1 clock frequency is left as 32Hz, it need to be by the pulsewidth meter
The bit wide of number device increases 2 bits, and the bit wide numerical value is set as 22 bits, this is as the correlation built in the pulsewidth counter
Register carries out configuration of reservations, and loads corresponding bit wide numerical value under the premise of high frequency clock signal CLK_US input.
The frequency that the d type flip flop of the rising edge detection circuit receives the first sub-frequency clock signal Clk_div1 is higher, Ke Yizeng
The efficiency of strong rising edge detection, although the clutter of jump cannot be filtered off, the first pwm signal Encoder1, which has been subjected to disappear, to be trembled
Processing, therefore clutter influences less.
The data output end of the pulsewidth counter connects the data input pin of the intermediate value averaging module, the pulsewidth meter
The signal of the pulse number of the data output end output of number device is connected to the data input pin of the intermediate value averaging module；Institute
State output end of the data output end of intermediate value averaging module as the speed detector.Include inside the intermediate value averaging module
One counting sample register, the pulse number for the output of pulsewidth counter described in real-time storage；The intermediate value is average
Module connects the pulsewidth counter, and the intermediate value averaging module controls the pulse number and deposits with the counting sample register
The pulse number of second preset quantity of storage carries out size comparison, and is ranked up according to comparison result, then selects its intermediate value generation
Impulse speed signal speed described in table；Wherein, the pulse number of second preset quantity is the input pwm signal
In Encoder1, the corresponding frequency-dividing clock letter in the pulse period for second preset quantity crossed by sample detecting
The pulse number of number Clk_div1.The intermediate value averaging module under the present embodiment is conducive to eliminate signal noise to the pulse
The influence of number avoids the pulsewidth of the input pwm signal Encoder1 measured from excessive or too small phenomenon occur, to be
The stable speed signal of external motor system acquisition.
As shown in figure 3, the embodiment of the present invention provides a kind of processing circuit of pwm signal, the processing circuit includes that PWM is adopted
Sample detection module and PWM generation module；The input end of clock of the PWM sample detecting module and the PWM generation module when
Clock input terminal is connected；The PWM input terminal of the PWM sample detecting module is used to capture the pwm signal PWM_ to be processed of input
IN, the input end of clock of the PWM sample detecting module are used to receive the high frequency clock letter of external system clock generator output
Number CLK_US, under the embodiment of the present invention, the frequency range of pwm signal PWM_IN to be processed is greater than 32Hz and is less than 2KHz,
The high frequency clock signal CLK_US of external system clock generator output is the clock signal for being 0.2us in the period, passes through corresponding essence
The counting of degree plays signal and disappears the effect of trembling；The PWM sample detecting module is used to export the pulse speed based on pwm signal to be processed
Signal speed and corresponding pulse step size signal are spent for external electric system, are used as feedback quantity.Relative to existing skill
Art expands the application function of pwm signal output circuit.The PWM generation module is defeated for receiving external system clock generator
Sampling clock Clk out, and export the controllable PWM output signal PWM_OUT of the duty ratio based on sampling clock Clk；The PWM
Sample detecting module and the PWM generation module are commonly connected to the sampling clock Clk；Wherein, sampling clock Clk can be with
Bus clock on external ahb bus, corresponding clock frequency size include 80MHz, 40MHz or 20MHz, so that
The PWM output signal PWM_OUT meets the application demand of various electric machine control systems.When the PWM sample detecting module is
When external electric system provides impulse speed signal speed and corresponding pulse step size signal, external electric system according to
Aforementioned sample signal is adjusted, and specifically adjusts the frequency size of the sampling clock Clk of output, pwm signal PWM_ to be processed
Then IN and high frequency clock signal CLK_US controls the PWM output signal PWM_ of the PWM generation module output duty ratio corresponding
OUT, to complete the rotational speed regulation control to external electric system.
The PWM sample detecting module includes the filter, step-length counting submodule, signal pre-divider, the speed
Detector and the first clock pre-divider are spent, the connection relationship of inside modules is: the signal output end of filter while and step-length
The data input pin of counting submodule is connected with the input end of clock of signal pre-divider, the output terminal of clock of signal pre-divider
It is connected with the data input pin of the speed detector；The input end of clock of the speed detector divides in advance with the first clock
The output terminal of clock of device is connected；Signal input part of the signal input part of filter as PWM sample detecting module, the speed
Spend output end of the speed signal output end of detector as PWM sample detecting module.The signal input part of filter is for catching
Obtain the pwm signal PWM_IN to be processed of input, the height of the clock input external system clock generator output of filter
Frequency clock signal clk _ US, and under the driving effect of high frequency clock signal CLK_US, control pwm signal PWM_IN mistake to be processed
Filter, then from the signal output end outputting reference pwm signal Encoder of filter.Due to high frequency clock signal CLK_US be can be with
Configuration, so, the mistake of the level dither signal of distinct pulse widths in pwm signal PWM_IN to be processed may be implemented in the filter
Filter operation.The signal output end of filter simultaneously with the data input pin of step-length counting submodule and the clock of signal pre-divider
Input terminal connection, for benchmark pwm signal Encoder to be transferred to step-length counting submodule and signal pre-divider；Signal is pre-
Frequency divider is used for received benchmark pwm signal Encoder scaling down processing to export the first pwm signal Encoder1, wherein institute
State the frequency divider that 2 frequency dividings, 4 frequency dividings or 8 frequency dividings were supported and be can be configured to signal pre-divider；The clock of the signal pre-divider
Output end is connected with the data input pin of the speed detector, described for the first pwm signal Encoder1 to be transferred to
Speed detector, to export the first pwm signal Encoder1 of different frequency to the speed detector.First clock divides in advance
Frequency device, the sampling clock Clk for controlling and receiving divide to obtain the first sub-frequency clock signal Clk_div1, and when by the first frequency dividing
Clock signal Clk_div1 is exported to speed detector, and under the present embodiment, the frequency division coefficient of the first clock pre-divider is configured to
16.The input end of clock of the speed detector is connected with the output terminal of clock of the first clock pre-divider, the speed
Detector is spent under the driving effect of the first sub-frequency clock signal Clk_div1, passes through the first pwm signal Encoder1's of detection
Corresponding first sub-frequency clock signal Clk_div1 in each pulse period of the rising edge to count the first pwm signal Encoder1
Pulse number, the speed detector is using the first sub-frequency clock signal Clk_div1 come to the first pwm signal Encoder1
Sample detecting is carried out, and the pulse number is subjected to intermediate value average treatment, completes the noise reduction process of the pulse number, then
Output obtains impulse speed signal speed, reduces noise signal to the impulse speed measured value of pwm signal PWM_IN to be processed
It influences, so that the impulse speed signal of higher precision is provided for external electric system, so as to the feedback of the revolving speed of electric system
Signal.Due to output end of the speed signal output end as the PWM sample detecting module of the speed detector, so
The speed signal output end of the speed detector exports impulse speed signal speed.
The filter includes the d type flip flop and a comparison output module of the first preset quantity, the D of the first preset quantity
Trigger constitutes the shift register of a first preset quantity bit, and the clock end of the d type flip flop of the first preset quantity connects
It is connected to the input end of clock of the filter, the output end (Q) of the d type flip flop of the first preset quantity, which is connected respectively to, compares output
The data input pin of first preset quantity of module, signal input part of the data input pin of shift register as filter,
Compare signal output end of the data output end as filter of output module.Under the present embodiment, first preset quantity
6 are set as, as shown in figure 4, the filter includes the first d type flip flop D1, the second d type flip flop D2, third d type flip flop D3, the
Four d flip-flop D4, the 5th d type flip flop D5, the 6th d type flip flop D6 and a comparison output module, aforementioned 6 d type flip flops are constituted
The clock end of the shift register of one 6 bit, aforementioned 6 d type flip flops all accesses high frequency clock signal CLK_US, the first D
The output end Q [0] of trigger D1, the output end Q [1] of the second d type flip flop D2, the output end Q [2] of third d type flip flop D3, the 4th
The output end Q [3] of d type flip flop D4, the output end Q [5] of the output end Q [4] and the 6th d type flip flop D6 of the 5th d type flip flop D5 divide
It is not connected to 6 data input pins for comparing output module, the data output end of the relatively output module is described for exporting
Benchmark pwm signal Encoder, to guarantee the stability of the PWM sample detecting module.
As one embodiment, each D triggering in the shift register, other than the d type flip flop of rightmost
The output of device terminates to the input terminal of one d type flip flop in the right, and the output end access of the d type flip flop of rightmost is described relatively to be exported
One data input pin of module, data input pin of the input terminal of leftmost d type flip flop as shift register.Such as Fig. 4
Shown, the data in the shift register successively move to right by turn under the driving effect of the high frequency clock signal CLK_US
When, the output of each d type flip flop other than the 6th d type flip flop D6 terminates to the input terminal D of one d type flip flop in the right, the
The input terminal D of one d type flip flop D1 accesses the pwm signal PWM_IN to be processed.
As another embodiment, each D touching in the shift register, other than leftmost d type flip flop
The output of hair device terminates to the input terminal of one d type flip flop in the left side, and the output end access of leftmost d type flip flop is described more defeated
A data input pin of module out, when the data in the shift register are in the driving of the high frequency clock signal CLK_US
When successively moving to left by turn under effect, the output end Q of each d type flip flop other than leftmost d type flip flop is connected to the left side one
The input terminal D of the input terminal D of a d type flip flop, the d type flip flop of rightmost access the pwm signal PWM_IN to be processed.
The shift register can not only registered data, and can make under the action of the high frequency clock signal CLK_US
Data therein are successively moved to left or are moved to right.Because since being added on trigger the rising edge of the high frequency clock signal CLK_US
One section of delay time is steadily set up to output end new state, so when the high frequency clock signal CLK_US adds simultaneously
When on to the d type flip flop of first preset quantity, received each d type flip flop is one, the left side (or the right) d type flip flop
In original data, then the data in the shift register successively move to right (or moving to left) one.
The internal logic relationship of the relatively output module are as follows: when 6 data input pins of the relatively output module are complete
When being 0, i.e., when corresponding 6 bit signal Q [5:0]=0 of the output end of 6 triggers, the institute of the relatively output module output
Stating benchmark pwm signal Encoder is low level；When 6 data input pins of the relatively output module are all 1, i.e., 6 touchings
When sending out corresponding 6 bit signal Q [5:0]=6 ' b111111 of output end of device, the base of the relatively output module output
Quasi- pwm signal Encoder is high level；When existing 0 in the relatively data input pin of the first preset quantity of output module
When also having 1, i.e. Q [5:0]！=0 and Q [5:0]！When=6 ' b111111, the benchmark PWM letter of the relatively output module output
It is constant that number Encoder retains original level state.
Preferably, first preset quantity is set as 6, so that the filter is by the pwm signal PWM_ to be processed
Level shake in IN less than 5 clock cycle is all filtered as burr, wherein the clock cycle is described to be processed
The pulse period of the jitter levels of pwm signal PWM_IN.If the pwm signal PWM_IN to be processed, which exists, is less than one fixed width
Pulse needs filter out, when needing to filter out such as the jitter levels pulse of 1uS, the filter can be by 6 delay times
The d type flip flop of 0.2us and a relatively output module are constituted, and the d type flip flop that 6 delay times are 0.2us constitutes one 6
The shift register of bit.Before disappearing to the pwm signal PWM_IN to be processed and trembling, the first of the relatively output module
The input terminal of preset quantity is all ones or all zeroes, and the benchmark pwm signal Encoder of the relatively output module output is accordingly
For high level or low level；It is trembled period disappearing to the pwm signal PWM_IN to be processed, the first of the relatively output module is pre-
If the input terminal of quantity had not only had 1 there are 0, the benchmark pwm signal Encoder of the relatively output module output is protected
It stays original level state constant, is stable level signal during can determine that this.To the pwm signal PWM_IN to be processed
Disappear after trembling, the input terminal of relatively first preset quantity of output module is all ones or all zeroes, and the relatively output module is defeated
The benchmark pwm signal Encoder out is accordingly high level or low level.So as to carry out noise suppression to input signal
Processing, the level shake less than 5 system clock cycles will be all filtered out, and the higher hamonic wave of the pwm signal of input is effectively reduced
Energy reduces the electromagnetic interference of external motor system, has very strong practicability.
Include step-length counter and direction register inside the step-length counting submodule, the output end of direction register with
The enable end of step-length counter connects.Output end of the terminal count output of step-length counter as the step-length counting submodule,
Data input pin of the counting input end of step-length counter as the step-length counting submodule.The direction register is for defeated
Add-subtract control signal out, as " adding " or the direction control signal of the switch of " subtracting ", the plus-minus of the direction register output
Control signal is connect with the step-length counter.If the add-subtract control signal is set to 1, the step-length counter is used for every
A pulse period is made plus 1 counts, and the step-length counting submodule detects a rising edge of the benchmark pwm signal Encoder
When signal, the step-length counter is since 0 plus 1 counts, while retaining built in current count value to the step-length counter
In register, to provide the step Numerical based on the pwm signal PWM_IN to be processed for external motor control system, electricity is represented
The distance value that machine rotates；After the count value of the step-length counter reaches maximum value, the step-length counter overflow is produced
The Tick pulse signal of a raw clock cycle, the step-length counter restarts from 0 plus 1 counts.If the add-subtract control
When signal is set to 0, the step-length counter is used to make the counting that subtracts 1, the step-length counting submodule detection in each pulse period
When a rising edge signal of the benchmark pwm signal Encoder, the step-length counter is made to subtract 1 since pre-set count value
It counts, while retaining in the register built in current count value to the step-length counter, to be external motor control system
Step Numerical based on the pwm signal PWM_IN to be processed is provided, the distance value of motor rotation is represented；When the step-length counter
Count value be reduced to 0 after, the step-length counter overflow (i.e. current count value is 0) generates the Tick of a clock cycle
Pulse signal, the step-length counter load the pre-set count value, then restart to subtract 1 counting.
Preferably, the step-length counter in the step-length counting submodule is set as 32 digit counters, does not need pair
Count value makees Symbol processing.
As shown in figure 3, the PWM generation module includes second clock pre-divider and pwm signal generator, inside modules
Connection relationship be: the output terminal of clock of second clock pre-divider is connected with the data input pin of the pwm signal generator
It connects.Specifically, second clock pre-divider is connected with the first clock pre-divider in the PWM sample detecting module, uses
In reception sampling clock Clk；Second clock pre-divider, for by received sampling clock Clk scaling down processing to export second
Sub-frequency clock signal Clk_div2, under the present embodiment, the clock frequency of the second sub-frequency clock signal Clk_div2 be can be
72MHz, 40MHz, 20MHz or 10MHz.Second clock pre-divider is connected with pwm signal generator, for dividing second
Clock signal Clk_div2 is transferred to pwm signal generator；Pwm signal generator, for receiving reference level signal level,
And it is defeated according to the comparison result of the frequency division value of the second sub-frequency clock signal Clk_div2 and reference level signal level generation PWM
Signal PWM_OUT out, specifically, pwm signal generator will be at the second sub-frequency clock signal Clk_div2 frequency dividings by counter
Reason, then again compared with reference level signal level carries out level, when the frequency dividing of the second sub-frequency clock signal Clk_div2
When value is greater than the level value of reference level signal level, PWM output signal PWM_OUT is high level, otherwise, PWM output signal
PWM_OUT is low level.
As shown in figure 5, the pwm signal generator includes output frequency divider and comparator, the output frequency divider when
Clock output end input terminal compared with one of the comparator connects, and the input terminal of output frequency divider is raw as the pwm signal
The data input pin grown up to be a useful person, data output end of the output end of comparator as the pwm signal generator.The output frequency division
Device divides the second sub-frequency clock signal Clk_div2 for receiving the second sub-frequency clock signal Clk_div2
Frequency is handled.It include a counter inside the output frequency divider under the embodiment of the present invention, which is 10bit
The counter of bit wide, frequency division coefficient 1024, therefore the output frequency divider is by the second sub-frequency clock signal Clk_div2
1024 scaling down processings are carried out, when the clock frequency of the second sub-frequency clock signal Clk_div2 is 72MHz, the output point
The frequency division value of frequency device output is 72MHz/1024=70KHz, can be used as highest output frequency to be compared, so that the pwm signal
The signal of generator output is low-frequency PWM output signal as unit of KHz.
As shown in figure 5, the comparison input terminal of the comparator be separately connected the frequency division value of the output frequency divider with it is described
Reference level signal level, for the frequency division value and the reference level according to the second sub-frequency clock signal Clk_div2
The level comparison result of signal level exports the PWM output signal PWM_OUT of corresponding level, when the frequency dividing
When value is greater than the level value of the reference level signal level, PWM output signal PWM_OUT is high level；When the frequency division value
When level value less than the reference level signal level, PWM output signal PWM_OUT is low level.Due to the output point
The frequency division coefficient of frequency device and the second sub-frequency clock signal Clk_div2 of input are adjustable, thus PWM export letter
The duty ratio of number PWM_OUT is controllable, while the PWM generation module also generates interrupt signal output, and the PWM is assisted to adopt
The revolving speed of electric system outside the control of sample detection module.
A kind of chip, the chip interior integrate aforementioned processing circuit, and the processing circuit includes the PWM sample detecting mould
Block and the PWM generation module；The pwm signal PWM_IN to be processed of the PWM sample detecting module capture chip exterior input,
The high frequency clock signal CLK_US of the system clock generator output of chip interior is received, and to chip exterior output based on wait locate
Manage the impulse speed signal speed of pwm signal.The PWM generation module is used to receive the system clock generator of chip interior
The sampling clock Clk of output, and the controllable PWM output signal PWM_OUT of the duty ratio based on sampling clock Clk is exported, it is described
PWM sample detecting module and the PWM generation module are commonly connected to the sampling clock Clk.Compared with the existing technology, the core
Piece is internally integrated aforementioned speed detector, and the chip is used to provide impulse sampling speed for external electric system.
Device embodiments described above are only schematical, wherein the unit as illustrated by the separation member
It may or may not be physically separated, component shown as a unit may or may not be physics list
Member, it can it is in one place, or may be distributed over multiple network units.It can be selected according to the actual needs
In some or all of the modules realize the purpose of present embodiment scheme.Those of ordinary skill in the art are not paying creation
Property labour in the case where, it can understand and implement.
Claims (11)
1. a kind of speed detector based on pwm signal, which is applied to provide pulse for external electric system
Sample rate, which is characterized in that speed detector includes rising edge detection circuit, pulsewidth counter and intermediate value averaging module；On
Rise and connect along the input end of clock of detection circuit with the input end of clock of pulsewidth counter, the output end of rising edge detection circuit and
The reset terminal (reset) of pulsewidth counter connects, and the data of the data output end connection intermediate value averaging module of pulsewidth counter are defeated
Enter end, the input terminal of output end of the data output end of intermediate value averaging module as speed detector, rising edge detection circuit is made
For the data input pin of speed detector.
2. speed detector according to claim 1, which is characterized in that the rising edge detection circuit includes a D triggering
Device and one and door, input terminal (D) connection and the input terminal of door of d type flip flop, d type flip flop reversed-phase output () even
Connect another input terminal with door；The clock end of the pulsewidth counter is connected with the clock end of d type flip flop, the output with door
Hold the output end as the rising edge detection circuit, input of the input terminal of d type flip flop as the rising edge detection circuit
End.
3. speed detector according to claim 2, which is characterized in that the bit wide numerical value power of the 2 pulsewidth counter
Greater than the ratio of the signal frequency of the input terminal of the signal frequency and d type flip flop of the input end of clock of the pulsewidth counter
Value.
4. a kind of processing circuit of pwm signal, which is applied to the electric system outside adjusting, which is characterized in that institute
Stating processing circuit includes PWM sample detecting module and PWM generation module；The input end of clock and PWM of PWM sample detecting module are raw
It is connected at the input end of clock of module；
PWM sample detecting module include step-length counting submodule, signal pre-divider, filter, the first clock pre-divider and
Any one of claims 1 to 3 speed detector, wherein the signal input part of filter is as PWM sample detecting module
Signal input part, output end of the speed signal output end of the speed detector as PWM sample detecting module；
The connection relationship of PWM sample detecting inside modules is: the signal output end of filter simultaneously with step-length counting submodule
Data input pin is connected with the input end of clock of signal pre-divider, and the output terminal of clock of signal pre-divider and the speed are examined
The data input pin for surveying device is connected；The output terminal of clock phase of the input end of clock of speed detector and the first clock pre-divider
Connection；
PWM generation module includes second clock pre-divider and pwm signal generator, and the connection relationship of inside modules is: second
The output terminal of clock of clock pre-divider is connected with the data input pin of pwm signal generator, second clock pre-divider
The data output end of input end of clock of the input end of clock as PWM generation module, pwm signal generator generates mould as PWM
The output end of block.
5. processing circuit according to claim 4, which is characterized in that the filter includes the D triggering of the first preset quantity
Device and a comparison output module, the displacement that the d type flip flop of the first preset quantity constitutes a first preset quantity bit are posted
Storage, the clock end of the d type flip flop of the first preset quantity are connected to the input end of clock of the filter, the first preset quantity
The output end (Q) of d type flip flop is connected respectively to the data input pin for comparing the first preset quantity of output module, shift register
Signal input part of the data input pin as filter, the data output end for comparing output module is defeated as the signal of filter
Outlet.
6. processing circuit according to claim 5, which is characterized in that in the shift register, in addition to the D touching of rightmost
The output end (Q) of each d type flip flop except hair device is connected to the input terminal (D) of one d type flip flop in the right, the D triggering of rightmost
One data input pin of output end (Q) access of the device relatively output module.
7. processing circuit according to claim 5, which is characterized in that in the shift register, in addition to leftmost D is touched
The output end (Q) of each d type flip flop except hair device is connected to the input terminal (D) of one d type flip flop in the left side, leftmost D triggering
One data input pin of output end (Q) access of the device relatively output module.
8. processing circuit according to claim 5, which is characterized in that first preset quantity is set as 6, so that the filter
Wave device is all filtered the level shake in the pwm signal to be processed (PWM_IN) of input less than 5 clock cycle as burr,
Wherein, the clock cycle is the pulse period of the jitter levels of the pwm signal to be processed (PWM_IN).
9. processing circuit according to claim 4, which is characterized in that include that step-length counts inside the step-length counting submodule
The output end of device and direction register, direction register is connect with the enable end of step-length counter, and the counting of step-length counter is defeated
The counting input end of output end of the outlet as the step-length counting submodule, step-length counter counts submodule as the step-length
The data input pin of block.
10. processing circuit according to claim 4, which is characterized in that the pwm signal generator include output frequency divider and
Comparator, the output terminal of clock of output frequency divider input terminal compared with one of comparator connect, the input terminal of output frequency divider
As the data input pin of the pwm signal generator, the output end of comparator is defeated as the data of the pwm signal generator
Outlet.
11. a kind of chip, which is characterized in that the chip interior includes any one of claim 4 to 10 processing circuit.
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| CN114441796A (en) * | 2022-02-10 | 2022-05-06 | 厦门乃尔电子有限公司 | Magnetoelectric revolution speed transducer with self-checking function and PFM modulation output |
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