CN203859711U - Engine rotating speed sampling and controlling circuit - Google Patents
Engine rotating speed sampling and controlling circuit Download PDFInfo
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- CN203859711U CN203859711U CN201420289434.3U CN201420289434U CN203859711U CN 203859711 U CN203859711 U CN 203859711U CN 201420289434 U CN201420289434 U CN 201420289434U CN 203859711 U CN203859711 U CN 203859711U
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Abstract
The utility model discloses an engine rotating speed sampling and controlling circuit. The engine rotating speed sampling and controlling circuit comprises a first counter, a second counter, a register, a combinational logic circuit and a controller. The first counter is electrically connected with the second counter, the register and the controller. The second counter is electrically connected with the register, the combinational logic circuit and the controller. The controller is electrically connected with the register and the combinational logic circuit. According to the engine rotating speed sampling and controlling circuit, the value of the engine rotating speed can be calculated, and whether the rotating speed is in a normal range, that is to say whether the rotating speed is between the maximum rotating speed and the minimum rotating speed, can also be directly determined; and two paths of sampling signals are compared by the controller, two pulse width modulation signals with different duty ratios are generated, an external motor can be controlled to accelerate and decelerate without CPU, and rotating speed precision can be ensured.
Description
Technical field
The utility model relates to engine speed Sampling techniques field, relates in particular to a kind of engine speed sampling and control circuit.
Background technology
Rotating speed is one of important parameter of engine, and the acquisition and processing of tach signal is an important process of engine.But, the tach signal that tradition rotating speed sample mode is just returned to sampling calculates, the size of pure calculating rotating speed, also cannot ensure the precision of the rotating speed calculating, only after rotating speed size, could judge that current rotating speed is whether in the normal range of speeds of engine calculating, speed is slow, and in the time finding that rotating speed is improper, be all often to control external motor acceleration or deceleration by central processing unit (CPU), implementation procedure is comparatively complicated.
Utility model content
The purpose of this utility model is to sample and control circuit by a kind of engine speed, solves the problem that above background technology part is mentioned.
For reaching this object, the utility model by the following technical solutions:
A kind of engine speed sampling and control circuit, it comprises the first counter, the second counter, register, combinational logic circuit and controller; Wherein, described the first counter and the second counter, register, controller are electrically connected, and for the first tach signal, second tach signal of input are sampled, obtain the first sampled signal; Described the second counter and register, combinational logic circuit, controller are electrically connected, and for to the first tach signal, second tach signal of input are sampled, obtain the second sampled signal; Described controller and register, combinational logic circuit are electrically connected, and for the count value of the first counter and the second counter is compared, produce the pulse-width signal of two different duty ratios, control external motor and accelerate, slow down.
The sampling of engine speed that the utility model provides and control circuit can not only calculation engine rotating speed size, can also directly judge that rotating speed is whether in a normal interval, whether between maximum (top) speed and minimum speed, and by controller, two-way sampled signal is compared, produce pulse-width modulation (PWM) signal of two different duty ratios, can control external motor without CPU and accelerate, slow down, ensure rotary speed precision.
Brief description of the drawings
Engine speed sampling and control circuit structure chart that Fig. 1 provides for the utility model embodiment;
The first counter works flow chart that Fig. 2 provides for the utility model embodiment;
The second counter works flow chart that Fig. 3 provides for the utility model embodiment;
The oscillogram of the first sampled signal under the rated speed that Fig. 4 a provides for the utility model embodiment;
The oscillogram of the second sampled signal under the rated speed that Fig. 4 b provides for the utility model embodiment;
The oscillogram of the second sampled signal higher than maximum (top) speed that Fig. 4 c provides for the utility model embodiment.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the utility model, but not to restriction of the present utility model.It also should be noted that, for convenience of description, in accompanying drawing, only show the part relevant to the utility model but not full content.
Please refer to shown in Fig. 1 engine speed sampling and control circuit structure chart that Fig. 1 provides for the utility model embodiment.
In the present embodiment, engine speed sampling and control circuit specifically comprise the first counter, the second counter, register, combinational logic circuit and controller.
Described the first counter and the second counter, register, controller are electrically connected, and for the first tach signal, second tach signal of input are sampled, obtain the first sampled signal.The first sampled signal is that the first tach signal and the second tach signal are sampled, and the process of sampling completes by the first counter and combinational logic circuit.
As shown in Figure 2, the first counter works flow process is as follows: the first counter starts as reset mode, initial value is Min, the D end of first sampled signal of now holding as trigger Q is 1, and the second tach signal is as the clock of the first sampled signal, so after the second tach signal rising edge comes, the first sampled signal is sampled.After the first sampled signal is height, the first counter reset signal removes, and starts counting, and when the first counter meter is to Max (maximum), now the D of the first sampled signal end is 0.After the rising edge of the first tach signal comes, the D end of the first sampled signal becomes 1, then wait until the rising edge of the second tach signal, the first sampled signal starts again sampling, the time of sampling is (Max-Min) * T, Max is the maximum of the first rolling counters forward, and Min is the minimum value of the first rolling counters forward, the cycle that T is clock signal.In the present embodiment, the bit wide of the first counter is X, and initial value is Min, and count range is Min-Max, and count frequency determines by clock signal, and the count cycle is above-mentioned (Max-Min) * T.The size of bit wide X can arrange flexibly according to different requirements.
Described the second counter and register, combinational logic circuit, controller are electrically connected, and for to the first tach signal, second tach signal of input are sampled, obtain the second sampled signal.The second sampled signal is also that the first tach signal and the second tach signal are sampled, and difference is that it is mainly that a certain section of tach signal is located to sample.
As shown in Figure 3, under the workflow diagram of the second counter: after system reset, the second counter is initial state Max, now counting enables invalidly, and the second counter keeps initial value always.When the first rolling counters forward is to Max, the second counter is cleared, and counting enables effectively simultaneously, and the second counter starts counting, and now the second sampled signal is output as high level.When the second rolling counters forward is during to Max, it is invalid that the second rolling counters forward enables, and stops counting.In the second rolling counters forward course of work, the second sampled signal is high level always, only has in the time that the second counter can not count up to Max, and the second sampled signal is output low level.In the present embodiment, the bit wide of the second counter is Y, and initial value is Max, and count range is Min-Max, and count frequency determines by clock signal, and the count cycle is above-mentioned (Max-Min) * T.The size of bit wide Y can arrange flexibly according to different requirements.
Described controller and register, combinational logic circuit are electrically connected, and for the count value of the first counter and the second counter is compared, produce the pulse-width signal of two different duty ratios, control external motor and accelerate, slow down.
The utility model can complete the sampling to the first tach signal and the second tach signal, obtains the first sampled signal, and the tach signal sampling is processed again, obtains the second sampled signal.The second sampled signal is the in the situation that of different rotating speeds, waveform only has a low level in one-period, when exceeding after certain rotating speed, waveform there will be plural low level in one-period, and lower than after certain rotating speed, waveform does not have low level in one-period, so reading after sampled signal, need not calculate the size of rotating speed, according to low level number, just can directly judge that whether it is in the normal range of speeds of engine, very fast.Controller compares two-way sampled signal, produce pulse-width modulation (PWM) signal of two different duty ratios, can directly control external motor without CPU, when engine is during higher than the fastest rotating speed or lower than low-rotate speed, pwm signal control external motor, realizes and slows down and accelerate.In addition, by adjusting the bit wide of the first counter and the second counter, can change this interval of maximum (top) speed and minimum speed, meet different demands.
After engine speed sampling and control circuit design, carry out emulation by ModelSim (emulation tool), the oscillogram obtaining by emulation is carried out the effect of proof scheme design, and Fig. 4 a is the oscillogram of the first sampled signal under rated speed; Fig. 4 b is the oscillogram of the second sampled signal under rated speed; Fig. 4 c is the oscillogram higher than the second sampled signal of maximum (top) speed.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.Skilled person in the art will appreciate that the utility model is not limited to specific embodiment described here, can carry out for a person skilled in the art various obvious variations, readjust and substitute and can not depart from protection range of the present utility model.Therefore, although the utility model is described in further detail by above embodiment, but the utility model is not limited only to above embodiment, in the situation that not departing from the utility model design, can also comprise more other equivalent embodiment, and scope of the present utility model is determined by appended claim scope.
Claims (1)
1. engine speed sampling and a control circuit, is characterized in that, comprises the first counter, the second counter, register, combinational logic circuit and controller; Wherein, described the first counter and the second counter, register, controller are electrically connected, and for the first tach signal, second tach signal of input are sampled, obtain the first sampled signal; Described the second counter and register, combinational logic circuit, controller are electrically connected, and for to the first tach signal, second tach signal of input are sampled, obtain the second sampled signal; Described controller and register, combinational logic circuit are electrically connected, and for the count value of the first counter and the second counter is compared, produce the pulse-width signal of two different duty ratios, control external motor and accelerate, slow down.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420289434.3U CN203859711U (en) | 2014-05-30 | 2014-05-30 | Engine rotating speed sampling and controlling circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420289434.3U CN203859711U (en) | 2014-05-30 | 2014-05-30 | Engine rotating speed sampling and controlling circuit |
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| CN203859711U true CN203859711U (en) | 2014-10-01 |
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| CN201420289434.3U Active CN203859711U (en) | 2014-05-30 | 2014-05-30 | Engine rotating speed sampling and controlling circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113422549A (en) * | 2021-06-29 | 2021-09-21 | 四川中微芯成科技有限公司 | PWM wave processing method of motor, motor control panel, motor and motor system |
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2014
- 2014-05-30 CN CN201420289434.3U patent/CN203859711U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113422549A (en) * | 2021-06-29 | 2021-09-21 | 四川中微芯成科技有限公司 | PWM wave processing method of motor, motor control panel, motor and motor system |
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