CN209170328U - PWM generative circuit, processing circuit and chip - Google Patents
PWM generative circuit, processing circuit and chip Download PDFInfo
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- CN209170328U CN209170328U CN201822060361.1U CN201822060361U CN209170328U CN 209170328 U CN209170328 U CN 209170328U CN 201822060361 U CN201822060361 U CN 201822060361U CN 209170328 U CN209170328 U CN 209170328U
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Abstract
The utility model discloses a kind of PWM generative circuit, processing circuit and chip, the PWM generative circuit is applied to the revolving speed of the electric system outside control, it is characterized in that, the PWM generative circuit includes second clock pre-divider and pwm signal generator, and the data input pin of the frequency division output terminal connection pwm signal generator of second clock pre-divider is connected；Wherein, the pwm signal generator includes output frequency divider and comparator, the output terminal of clock of output frequency divider input terminal compared with one of the comparator connects, which exports the pwm signal of different duty on the basis of reducing complex software process.
Description
Technical field
The utility model relates to signal modulation technique field, it is related to a kind of PWM generative circuit, processing circuit and chip.
Background technique
PWM (Pulse Width Modulation) technology is in industrial automation, robot, precise numerical control machine, boat
The numerous areas such as empty space flight are used widely.Servo control system needs to generate the pwm signal driving of variable duty ratio
IGBT, IPM constant power device；The kinetic control systems such as robot or numerically-controlled machine tool can between motion control card and servo-driver
Pass through the pwm signal of changeable frequency, transmission location control instruction.
PWM and PFM is two kinds of control modes of DC/DC switch, and this kind of technology is usually used in some analog circuits or periphery electricity
Machine is controlled.As the integrated level of IC is higher and higher.There are many kinds of implementations for most pwm circuit on the market, there is one
It is realized a bit by the peripheral components such as square-wave oscillator or single limit comparator.In the architecture design of prior art PWM, output
For PWM signal by CPU timing control, software interrupt process is complex, wastes a large amount of software resources.
Utility model content
In order to overcome the problems referred above, the utility model proposes a kind of PWM generative circuits.
A kind of PWM generative circuit, the PWM generative circuit are applied to the revolving speed of the electric system outside control, and PWM generates electricity
Road includes second clock pre-divider and pwm signal generator, and the frequency division output terminal of second clock pre-divider connects pwm signal
The data input pin of generator is connected；Pwm signal generator includes output frequency divider and comparator, a comparison of comparator
The connection of the output terminal of clock of input terminal and output frequency divider, another comparison input terminal of comparator are connect with reference to constant pressure source,
Data input pin of the input terminal of output frequency divider as the pwm signal generator, the signal output end of comparator is as PWM
The comparison result output end of generative circuit.
Further, the frequency division coefficient of the second clock pre-divider is configurable.
A kind of processing circuit of pwm signal, the processing circuit are applied to the electric system outside adjusting, the processing circuit packet
Include PWM sample detecting module and PWM generation module；The input end of clock of PWM sample detecting module and the clock of PWM generation module
Input terminal is connected；Pwm signal sample detecting module includes filter, step-length counting submodule, signal pre-divider, speed inspection
Survey device and the first clock pre-divider, wherein the signal input part of filter is believed as the PWM of pwm signal sample detecting module
Number input terminal；The connection relationship of pwm signal sample detecting inside modules is: the signal output end of filter is counted with step-length simultaneously
The data input pin of submodule is connected with the input end of clock of signal pre-divider, the output terminal of clock and speed of signal pre-divider
The data input pin of degree detector is connected；The clock output of the input end of clock of speed detector and the first clock pre-divider
End is connected, output end of the speed signal output end of speed detector as pwm signal sample detecting module；PWM generates mould
Block includes the PWM generative circuit, wherein ratio of the comparison result output end of the PWM generative circuit as PWM generation module
Compared with result output end.
Further, the filter includes the d type flip flop and a comparison output module of the first preset quantity, and first is pre-
If the d type flip flop of quantity constitutes the shift register of a first preset quantity bit, the d type flip flop of the first preset quantity
Clock end is connected to the input end of clock of the filter, and the output end Q of the d type flip flop of the first preset quantity is connected respectively to ratio
Compared with the data input pin of the first preset quantity of output module, the data input pin of shift register is defeated as the signal of filter
Enter end, compares signal output end of the data output end as filter of output module.
Further, in the shift register, each d type flip flop other than the d type flip flop of rightmost it is defeated
The input terminal of one d type flip flop in the right is terminated to out, and the output end of the d type flip flop of rightmost accesses the relatively output module
One data input pin, data input pin of the input terminal of leftmost d type flip flop as shift register.
Further, in the shift register, each d type flip flop other than leftmost d type flip flop it is defeated
The input terminal of one d type flip flop in the left side is terminated to out, and the output end of leftmost d type flip flop accesses the relatively output module
One data input pin, data input pin of the input terminal of the d type flip flop of rightmost as shift register.
Further, first preset quantity is set as 6, so that the filter is by the pwm signal to be processed of input
Level shake in PWM_IN less than 5 clock cycle is all filtered as burr, wherein the clock cycle is described wait locate
Manage the pulse period of the jitter levels of pwm signal PWM_IN.
It further, include step-length counter and direction register, direction register inside the step-length counting submodule
Output end connect with the enable end of step-length counter, the terminal count output of step-length counter is as the step-length counting submodule
Output end, data input pin of the counting input end of step-length counter as the step-length counting submodule.
Further, the speed detector includes rising edge detection circuit, pulsewidth counter and intermediate value averaging module；On
It rises and includes a d type flip flop and one and door, the input terminal D connection of d type flip flop and an input terminal of door, D along detection circuit
The reversed-phase output of triggerAnother input terminal of connection and door；The clock end of pulsewidth counter and the clock end of d type flip flop
It is connected, rising edge detection circuit with the output end of door with the reset terminal reset of pulsewidth counter by connecting, pulsewidth counter
Data output end connection intermediate value averaging module data input pin, the output end of intermediate value averaging module is as the velocity measuring
The speed signal output end of device, data input pin of the input terminal of rising edge detection circuit as the speed detector.
Further, the clock that the bit wide numerical value power of the 2 pulsewidth counter is greater than the pulsewidth counter inputs
The ratio of the signal frequency of the input terminal D of the signal frequency at end and the d type flip flop.
A kind of chip, the chip interior include the processing circuit.
Compared with prior art, the external sampling clock Clk exported is received by the PWM generative circuit, and exports base
In the controllable PWM output signal PWM_OUT of the duty ratio of sampling clock Clk to adjust external electric system, CPU ginseng is not needed
It is operated with scaling down processing is adjusted, reduces the complexity of software control process.
Detailed description of the invention
Fig. 1 is a kind of PWM generative circuit structural schematic diagram of the utility model embodiment.
Fig. 2 is the circuit diagram of the pwm signal generator of the utility model embodiment.
Fig. 3 is a kind of processing circuit structural schematic diagram of pwm signal of the utility model embodiment.
Fig. 4 is the circuit diagram of the filter of the utility model embodiment.
Fig. 5 is the circuit diagram of the speed detector of the utility model embodiment.
Fig. 6 is that the filtering of the utility model embodiment disappears the sampling time sequence figure of the pwm signal pulsewidth trembled.
Specific embodiment
Specific embodiment of the present utility model is described further with reference to the accompanying drawing: as shown in Figure 1, this is practical new
Type embodiment provides a kind of PWM generative circuit, as shown in Figure 1, the PWM generative circuit include second clock pre-divider and
The connection relationship of pwm signal generator, inside modules is: second clock pre-divider is connected with the PWM sample detecting module
It connects, specifically, second clock pre-divider is connected with the first clock pre-divider in the PWM sample detecting module, uses
In reception sampling clock Clk；Second clock pre-divider, for by received sampling clock Clk scaling down processing to export second
Sub-frequency clock signal Clk_div2, under the present embodiment, the clock frequency of the second sub-frequency clock signal Clk_div2 be can be
72MHz, 40MHz, 20MHz or 10MHz.Second clock pre-divider is connected with pwm signal generator, for dividing second
Clock signal Clk_div2 is transferred to pwm signal generator；Pwm signal generator, for receiving reference level signal level,
And it is defeated according to the comparison result of the frequency division value of the second sub-frequency clock signal Clk_div2 and reference level signal level generation PWM
Signal PWM_OUT out, specifically, pwm signal generator will be at the second sub-frequency clock signal Clk_div2 frequency dividings by counter
Reason, then again compared with reference level signal level carries out level, when the frequency dividing of the second sub-frequency clock signal Clk_div2
When value is greater than the level value of reference level signal level, PWM output signal PWM_OUT is high level, otherwise, PWM output signal
PWM_OUT is low level, exports PWM output signal PWM_OUT in the comparison result output end of the PWM generative circuit.
As shown in Fig. 2, the pwm signal generator includes output frequency divider and comparator, one of comparator is more defeated
Enter end to connect with the output terminal of clock of the output frequency divider, another comparison input terminal and reference constant pressure source of comparator connect
It connects, data input pin of the input terminal of output frequency divider as the pwm signal generator, the signal output end conduct of comparator
The comparison result output end of the PWM generative circuit provides the reference level signal level with reference to constant pressure source.The output
Frequency divider for receiving the second sub-frequency clock signal Clk_div2, and to the second sub-frequency clock signal Clk_div2 into
Row scaling down processing.It include a counter, counter configuration inside the output frequency divider under the utility model embodiment
For the counter of 10bit bit wide, frequency division coefficient 1024, therefore the output frequency divider is by second sub-frequency clock signal
Clk_div2 carries out 1024 scaling down processings, when the clock frequency of the second sub-frequency clock signal Clk_div2 is 72MHz, institute
The frequency division value for stating output frequency divider output is 72MHz/1024=70KHz, can be used as highest output frequency to be compared, so that institute
Stating the signal that pwm signal generator exports is low-frequency PWM output signal as unit of KHz.
As shown in Fig. 2, the output terminal of clock of a comparison input terminal and the output frequency divider due to the comparator
Connection, another comparison input terminal of the comparator is connect with described with reference to constant pressure source, so the comparator is more defeated
Enter frequency division value and the reference level signal level that end is separately connected the output frequency divider, for according to described second point
The level comparison result of the frequency division value of frequency clock signal Clk_div2 and the reference level signal level, output correspond to
Level PWM output signal PWM_OUT, when the frequency division value be greater than the reference level signal level level value
When, PWM output signal PWM_OUT is high level；When the frequency division value is less than the level value of the reference level signal level
When, PWM output signal PWM_OUT is low level.Due to the frequency division coefficient of the output frequency divider and described second point of input
Frequency clock signal Clk_div2 is adjustable, thus the duty ratio of PWM output signal PWM_OUT be controllable, while institute
It states PWM generative circuit and also generates interrupt signal output, assist turning for the electric system outside the PWM sample detecting module control
Speed.
The utility model embodiment also provides a kind of processing circuit of pwm signal, and the processing circuit includes PWM sampling inspection
Survey module and the PWM generation module；The PWM generation module includes the PWM generative circuit, in the utility model embodiment
Under, the inside connection relationship of the PWM generative circuit is equal to the connection relationship inside the PWM generation module.
The input end of clock of the PWM sample detecting module is connected with the input end of clock of the PWM generation module；Institute
The pwm signal input terminal for stating PWM sample detecting module is used to capture the pwm signal PWM_IN to be processed of input, the PWM sampling
The input end of clock of detection module is used to receive the high frequency clock signal CLK_US of external system clock generator output, in this reality
With under new embodiment, the frequency range of pwm signal PWM_IN to be processed is greater than 32Hz and is less than 2KHz, external system clock
The high frequency clock signal CLK_US of generator output is the clock signal for being 0.2us in the period, is sent out by the counter of corresponding precision
Signal is waved to disappear the effect of trembling；The PWM sample detecting module is for exporting the impulse speed signal based on pwm signal to be processed
Speed and corresponding pulse step size signal are used for external electric system as feedback quantity.Compared with the existing technology, it expands
The application function of pwm signal output circuit.The PWM generation module is used to receive the sampling of external system clock generator output
Clock Clk, and export the controllable PWM output signal PWM_OUT of the duty ratio based on sampling clock Clk；The PWM sample detecting
Module and the PWM generation module are commonly connected to the sampling clock Clk；Wherein, sampling clock Clk can also be from outer
Bus clock on the ahb bus in portion, corresponding clock frequency size includes 80MHz, 40MHz or 20MHz, so that the PWM
Output signal PWM_OUT meets the application demand of various electric machine control systems.When the PWM sample detecting module is external electricity
When machine system provides impulse speed signal speed and corresponding pulse step size signal, external electric system is according to aforementioned sample
Signal is adjusted, and specifically adjusts frequency size, pwm signal PWM_IN to be processed and the high frequency of the sampling clock Clk of output
Then clock signal clk _ US controls the PWM output signal PWM_OUT of the PWM generation module output duty ratio corresponding, with complete
The rotational speed regulation control of pairs of external motor system.
As shown in figure 3, the PWM sample detecting module include filter, step-length counting submodule, signal pre-divider,
The signal input part of speed detector and the first clock pre-divider, filter is believed as the PWM of pwm signal sample detecting module
Number input terminal, output end of the speed signal output end of speed detector as pwm signal sample detecting module；The PWM is adopted
Connection relationship inside sample detection module is: the signal output end of filter while the data input pin with step-length counting submodule
It is connected with the input end of clock of signal pre-divider, the output terminal of clock of signal pre-divider and the data of speed detector input
End is connected；The input end of clock of speed detector is connected with the output terminal of clock of the first clock pre-divider；Filter
Signal input part is used to capture the pwm signal PWM_IN to be processed inputted, when the clock input external system of filter
The high frequency clock signal CLK_US of clock generator output, and under the driving effect of high frequency clock signal CLK_US, it controls wait locate
Pwm signal PWM_IN filtering is managed, then from the signal output end outputting reference pwm signal Encoder of the filter.
Since high frequency clock signal CLK_US can be configured, so, PWM letter to be processed may be implemented in the filter
The filter operation of the level dither signal of distinct pulse widths in number PWM_IN.The signal output end of filter counts son with step-length simultaneously
The data input pin of module is connected with the input end of clock of signal pre-divider, for benchmark pwm signal Encoder to be transferred to
Step-length counting submodule and signal pre-divider；Signal pre-divider is used for will be at received benchmark pwm signal Encoder frequency dividing
Reason is to export the first pwm signal Encoder1, wherein 2 frequency dividings, 4 frequency dividings or 8 are supported and be can be configured to the signal pre-divider
The frequency divider of frequency dividing；The output terminal of clock of the signal pre-divider is connected with the data input pin of the speed detector,
For the first pwm signal Encoder1 to be transferred to the speed detector, to export the first pwm signal of different frequency
Encoder1 is to the speed detector.First clock pre-divider, the sampling clock Clk for controlling and receiving divide to obtain
One sub-frequency clock signal Clk_div1, and the first sub-frequency clock signal Clk_div1 is exported to speed detector, in this implementation
Under example, the frequency division coefficient of the first clock pre-divider is configured to 16.The input end of clock of the speed detector and described first
The output terminal of clock of clock pre-divider is connected, driving of the speed detector in the first sub-frequency clock signal Clk_div1
Under effect, each pulse of the first pwm signal Encoder1 is counted by detecting the rising edge of the first pwm signal Encoder1
The pulse number of corresponding first sub-frequency clock signal Clk_div1 in period, the speed detector use the first frequency-dividing clock
Signal Clk_div1 to carry out the first pwm signal Encoder1 sample detecting, and pulse number progress intermediate value is averaged
The noise reduction process of the pulse number is completed in processing, is reduced noise signal and is surveyed to the impulse speed of pwm signal PWM_IN to be processed
The influence of magnitude, so that the impulse speed signal of higher precision is provided for external electric system, in order to provide electric system
The feedback signal of revolving speed.Since the speed signal output end of the speed detector is as the pwm signal sample detecting module
Output end, so the speed detector speed signal output end export impulse speed signal speed.
The filter includes the d type flip flop of the first preset quantity and a comparison output module, the filter include
The d type flip flop of first preset quantity and a comparison output module, the d type flip flop of the first preset quantity constitute one first and preset
The shift register of number of bits position, the clock that the clock end of the d type flip flop of the first preset quantity is connected to the filter are defeated
Enter end, the output end (Q) of the d type flip flop of the first preset quantity is connected respectively to the number for comparing the first preset quantity of output module
According to input terminal, signal input part of the data input pin of shift register as filter compares the data output of output module
Hold the signal output end as filter.Under the present embodiment, first preset quantity is set as 6, as shown in figure 4, described
Filter includes the first d type flip flop D1, the second d type flip flop D2, third d type flip flop D3, four d flip-flop D4, the 5th d type flip flop
D5, the 6th d type flip flop D6 and a comparison output module, aforementioned 6 d type flip flops constitute the shift register of 6 bits,
The clock end of aforementioned 6 d type flip flops all accesses high frequency clock signal CLK_US, the output end Q [0] of the first d type flip flop D1, second
The output end Q [1] of d type flip flop D2, the output end Q [2] of third d type flip flop D3, the output end Q [3] of four d flip-flop D4,
The output end Q [5] of the output end Q [4] and the 6th d type flip flop D6 of five d type flip flop D5, which are connected respectively to, compares 6 of output module
Data input pin, the data output end of the relatively output module is for exporting the benchmark pwm signal Encoder, to protect
Demonstrate,prove the stability of the PWM sample detecting module.
As one embodiment, each D triggering in the shift register, other than the d type flip flop of rightmost
The output of device terminates to the input terminal of one d type flip flop in the right, and the output end access of the d type flip flop of rightmost is described relatively to be exported
One data input pin of module, data input pin of the input terminal of leftmost d type flip flop as shift register.Such as Fig. 4
Shown, the data in the shift register successively move to right by turn under the driving effect of the high frequency clock signal CLK_US
When, the output of each d type flip flop other than the 6th d type flip flop D6 terminates to the input terminal D of one d type flip flop in the right, the
The input terminal D of one d type flip flop D1 accesses pwm signal PWM_IN to be processed.
As another embodiment, each D touching in the shift register, other than leftmost d type flip flop
The output of hair device terminates to the input terminal of one d type flip flop in the left side, and the output end access of leftmost d type flip flop is described more defeated
A data input pin of module out, when the data in the shift register are in the driving of the high frequency clock signal CLK_US
When successively moving to left by turn under effect, the output end Q of each d type flip flop other than leftmost d type flip flop is connected to the left side one
The input terminal D of the input terminal D of a d type flip flop, the d type flip flop of rightmost access the pwm signal PWM_IN to be processed.Because from
The rising edge of the high frequency clock signal CLK_US, which is added on trigger, to be started to output end new state steadily to have set up
One section of delay time, so when the high frequency clock signal CLK_US is added on the d type flip flop of first preset quantity simultaneously
When, received each d type flip flop is data original in the d type flip flop of one, the left side (or the right), then the shift LD
Data in device successively move to right (or moving to left) one.
The internal logic relationship of the relatively output module are as follows: when 6 data input pins of the relatively output module are complete
When being 0, i.e., when corresponding 6 bit signal Q [5:0]=0 of the output end of 6 triggers, the institute of the relatively output module output
Stating benchmark pwm signal Encoder is low level；When 6 data input pins of the relatively output module are all 1, i.e., 6 touchings
When sending out corresponding 6 bit signal Q [5:0]=6 ' b111111 of output end of device, the base of the relatively output module output
Quasi- pwm signal Encoder is high level；When existing 0 in the relatively data input pin of the first preset quantity of output module
When also having 1, i.e. Q [5:0]！=0 and Q [5:0]！When=6 ' b111111, the benchmark PWM letter of the relatively output module output
It is constant that number Encoder retains original level state.
Preferably, first preset quantity is set as 6, so that the filter is by the pwm signal PWM_ to be processed
Level shake in IN less than 5 clock cycle is all filtered as burr, wherein the clock cycle is described to be processed
The pulse period of the jitter levels of pwm signal PWM_IN.If the pwm signal PWM_IN to be processed, which exists, is less than one fixed width
Pulse needs filter out, when needing to filter out such as the jitter levels pulse of 1uS, the filter can be by 6 delay times
The d type flip flop of 0.2us and a relatively output module are constituted, and the d type flip flop that 6 delay times are 0.2us constitutes one 6
The shift register of bit.Before disappearing to the pwm signal PWM_IN to be processed and trembling, the first of the relatively output module
The input terminal of preset quantity is all ones or all zeroes, and the benchmark pwm signal Encoder of the relatively output module output is accordingly
For high level or low level；It is trembled period disappearing to the pwm signal PWM_IN to be processed, the first of the relatively output module is pre-
If the input terminal of quantity had not only had 1 there are 0, the benchmark pwm signal Encoder of the relatively output module output is protected
It stays original level state constant, is stable level signal during can determine that this.To the pwm signal PWM_IN to be processed
Disappear after trembling, the input terminal of relatively first preset quantity of output module is all ones or all zeroes, and the relatively output module is defeated
The benchmark pwm signal Encoder out is accordingly high level or low level.So as to carry out noise suppression to input signal
Processing, the level shake less than 5 system clock cycles will be all filtered out, and the higher hamonic wave of the pwm signal of input is effectively reduced
Energy reduces the electromagnetic interference of external motor system, has very strong practicability.
Include step-length counter and direction register inside the step-length counting submodule, the output end of direction register with
The enable end of step-length counter connects, output end of the terminal count output of step-length counter as the step-length counting submodule,
Data input pin of the counting input end of step-length counter as the step-length counting submodule.The direction register is for defeated
Add-subtract control signal out, as " adding " or the direction control signal of the switch of " subtracting ", the plus-minus of the direction register output
Control signal is connect with the step-length counter.If the add-subtract control signal is set to 1, the step-length counter is used for every
A pulse period is made plus 1 counts, and the step-length counting submodule detects a rising edge of the benchmark pwm signal Encoder
When signal, the step-length counter is since 0 plus 1 counts, while retaining built in current count value to the step-length counter
In register, to provide the step Numerical based on the pwm signal PWM_IN to be processed for external motor control system, electricity is represented
The distance value that machine rotates；After the count value of the step-length counter reaches maximum value, the step-length counter overflow is produced
The Tick pulse signal of a raw clock cycle, the step-length counter restarts from 0 plus 1 counts.If the add-subtract control
When signal is set to 0, the step-length counter is used to make the counting that subtracts 1, the step-length counting submodule detection in each pulse period
When a rising edge signal of the benchmark pwm signal Encoder, the step-length counter is made to subtract 1 since pre-set count value
It counts, while retaining in the register built in current count value to the step-length counter, to be external motor control system
Step Numerical based on the pwm signal PWM_IN to be processed is provided, the distance value of motor rotation is represented；When the step-length counter
Count value be reduced to 0 after, the step-length counter overflow (i.e. current count value is 0) generates the Tick of a clock cycle
Pulse signal, the step-length counter load the pre-set count value, then restart to subtract 1 counting.
Preferably, the step-length counter in the step-length counting submodule is set as 32 digit counters, does not need pair
Count value makees Symbol processing.
As shown in figure 5, the speed detector includes rising edge detection circuit, pulsewidth counter and intermediate value averaging module,
For realizing the velocity amplitude of measurement motor rotation by the period for measuring the pwm signal PWM_IN to be processed, actually
Measure the time width between two rising edges of the pwm signal PWM_IN to be processed.The rising edge detection circuit includes
One d type flip flop and one and door, the input terminal D connection of d type flip flop and an input terminal of door, the anti-phase output of d type flip flop
EndAnother input terminal of connection and door；The clock end of the pulsewidth counter is connected with the clock end of d type flip flop, described
Rising edge detection circuit is connect by described with the output end of door with the reset terminal reset of the pulsewidth counter.Pulsewidth counts
The data input pin of the data output end connection intermediate value averaging module of device, the output end of intermediate value averaging module are examined as the speed
Survey the speed signal output end of device, data input pin of the input terminal of rising edge detection circuit as the speed detector.D touching
For the input terminal D of hair device for receiving the first pwm signal Encoder1, the first pwm signal Encoder1 is the base
What quasi- pwm signal Encoder scaling down processing obtained；The clock end of d type flip flop is for receiving first sub-frequency clock signal
Clk_div1, the first sub-frequency clock signal Clk_div1 are that the high frequency clock signal CLK_US divides to obtain.When D is touched
The first pwm signal Encoder1 at the place input terminal D of device is sent out when the first moment is low level signal, d type flip flop latches the
Low level signal of the one pwm signal Encoder1 at the first moment, by the one of the first sub-frequency clock signal Clk_div1
After a clock cycle, the reversed-phase output of d type flip flopExport high level signal, if under synchronization d type flip flop input terminal
D becomes high level signal, i.e., is simultaneously high level signal with two input terminals of door, the rising edge detection circuit by with door
High level signal is exported, can determine that the first pwm signal Encoder1 is rising edge signal at this time, and export to the pulsewidth and count
The reset terminal reset of device.
Under the driving of the first sub-frequency clock signal Clk_div1, when the pulsewidth counter sample detecting is described in
When the rising edge signal of the first pwm signal Encoder1, counted the rising edge signal as reset signal input, often
A reset signal is inputted, the pulsewidth counter is according to the pulse number of the first sub-frequency clock signal Clk_div1
It counts once, thus when obtaining the corresponding described first frequency dividing in a pulse period of the first pwm signal Encoder1
The pulse number of clock signal Clk_div1.As shown in fig. 6, the pulsewidth counter often detects first pwm signal
A rising edge signal of Encoder1, the first sub-frequency clock signal Clk_div1 has passed over 4 clock cycle, described
Pulsewidth counter adds 4 on the basis of original count value, as current count value；The two of the first pwm signal Encoder1
Between a rising edge signal, the pulse number of the first sub-frequency clock signal Clk_div1 is 4, and the pulsewidth counter uses
The clock cycle of 4 the first sub-frequency clock signal Clk_div1 removes first pwm signal of one pulse period of sampling
Encoder1.In Fig. 6, confined 4 of the corresponding dotted line of two rising edge signals of the first pwm signal Encoder1
The pulse of the first sub-frequency clock signal Clk_div1, the mark as the pulsewidth for measuring the first pwm signal Encoder1
Standard, and then measure the corresponding motor speed of the pwm signal PWM_IN to be processed.Made under the conditions of the prior art using clock edge
The mode of energy signal drives the pulsewidth counter to be counted, but can have the nonsynchronous problem of clock, and the utility model is real
It applies example and drives the pulsewidth counter to the pulsewidth of the first pwm signal Encoder1 by the rising edge detection circuit
It counts, really drives the pulsewidth counter to be counted under high frequency clock signal by Edge check enable signal, make
Obtain the precision that clock is synchronous, and the pulse period of raising the first pwm signal Encoder1 samples.
Preferably, the bit wide numerical value power of the 2 pulsewidth counter is greater than the input end of clock of the pulsewidth counter
Signal frequency and the d type flip flop input terminal D signal frequency ratio.The first sub-frequency clock signal Clk_div1
Highest input frequency be 80MHz, the first sub-frequency clock signal Clk_div1 is set as under the utility model embodiment
20MHz.In order to realize that the first pwm signal Encoder1's described in the first sub-frequency clock signal Clk_div1 synchronized sampling is upper
It rises along signal, the ratio and the arteries and veins of the first sub-frequency clock signal Clk_div1 and the first pwm signal Encoder1
The bit wide of wide counter is there are power side's relationship, when the first pwm signal Encoder1 clock frequency is 32Hz, then described the
The clock frequency of one sub-frequency clock signal Clk_div1 and the ratio of the clock frequency of the first pwm signal Encoder1 are
625000.Because 2 20 power are bigger than 625000,20 bits are set by the bit wide of the pulsewidth counter, thus
The bit wide numerical value power for meeting the 2 pulsewidth counter is greater than the clock frequency of the first sub-frequency clock signal Clk_div1
With the ratio of the clock frequency of the first pwm signal Encoder1；Due to the high frequency clock signal CLK_US maximum clock
Frequency is 80MHz, is 4 times of 20MHz, so when the high frequency clock signal CLK_US mono- frequency dividing obtains the described first frequency dividing
Clock signal Clk_div1, and when the first pwm signal Encoder1 clock frequency is left as 32Hz, it need to be by the pulsewidth meter
The bit wide of number device increases 2 bits, and the bit wide numerical value is set as 22 bits, this is as the correlation built in the pulsewidth counter
Register carries out configuration of reservations, and loads corresponding bit wide numerical value under the premise of high frequency clock signal CLK_US input.
The frequency that the d type flip flop of the rising edge detection circuit receives the first sub-frequency clock signal Clk_div1 is higher, Ke Yizeng
The efficiency of strong rising edge detection, although the clutter of jump cannot be filtered off, the first pwm signal Encoder1, which has been subjected to disappear, to be trembled
Processing, therefore clutter influences less.
The data output end of the pulsewidth counter connects the data input pin of the intermediate value averaging module, the pulsewidth meter
The signal of the pulse number of number device output is connected to the intermediate value averaging module；It include one inside the intermediate value averaging module
A counting sample register, the pulse number for the output of pulsewidth counter described in real-time storage；The intermediate value is averaged mould
Block connects the pulsewidth counter, and the intermediate value averaging module controls the pulse number and the counting sample register stores
The pulse number of the second preset quantity carry out size comparison, and be ranked up according to comparison result, its intermediate value then selected to represent
The impulse speed signal speed；Wherein, the pulse number of second preset quantity is first pwm signal
In Encoder1, in the pulse period for second preset quantity crossed by sample detecting when the corresponding described first frequency dividing
The pulse number of clock signal Clk_div1.The intermediate value averaging module under the present embodiment is conducive to eliminate signal noise to described
The influence of pulse number avoids the pulsewidth of the first pwm signal Encoder1 measured from excessive or too small phenomenon occur, from
And it is the stable speed signal of external motor system acquisition.
A kind of chip, the chip interior integrate aforementioned processing circuit, and the processing circuit includes the PWM sample detecting mould
Block and the PWM generation module；The pwm signal PWM_IN to be processed of the PWM sample detecting module capture chip exterior input,
The high frequency clock signal CLK_US of the system clock generator output of chip interior is received, and to chip exterior output based on wait locate
Manage the impulse speed signal speed of pwm signal.The PWM generation module is used to receive the system clock generator of chip interior
The sampling clock Clk of output, and the controllable PWM output signal PWM_OUT of the duty ratio based on sampling clock Clk is exported, it is described
PWM sample detecting module and the PWM generation module are commonly connected to the sampling clock Clk.Compared with the existing technology, the core
Piece is internally integrated aforementioned speed detector, and the chip is used to provide impulse sampling speed for external electric system.Relative to
The prior art, the chip interior integrate aforementioned PWM generative circuit, and output duty cycle is controllable under the premise of less software resource
Pwm signal.
Device embodiments described above are only schematical, wherein the unit as illustrated by the separation member
It may or may not be physically separated, component shown as a unit may or may not be physics list
Member, it can it is in one place, or may be distributed over multiple network units.It can be selected according to the actual needs
In some or all of the modules realize the purpose of present embodiment scheme.Those of ordinary skill in the art are not paying creation
Property labour in the case where, it can understand and implement.
Claims (11)
1. a kind of PWM generative circuit, which is applied to the revolving speed of the electric system outside control, which is characterized in that
PWM generative circuit includes second clock pre-divider and pwm signal generator, and the frequency division output terminal of second clock pre-divider connects
The data input pin for connecing pwm signal generator is connected；Pwm signal generator includes output frequency divider and comparator, comparator
A comparison input terminal and the output terminal of clock of output frequency divider connect, another comparison input terminal of comparator and with reference to permanent
Potential source connection, data input pin of the input terminal of output frequency divider as the pwm signal generator, the signal output of comparator
Hold the comparison result output end as PWM generative circuit.
2. PWM generative circuit according to claim 1, which is characterized in that the frequency division coefficient of the second clock pre-divider
It is configurable.
3. a kind of processing circuit of pwm signal, which is applied to the electric system outside adjusting, which is characterized in that place
Managing circuit includes PWM sample detecting module and PWM generation module；The input end of clock and PWM of PWM sample detecting module generate
The input end of clock of module is connected；
Pwm signal sample detecting module includes filter, step-length counting submodule, signal pre-divider, speed detector and
One clock pre-divider, wherein pwm signal input terminal of the signal input part of filter as pwm signal sample detecting module；
The connection relationship of pwm signal sample detecting inside modules is: the signal output end of filter simultaneously with step-length counting submodule
Data input pin is connected with the input end of clock of signal pre-divider, the output terminal of clock and speed detector of signal pre-divider
Data input pin be connected；The input end of clock of speed detector is connected with the output terminal of clock of the first clock pre-divider
It connects, output end of the speed signal output end of speed detector as pwm signal sample detecting module；
PWM generation module includes any one of claim 1 to 2 PWM generative circuit, wherein the ratio of the PWM generative circuit
Comparison result output end compared with result output end as PWM generation module.
4. processing circuit according to claim 3, which is characterized in that the filter includes the D triggering of the first preset quantity
Device and a comparison output module, the displacement that the d type flip flop of the first preset quantity constitutes a first preset quantity bit are posted
Storage, the clock end of the d type flip flop of the first preset quantity are connected to the input end of clock of the filter, the first preset quantity
The output end Q of d type flip flop is connected respectively to the data input pin for comparing the first preset quantity of output module, shift register
Signal input part of the data input pin as filter, the data output end for comparing output module are exported as the signal of filter
End.
5. processing circuit according to claim 4, which is characterized in that in the shift register, in addition to the D touching of rightmost
Hair device except each d type flip flop output terminate on the right of a d type flip flop input terminal, the d type flip flop of rightmost it is defeated
Outlet accesses a data input pin of the relatively output module, and the input terminal of leftmost d type flip flop is as shift LD
The data input pin of device.
6. processing circuit according to claim 4, which is characterized in that in the shift register, in addition to leftmost D is touched
The output of each d type flip flop except hair device terminates to the input terminal of one d type flip flop in the left side, leftmost d type flip flop it is defeated
Outlet accesses a data input pin of the relatively output module, and the input terminal of the d type flip flop of rightmost is as shift LD
The data input pin of device.
7. processing circuit according to claim 4, which is characterized in that first preset quantity is set as 6, so that the filter
Wave device is all filtered the level shake in the pwm signal PWM_IN to be processed of input less than 5 clock cycle as burr,
In, the clock cycle is the pulse period of the jitter levels of the pwm signal PWM_IN to be processed.
8. processing circuit according to claim 3, which is characterized in that include that step-length counts inside the step-length counting submodule
The output end of device and direction register, direction register is connect with the enable end of step-length counter, and the counting of step-length counter is defeated
The counting input end of output end of the outlet as the step-length counting submodule, step-length counter counts submodule as the step-length
The data input pin of block.
9. processing circuit according to claim 3, which is characterized in that the speed detector include rising edge detection circuit,
Pulsewidth counter and intermediate value averaging module；
Rising edge detection circuit includes a d type flip flop and one and door, and one of the input terminal D connection of d type flip flop and door is defeated
Enter end, the reversed-phase output of d type flip flopAnother input terminal of connection and door；The clock end and d type flip flop of pulsewidth counter
Clock end be connected, rising edge detection circuit with the output end of door with the reset terminal reset of pulsewidth counter by connecting, arteries and veins
The data input pin of the data output end connection intermediate value averaging module of wide counter, described in the output end of intermediate value averaging module is used as
The input terminal of the speed signal output end of speed detector, rising edge detection circuit is inputted as the data of the speed detector
End.
10. processing circuit according to claim 9, which is characterized in that the bit wide numerical value power of the 2 pulsewidth counter is big
In the ratio of the signal frequency of the input terminal D of the signal frequency and d type flip flop of the input end of clock of the pulsewidth counter.
11. a kind of chip, which is characterized in that the chip interior includes any one of claim 3 to 10 processing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822060361.1U CN209170328U (en) | 2018-12-10 | 2018-12-10 | PWM generative circuit, processing circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822060361.1U CN209170328U (en) | 2018-12-10 | 2018-12-10 | PWM generative circuit, processing circuit and chip |
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| Publication Number | Publication Date |
|---|---|
| CN209170328U true CN209170328U (en) | 2019-07-26 |
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ID=67342922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822060361.1U Withdrawn - After Issue CN209170328U (en) | 2018-12-10 | 2018-12-10 | PWM generative circuit, processing circuit and chip |
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| Country | Link |
|---|---|
| CN (1) | CN209170328U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109361381A (en) * | 2018-12-10 | 2019-02-19 | 珠海市微半导体有限公司 | A kind of PWM generative circuit, processing circuit and chip |
| CN109361381B (en) * | 2018-12-10 | 2024-05-03 | 珠海一微半导体股份有限公司 | PWM generating circuit, processing circuit and chip |
-
2018
- 2018-12-10 CN CN201822060361.1U patent/CN209170328U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109361381A (en) * | 2018-12-10 | 2019-02-19 | 珠海市微半导体有限公司 | A kind of PWM generative circuit, processing circuit and chip |
| CN109361381B (en) * | 2018-12-10 | 2024-05-03 | 珠海一微半导体股份有限公司 | PWM generating circuit, processing circuit and chip |
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