CN2596675Y - Full digital phase-locked loop - Google Patents
Full digital phase-locked loop Download PDFInfo
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- CN2596675Y CN2596675Y CN 02283590 CN02283590U CN2596675Y CN 2596675 Y CN2596675 Y CN 2596675Y CN 02283590 CN02283590 CN 02283590 CN 02283590 U CN02283590 U CN 02283590U CN 2596675 Y CN2596675 Y CN 2596675Y
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Abstract
The utility model relates to a full digital phase-locked loop device, which comprises a frequency and phase detector, a rising or dropping counter, an adding or dropping detector and a frequency divider. A charge pump circuit with a fast-sampling function and two same hysteresis window circuits with firm output clocks are also connected between the frequency and phase detector and the rising or dropping counter. Thus, the frequency difference between an input signal and an output signal of the frequency divider is zero, and phase difference is no longer changed following the change of the time. Voltage is a fixed, and the stabilization of the performance and the system can be ensured.
Description
Technical field
The utility model relates to a kind of phase-locked loop apparatus, specifically, relates to a kind of all-digital phase-locked loop that is used for data communication, microprocessor, disc driver and household appliance technical field.
Background technology
When design data communication, microprocessor, disc driver and household electrical appliance integrated circuit (IC) system, need clock and data recovery in the data flow that a device receives system to come out and make the work between the system synchronous, phase-locked loop just plays this effect.Phase-locked loop circuit generally is made up of three basic elements of character, phase frequency detector, low pass filter and voltage controlled oscillator.Phase difference between phase-locked loop comparator input signal and the voltage controlled oscillator output signal, thus the frequency that error control voltage is adjusted voltage controlled oscillator produced, to reach and input signal frequency together.When loop is started working, if frequency input signal is different with pressuring controlling oscillator frequency, then owing to have intrinsic difference on the frequency between two signals, the phase difference between them certainly will change always, and the error voltage of phase discriminator output as a result just changes within the specific limits.Under the control of this error voltage, the frequency of voltage controlled oscillator is also changing.If the frequency of voltage controlled oscillator can change to frequency input signal and equate, just on this frequency, settle out satisfying under the stability condition.Reach stable after, the phase difference between input signal and the voltage controlled oscillator output signal is zero, differs no longer in time to change, error voltage is a fixed value, at this moment loop just enters " locking " state.The disclosed digital PLL circuit of prior art, its low pass filter and voltage controlled oscillator all are analog circuits, have shortcomings such as charge shift, components and parts are easily aging, parameter instability, low pass filter and the voltage controlled oscillator realized with digital circuit also exist the problem that locking time is long, noise is big.
Summary of the invention
The utility model technical issues that need to address provide a kind of all-digital phase-locked loop device, it compared with prior art, in the time of making phase-locked loop be in work, making the phase difference between input signal and the voltage controlled oscillator output signal apace is zero, differ no longer in time and change, voltage is a fixed value, and noise is lower simultaneously.
For achieving the above object, phase-locked loop of the present invention comprises a phase frequency detector, rising/decline counter, one and increases/subtract detector, a frequency divider, they are electrically connected successively, it is characterized in that, between phase frequency detector and rising/decline counter, also connect a charge pump circuit and 2 identical retarding window circuit in the described all-digital phase-locked loop device with stable output clock with quick sampling.The high level signal input of charge pump circuit and the high level signal output of phase frequency detector are electrically connected, and the high level signal input port of the high level signal output of charge pump circuit and retarding window circuit, rising/decline counter is electrically connected successively.The low level signal input of charge pump circuit and the low level signal output of phase frequency detector are electrically connected, and the low level signal input port of the low level signal output of charge pump circuit and retarding window circuit, rising/decline counter is electrically connected successively.The high frequency clock output port of frequency divider is electrically connected with the counter signals input port and the two-way selector low level input port of charge pump circuit respectively.Charge pump circuit is by the two-way selector of the logical block of handling high flat signal, the logical block of handling low flat signal, the high flat signal of processing, handle the two-way selector of low flat signal, having the two-way selector sum counter that reduces sampling noiset forms, an input handling the logical block of high flat signal links to each other with the high level input of the two-way selector of handling high flat signal, forms high flat input port.An input handling the logical block of low flat signal links to each other with the high level input of the two-way selector of handling low flat signal, forms low flat input port.Handle the logical block of high flat signal, two input ports in addition of handling the logical block of low flat signal link to each other with the output port with the two-way selector that reduces sampling noiset.Handle the logical block of high flat signal, the output port of handling the logical block of low flat signal links to each other with the two-way selector of handling high flat signal and the low level input port of handling the two-way selector of low flat signal respectively.High level port ground connection with the two-way selector that reduces sampling noiset, low level end interruption-forming low level input port.Output with the counter that reduces sampling noiset selects the input port of circuit to link to each other with all two-way.Input with the counter that reduces sampling noiset forms the counter signals input port.Handle the two-way selector of high flat signal and the output port of the two-way selector of handling low flat signal and form high level and low level output port respectively.
In this all-digital phase-locked loop device, the system lock time drops to 7.5 microseconds from 13 microseconds.
Phase-locked loop of the present invention can demonstrate very big superiority during as data communication, microprocessor, disc driver and household appliance technical field integrated circuit (IC) design.High frequency sampling circuit is the output impulse sampling to the frequency discrimination phase discriminator in starting stage that phase-locked loop starts, make pulse counter could export a pulse and become only 1-2 pulse of need from 4 pulses of original needs, pulse counter is just exported a pulse, and the time that system reaches lock-out state shortens.
Description of drawings
Fig. 1 represents the phase-locked loop operation schematic diagram of prior art.
Fig. 2 represents phase-locked loop operation schematic diagram of the present invention.
Fig. 3 is the circuit structure and the waveform of general phase frequency detector.
102 and 101 pulses when Fig. 4 does not have high frequency sampling.
102 and 101 pulses when Fig. 5 has high frequency sampling.
The Down of PFD output pulse when Fig. 6 does not have high frequency sampling.
Before the high frequency sampling of Fig. 7 and the Down pulse after the sampling.
Fig. 8 represents retarding window circuit working schematic diagram of the present invention.
Fig. 9 Up/Down counter circuit source road figure.
Embodiment
Fig. 1 is the phase-locked loop operation schematic diagram of prior art.
With reference to Fig. 2, a kind of all-digital phase-locked loop, contain a phase frequency detector (2), a rising/decline counter (5), one and increase/subtract detector (6), a frequency divider (7), they are electrically connected successively, it is characterized in that, between phase frequency detector (2) and rising/decline counter (5), also connect a charge pump circuit (3) and 2 identical retarding window circuit (15) (16) in the described all-digital phase-locked loop device with stable output clock with quick sampling;
The high level signal output of the high level signal input of described charge pump circuit (3) and phase frequency detector (2) is electrically connected, and the high level signal input port of the high level signal output of charge pump circuit (3) and retarding window circuit (15), rising/decline counter (5) is electrically connected successively;
The low level signal output of the low level signal input of described charge pump circuit (3) and phase frequency detector (2) is electrically connected, and the low level signal input port of the low level signal output of charge pump circuit (3) and retarding window circuit (16), rising/decline counter (5) is electrically connected successively;
The high frequency clock output port of described frequency divider (7) is electrically connected with the counter signals input port and the two-way selector low level input port of charge pump circuit (3) respectively.
Fig. 3 is the circuit structure and the waveform of general phase frequency detector.
Referring to Fig. 8, the transistor in the retarding window circuit (21), the base stage of transistor (22), transistor (24), transistor (26) is electrically connected, and is the input of signal; The emitter electricity of the emitter of the collector electrode of transistor (21) and transistor (22), transistor (23) is electrically connected; The emitter of the emitter of the collector electrode of transistor (26) and transistor (24), transistor (25) is electrically connected; The base stage of the base stage of the collector electrode of the collector electrode of transistor (22) and transistor (24), transistor (23), transistor (25), the positive pole of diode are electrically connected; The collector electrode of the emitter of transistor (21) and transistor (25) is additional power source respectively; The emitter of the collector electrode of transistor (23) and transistor (26) is ground connection respectively; The negative pole of crystal diode is a signal output part.
In the starting stage of starting working, the phase difference between input signal 101 and the output signal 102 is bigger, and the high level pulse of output (UP) 118 compares broad with low level pulse (DOWN) 119.The output signal 116 of unison counter (COUNTER_1) 9 is low levels, by three two-way selectors (MUX) 10,11,12 low level mode input output, a frequency division output signal 107 of frequency dividing circuit 7 is through relative higher signal of frequency of two-way selector (MUX) 10 outputs.This high-frequency signal and broad pulse (UP) 118, (DOWN) 119 carry out and (AND) computing output signal 105,106 respectively by arithmetic logic unit 13,14.Signal 105 and 106 is respectively the low level input of two-way selector (MUX) 11,12, and when output signal 116 was low level, signal 105 and 106 is output signal 108 and 109 respectively.Through this process, wide pulse signal originally (UP) 118, (DOWN) 119 have become a plurality of narrow pulse signals 108 and 109. Signal 110 and 111 is respectively the signal behind the 108 and 109 process retarding window circuit (HYP) 15,16.
Rising/decline (UP/DOWN) counter 5 is counted the pulse number of signal 110 and 111 respectively, and when receiving signal 110, (UP) counter that rises just adds " 1 ", and (DOWN) counter that descends simultaneously subtracts " 1 ".Otherwise pulse when receiving signal 111, (DOWN) counter that descends adds " 1 ", and (UP) counter that rises subtracts " 1 ".Every meter full 2 or 4 pulses, rising/decline (UP/DOWN) counter 5 is just exported one and is brought position/borrow pulse (CARRY/BORROW) into.When rising/decline (UP/DOWN) counter 5 subtracts " 1 " and arrives " 0 " state, just be locked in " 0 " state, and output pulse signal no longer.Position/borrow pulse (CARRY/BORROW) is brought in one of every output into, increases/subtracts detector (INC/DEC Detector) and just increase or reduce a clock pulse (CLOCK) 114 in signal 115 frequencies.So, the frequency of having adjusted signal 115 just has been equivalent to adjust the frequency of signal 102.Wherein, rising/decline (UP/DOWN) counter is one two pulse counter, sees shown in Figure 9.
After after a while, the number of time by Counter 1 count pulse decides, signal 118, the width of 119 pulses is very little, the output of counter (COUNTER_1) 9 is locked as high level, high level input output by three two-way selectors (MUX), it is signal 103,104 output to signal 108,109 respectively, not to signal 118,119 carry out high frequency sampling, the input of shutdown signal 107 simultaneously, arithmetic logic unit 13,14 all is " 0 " through the signal of exporting with (AND) computing 105 and 106.108 and 109 signals process retarding window circuit (HYP) 15,16, output signal 110,111 respectively.
When circuit entered lock-out state, the pulse of signal 118,119 was very narrow, and very narrow signal 103/104 changes to signal 108/109, behind retarding window circuit (HYP) 15,16, had not just had pulse output, and 110 or 111 is exactly low level signal.Circuit enters lock-out state, 115 signals is not adjusted.
Because the state that has had high frequency sampling circuit, circuit to enter locking has just been accelerated greatly.As the comparison that instance graph 4, Fig. 5, Fig. 6, a Fig. 7 are the results, rising/decline (UP/DOWN) counter 5 is binary counters, counter (COUNTR_1) the 7th, the time in 4 cycles of count signal 115.
Claims (4)
1. all-digital phase-locked loop, it is characterized in that containing a phase frequency detector (2), a rising/decline counter (5), one and increase/subtract detector (6), a frequency divider (7), they are electrically connected successively, it is characterized in that, between phase frequency detector (2) and rising/decline counter (5), also connect a charge pump circuit (3) and 2 identical retarding window circuit (15) (16) in the described all-digital phase-locked loop device with stable output clock with quick sampling;
The high level signal output of the high level signal input of described charge pump circuit (3) and phase frequency detector (2) is electrically connected, and the high level signal input port of the high level signal output of charge pump circuit (3) and retarding window circuit (15), rising/decline counter (5) is electrically connected successively;
The low level signal output of the low level signal input of described charge pump circuit (3) and phase frequency detector (2) is electrically connected, and the low level signal input port of the low level signal output of charge pump circuit (3) and retarding window circuit (16), rising/decline counter (5) is electrically connected successively;
The high frequency clock output port of described frequency divider (7) is electrically connected with the counter signals input port and the two-way selector low level input port of charge pump circuit (3) respectively.
2. all-digital phase-locked loop according to claim 1, it is characterized in that the two-way selector (11) of wherein said charge pump circuit by the logical block (13) of handling high flat signal, the logical block (14) of handling low flat signal, the high flat signal of processing, handle the two-way selector (12) of low flat signal, having two-way selector (10) sum counter (9) that reduces sampling noiset forms, an input handling the logical block (13) of high flat signal links to each other with the high level input of the two-way selector (11) of handling high flat signal, forms high flat input port;
An input handling the logical block (14) of low flat signal links to each other with the high level input of the two-way selector (12) of handling low flat signal, forms low flat input port;
Handle the logical block (13) of high flat signal, two input ports in addition of handling the logical block (14) of low flat signal link to each other with the output port of the two-way selector (10) with reduction sampling noiset;
Handle the logical block (13) of high flat signal, the output port of handling the logical block (14) of low flat signal links to each other with the two-way selector (11) of handling high flat signal and the low level input port of handling the two-way selector (12) that hangs down flat signal respectively;
High level port ground connection with the two-way selector (10) that reduces sampling noiset, low level end interruption-forming low level input port;
Output and two-way with the counter (9) that reduces sampling noiset are selected circuit (10), and (11), the input port of (12) links to each other;
Input with the counter (9) that reduces sampling noiset forms the counter signals input port;
The output port of handling the two-way selector (11) of high flat signal and handling the two-way selector (12) of low flat signal forms high level and low level output port respectively.
3. all-digital phase-locked loop according to claim 1 is characterized in that the transistor (21) in the retarding window circuit (15), and the base stage of transistor (22), transistor (24), transistor (26) is electrically connected, and is the input of signal; The emitter electricity of the emitter of the collector electrode of transistor (21) and transistor (22), transistor (23) is electrically connected; The emitter of the emitter of the collector electrode of transistor (26) and transistor (24), transistor (25) is electrically connected; The positive pole of the base stage of the base stage of the collector electrode of the collector electrode of transistor (22) and transistor (24), transistor (23), transistor (25), diode (27) is electrically connected; The collector electrode of the emitter of transistor (21) and transistor (25) is additional power source respectively; The emitter of the collector electrode of transistor (23) and transistor (26) is ground connection respectively; The negative pole of crystal diode (27) is a signal output part.
4. all-digital phase-locked loop according to claim 1 is characterized in that the system lock time drops to 7.5 microseconds from 13 microseconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02283590 CN2596675Y (en) | 2002-12-25 | 2002-12-25 | Full digital phase-locked loop |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02283590 CN2596675Y (en) | 2002-12-25 | 2002-12-25 | Full digital phase-locked loop |
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| CN2596675Y true CN2596675Y (en) | 2003-12-31 |
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| CN 02283590 Expired - Lifetime CN2596675Y (en) | 2002-12-25 | 2002-12-25 | Full digital phase-locked loop |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100376081C (en) * | 2005-09-15 | 2008-03-19 | 威盛电子股份有限公司 | Delayed locking loop capable of sharing counter and related method |
| US7471131B2 (en) | 2005-08-31 | 2008-12-30 | Via Technologies, Inc. | Delay locked loop with common counter and method thereof |
| CN101050940B (en) * | 2007-05-23 | 2010-05-26 | 中国科学院光电技术研究所 | High-precision dual-frequency laser interferometer signal subdivision system |
| CN101656536B (en) * | 2008-08-18 | 2012-06-20 | 中芯国际集成电路制造(上海)有限公司 | Phase-locked loop, and locking detection device and method thereof |
| CN101414821B (en) * | 2007-10-16 | 2012-07-04 | 联发科技股份有限公司 | Error protection method |
| CN103155415A (en) * | 2011-06-15 | 2013-06-12 | 旭化成微电子株式会社 | Cancellation system for phase jumps at loop gain changes in fractional-n frequency synthesizers |
-
2002
- 2002-12-25 CN CN 02283590 patent/CN2596675Y/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7471131B2 (en) | 2005-08-31 | 2008-12-30 | Via Technologies, Inc. | Delay locked loop with common counter and method thereof |
| CN100376081C (en) * | 2005-09-15 | 2008-03-19 | 威盛电子股份有限公司 | Delayed locking loop capable of sharing counter and related method |
| CN101050940B (en) * | 2007-05-23 | 2010-05-26 | 中国科学院光电技术研究所 | High-precision dual-frequency laser interferometer signal subdivision system |
| CN101414821B (en) * | 2007-10-16 | 2012-07-04 | 联发科技股份有限公司 | Error protection method |
| CN101414822B (en) * | 2007-10-16 | 2012-09-05 | 联发科技股份有限公司 | All-digital phase-locked loop, loop bandwidth calibration method, and loop gain calibration method for the same |
| CN101656536B (en) * | 2008-08-18 | 2012-06-20 | 中芯国际集成电路制造(上海)有限公司 | Phase-locked loop, and locking detection device and method thereof |
| CN103155415A (en) * | 2011-06-15 | 2013-06-12 | 旭化成微电子株式会社 | Cancellation system for phase jumps at loop gain changes in fractional-n frequency synthesizers |
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Expiration termination date: 20121225 Granted publication date: 20031231 |