CN103633996A - Frequency division method for accumulating counter capable of generating optional-frequency square wave - Google Patents
Frequency division method for accumulating counter capable of generating optional-frequency square wave Download PDFInfo
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- CN103633996A CN103633996A CN201310672103.8A CN201310672103A CN103633996A CN 103633996 A CN103633996 A CN 103633996A CN 201310672103 A CN201310672103 A CN 201310672103A CN 103633996 A CN103633996 A CN 103633996A
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Abstract
The invention discloses a frequency division method for an accumulating counter capable of generating optional-frequency square wave and aims to solve the technical problem that output precision in the existing frequency division method for the accumulating counter is low. According to the technical scheme, the existing frequency division method for the accumulating counter is modified, count values which remain every time the counter outputs a pulse are added to the counting process of next pulse, pulse width generated in the mode fluctuates in one clock period, and the frequency of the generated pulse is statistically equal to a demanded value. The frequency division method for the accumulating counter capable of generating optional-frequency square wave is widely applicable to various frequency division digital systems, and the digital systems can output pulses more precisely.
Description
Technical field
The present invention relates to a kind of summary counter dividing method, particularly a kind of summary counter dividing method that produces optional frequency square wave.
Background technology
In digital logic system design, clock can be described as the blood of system.In sequential logical circuit, nearly all signal all needs clock to front transfer.Frequency division method is a kind of basic skills, is commonly used to certain given frequency to carry out frequency division, with the frequency that obtains needing.
In the Electric Machine Control based on FPGA, the pulse of output is to have the pulse frequency value corresponding with the motor speed of service, and the frequency values of the pulse of exporting by real-time adjusting FPGA, just can realize the speed regulating control to motor.Realize the accurate control to motor speed and position, the frequency of output pulse is very important, and accurately pulse frequency and pulse duration just can be so that motor move very reposefully.By consulting related data, the operation principle of various frequency division methods, feature are analyzed to summary, output frequency precision for existing frequency division method is lower, by existing summary counter frequency division method is passed through to transformation, the pulse frequency of exporting of take is accumulating values, by adding up of limited number of time, when summation and the clock number of cumulative number compares, the difference next counting process that is added to, can realize repeatedly like this average of frequency and need the frequency values of output to equate, can realize like this pulse frequency accurately output in statistical significance.
Summary of the invention
In order to overcome the low deficiency of existing summary counter dividing method output accuracy.The invention provides a kind of summary counter dividing method that produces optional frequency square wave.The method is by improving existing summary counter frequency division method, counter remaining count value after pulse of every output is added in the counting process of next pulse, this mode produces the fluctuation range of pulse duration within a clock cycle, can in statistical significance, reach equal with required value so that produce the frequency of pulse.This method can be widely used in various frequency division digital systems, can improve the precision of digital system output pulse.
The technical solution adopted for the present invention to solve the technical problems is: a kind of summary counter dividing method that produces optional frequency square wave, is characterized in comprising the following steps:
Step 1, according to formula
the setting of the mould value of counter is equated with the input of input clock, and the step-length of summary counter just equates with the frequency values of output in number like this.In formula, clk_in is the clock frequency of input, and clk_out is the pulse frequency that needs output, and N is the mould value of summary counter, and STEP is the step-length of summary counter.
Step 2, rising edge clock of every input, just add STEP to the value of counter, like this meter
when inferior, export pulse and carry out once inside out,
when value is not integer, unnecessary number was added in the count cycle next time, the pulse producing is like this that adjacent two frequency dividing ratio pulse interlacings produce, by count difference value is added to next time, and automatic switchover frequency dividing ratio.
Step 3, according to the method row that calculate, write out the expression formula that realizes frequency division, according to expression formula row written-out program.
On the ISE platform of company of step 4 ,Sai SEL, utilize Verilog language compilation program.
Step 5, the program of finishing is downloaded in objective chip.
The invention has the beneficial effects as follows: the method is by improving existing summary counter frequency division method, counter remaining count value after pulse of every output is added in the counting process of next pulse, this mode produces the fluctuation range of pulse duration within a clock cycle, can in statistical significance, reach equal with required value so that produce the frequency of pulse.This method can be widely used in various frequency division digital systems, has improved the precision of digital system output pulse.
Below in conjunction with the drawings and specific embodiments, the present invention is elaborated.
Accompanying drawing explanation
Fig. 1 is the flow chart that the present invention produces the summary counter dividing method of optional frequency square wave.
Embodiment
With reference to Fig. 1.The summary counter dividing method concrete steps that the present invention produces optional frequency square wave are as follows:
The method that the present invention adopts is that summary counter method is transformed, and the surplus value of at every turn counting is added in counting next time, thereby realize, in statistical significance, can export frequency values accurately; Equal by the total value of counter being arranged to clock number, totalizing step just equates with output pulse frequency value, thereby need not calculate the totalizing step of summary counter; Make the pulse frequency of output not be subject to the impact of output clock, take less resource.
The formula that this method adopts is:
wherein clk_in is the clock frequency of input, and clk_out is the pulse frequency that needs output, and N is the mould value of summary counter, and STEP is the step-length of summary counter.Here the mould value setting of counter and the input of input clock are equated, the step-length of summary counter just equates with the frequency values of output in number like this, so just without count step-length.
Summary counter to realize principle as follows: often carry out the rising edge of a clock, add STEP just to the value of counter, like this meter
when inferior, output clock carries out once inside out,
when value is not integer, unnecessary number was added in the count cycle next time, the pulse producing is like this that adjacent two frequency dividing ratio pulse interlacings produce, and by count difference value is added to next time, frequency dividing ratio just can automatically switch.
Utilize this improvement summary counter frequency division method, can improve the precision of the pulse frequency of output, and in the process of output pulse, need not calculate the step-length of summary counter, by the mould value of counter is made into input clock numerical value on identical value, the totalizing step of summary counter is exactly the numerical value that output frequency is corresponding.
Concrete steps are as follows:
According to formula:
(wherein clk_in is the clock frequency of input, and clk_out is the pulse frequency that needs output, and N is the mould value of summary counter, and STEP is the step-length of summary counter).Here the mould value setting of counter and the input of input clock are equated, the step-length of summary counter just equates with the frequency values of output in number like this, so just without count step-length.
Summary counter to realize principle as follows: rising edge clock of every input, add STEP just to the value of counter, like this meter
when inferior, export pulse and carry out once inside out,
when value is not integer, unnecessary number was added in the count cycle next time, the pulse producing is like this that adjacent two frequency dividing ratio pulse interlacings produce, and by count difference value is added to next time, frequency dividing ratio just can automatically switch.
According to the method row that calculate, write out the expression formula that realizes frequency division, according to expression formula row written-out program flow chart.
On the ISE platform of company of Sai SEL, utilize Verilog language compilation to realize the program of the method.
To finish ground program and download in objective chip, and utilize oscilloscope to can be observed satisfactory pulse.
Claims (1)
1. a summary counter dividing method that produces optional frequency square wave, is characterized in that comprising the following steps:
Step 1, according to formula
the setting of the mould value of counter is equated with the input of input clock, and the step-length of summary counter just equates with the frequency values of output in number like this; In formula, clk_in is the clock frequency of input, and clk_out is the pulse frequency that needs output, and N is the mould value of summary counter, and STEP is the step-length of summary counter;
Step 2, rising edge clock of every input, just add STEP to the value of counter, like this meter
when inferior, export pulse and carry out once inside out,
when value is not integer, unnecessary number was added in the count cycle next time, the pulse producing is like this that adjacent two frequency dividing ratio pulse interlacings produce, by count difference value is added to next time, and automatic switchover frequency dividing ratio;
Step 3, according to the method row that calculate, write out the expression formula that realizes frequency division, according to expression formula row written-out program;
On the ISE platform of company of step 4 ,Sai SEL, utilize Verilog language compilation program;
Step 5, the program of finishing is downloaded in objective chip.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105223872A (en) * | 2015-10-19 | 2016-01-06 | 宁波卓奥电子科技有限公司 | A kind of electric terminal control panel square-wave generator |
| CN109765583A (en) * | 2019-03-04 | 2019-05-17 | 华通信安(北京)科技发展有限公司 | A kind of clock synchronizing method based on GNSS receiver pulse per second (PPS) |
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| CN101176673A (en) * | 2007-11-30 | 2008-05-14 | 深圳市蓝韵实业有限公司 | Device for testing the compatibility of front end amplification channel of ultrasonic diagnostic device |
| US20110194702A1 (en) * | 2009-10-15 | 2011-08-11 | Huawei Technologies Co., Ltd. | Method and Apparatus for Detecting Audio Signals |
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Patent Citations (2)
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| CN101176673A (en) * | 2007-11-30 | 2008-05-14 | 深圳市蓝韵实业有限公司 | Device for testing the compatibility of front end amplification channel of ultrasonic diagnostic device |
| US20110194702A1 (en) * | 2009-10-15 | 2011-08-11 | Huawei Technologies Co., Ltd. | Method and Apparatus for Detecting Audio Signals |
Non-Patent Citations (1)
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| 王耀琦: "基于CPLD/FPGA的任意分频器设计研究与仿真", 《兰州交通大学学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105223872A (en) * | 2015-10-19 | 2016-01-06 | 宁波卓奥电子科技有限公司 | A kind of electric terminal control panel square-wave generator |
| CN105223872B (en) * | 2015-10-19 | 2017-12-08 | 浙江卓奥科技股份有限公司 | A kind of electric terminal control panel square-wave generator |
| CN109765583A (en) * | 2019-03-04 | 2019-05-17 | 华通信安(北京)科技发展有限公司 | A kind of clock synchronizing method based on GNSS receiver pulse per second (PPS) |
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Application publication date: 20140312 |