CN215871370U

CN215871370U - Trigger device for analog-digital converter

Info

Publication number: CN215871370U
Application number: CN202121018406.4U
Authority: CN
Inventors: 刘扬波; 耿骏; 吕华伟
Original assignee: On Bright Electronics Shanghai Co Ltd
Current assignee: On Bright Electronics Shanghai Co Ltd
Priority date: 2021-05-12
Filing date: 2021-05-12
Publication date: 2022-02-18
Anticipated expiration: 2031-05-12
Also published as: TWM622514U

Abstract

A triggering apparatus for an analog-to-digital converter is provided. In the trigger device: the clock end of the timing counter is connected to the system clock, the zero clearing end is connected to the output end of the second logic AND gate, and the output end is connected to the positive phase input end of the first comparator; the inverting input end of the first comparator is used for receiving a threshold signal set by a user, and the output end of the first comparator is connected to the first input end of the first logic AND gate; the second input end of the first logic AND gate is used for receiving a timing trigger-analog-to-digital conversion enabling signal set by a user, and the output end of the first logic AND gate is used for outputting a timing trigger-analog-to-digital conversion signal to the outside of the trigger device; the input end of the second comparator is used for receiving the pulse width modulation signal from the outside of the trigger device, and the output end of the second comparator is connected to the input end of the edge generator; the output end of the edge generator is connected to the first input end of the second logic AND gate; and the second input end of the second logic AND gate is used for receiving a pulse width modulation-timing synchronization enabling signal set by a user.

Description

Trigger device for analog-digital converter

Technical Field

The present invention relates to the field of circuits, and in particular, to a trigger device for an analog-to-digital converter.

Background

Micro Control Units (MCUs) are widely used in controllers for direct current brushless motors (BLDC) and Permanent Magnet Synchronous Motors (PMSM). The MCU for motor control includes, in addition to a Central Processing Unit (CPU), a Pulse Width Modulation (PWM) controller for controlling switching of the semiconductor switches, an analog-to-digital converter (ADC) for sampling a phase line voltage of the motor, and a timer for timing or generating a timing signal.

Currently, PWM controllers in MCUs for motor control cannot trigger the ADC or can trigger the ADC only a single time. On the one hand, if the PWM controller is unable to trigger the ADC, the CPU is required to trigger the ADC periodically, which increases the burden on the CPU. On the other hand, if the PWM controller can only trigger the ADC a single time, it cannot accommodate the requirements of the new control algorithm.

SUMMERY OF THE UTILITY MODEL

In view of one or more problems with current trigger mechanisms for analog-to-digital converters, the present invention provides a trigger apparatus for an analog-to-digital converter.

The trigger device for the analog-to-digital converter according to the embodiment of the utility model comprises a system clock, a timing counter, an edge generator, a first comparator, a second comparator and a first logic AND gate, wherein: the clock end of the timing counter is connected to the system clock, the zero clearing end is connected to the output end of the second logic AND gate, and the output end is connected to the positive phase input end of the first comparator; the inverting input end of the first comparator is used for receiving a threshold signal set by a user, and the output end of the first comparator is connected to the first input end of the first logic AND gate; the second input end of the first logic AND gate is used for receiving a timing trigger-analog-to-digital conversion enabling signal set by a user, and the output end of the first logic AND gate is used for outputting a timing trigger-analog-to-digital conversion signal which triggers an analog-to-digital converter to perform analog-to-digital conversion to the outside of the trigger device; the input end of the second comparator is used for receiving the pulse width modulation signal from the outside of the trigger device, and the output end of the second comparator is connected to the input end of the edge generator; the output end of the edge generator is connected to the first input end of the second logic AND gate; and the second input end of the second logic AND gate is used for receiving a pulse width modulation-timing synchronization enabling signal set by a user.

According to the triggering device for the analog-to-digital converter, the single triggering of the analog-to-digital converter can be realized based on the pulse width modulation signal. Therefore, an increase in the CPU burden caused by the CPU triggering the ADC can be avoided, and an increase in the circuit complexity of the PWM controller caused by the PWM controller triggering the ADC can be avoided.

The trigger device for the analog-to-digital converter according to the embodiment of the utility model comprises a system clock, a timing counter, an edge generator, a D flip-flop, a logic OR gate, a first comparator, a second comparator and a first logic AND gate, a second logic AND gate and a third logic AND gate, wherein: the clock end of the timing counter is connected to a system clock, the zero clearing end is connected to the output end of the logic OR gate, and the output end is connected to the positive phase input end of the first comparator; the inverting input end of the first comparator is used for receiving a threshold signal set by a user, and the output end of the first comparator is connected to the first input end of the first logic AND gate; the second input end of the first logic AND gate is used for receiving a timing trigger-analog-to-digital conversion enabling signal set by a user, and the output end of the first logic AND gate is used for outputting a timing trigger-analog-to-digital conversion signal which triggers the analog-to-digital converter to perform analog-to-digital conversion to the outside of the trigger device and is connected to the clock end of the D trigger; the input end of the second comparator is used for receiving the pulse width modulation signal from the outside of the trigger device, and the output end of the second comparator is connected to the input end of the edge generator; the output end of the edge generator is connected to the first input end of the second logic AND gate; the second input end of the second logic AND gate is used for receiving a pulse width modulation-timing synchronization enabling signal set by a user, and the output end of the second logic AND gate is connected to the first input end of the logic OR gate; the output end of the D trigger is connected to the first input end of the third logic AND gate; the second input end of the third logic AND gate is used for receiving the continuous trigger enable signal set by the user, and the output end of the third logic AND gate is connected to the second input end of the logic OR gate.

According to the triggering device for the analog-digital converter, continuous triggering of the ADC can be realized based on the pulse width modulation signal, and the requirement of a motor control algorithm on the computing capacity of a CPU (Central processing Unit) can be remarkably reduced when the triggering device is applied to an MCU (microprogrammed control Unit) for motor control.

Drawings

The utility model may be better understood from the following description of specific embodiments thereof taken in conjunction with the accompanying drawings, in which:

fig. 1 shows an example block diagram of a triggering arrangement for an analog-to-digital converter according to an embodiment of the utility model;

FIG. 2 shows an example block diagram of a triggering arrangement for an analog-to-digital converter according to another embodiment of the utility model;

FIG. 3 illustrates a waveform diagram of a plurality of signals associated with the second comparator and edge generator shown in FIG. 2;

FIG. 4 illustrates a waveform diagram of a plurality of signals associated with the system clock, the timing counter, and the first comparator shown in FIG. 2;

FIG. 5 illustrates a waveform diagram of a plurality of signals associated with the second comparator, the timing counter, and the first comparator shown in FIG. 2;

FIG. 6 illustrates a waveform diagram of a plurality of signals associated with the first comparator and D flip-flop shown in FIG. 2;

fig. 7 illustrates a waveform diagram of a plurality of signals related to the timing counter, the first and second comparators, and the D flip-flop illustrated in fig. 2.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is in no way limited to any specific configuration set forth below, but rather covers any modification, substitution, and improvement of elements and components without departing from the spirit of the utility model. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present invention. Note that, the term "a and B are connected" as used herein may mean "a and B are directly connected" or "a and B are indirectly connected via one or more other elements".

Fig. 1 shows an example block diagram of a triggering apparatus 100 for an analog-to-digital converter according to an embodiment of the utility model. As shown in fig. 1, the trigger apparatus 100 for an analog-to-digital converter includes a system clock 102, a timing counter 104, a first comparator 106, a second comparator 108, an edge generator 110, a first logic and gate 112, and a second logic and gate 114, wherein: the timing counter 104 has a clock terminal (i.e., CLK terminal) connected to the system clock 102, a clear terminal (i.e., CLR terminal) connected to the output terminal of the second logic and gate 114, and an output terminal connected to the non-inverting input terminal of the first comparator 106; an inverting input terminal of the first comparator 106 is configured to receive a threshold signal TimerPeriod set by a user, and an output terminal thereof is connected to a first input terminal of the first logical and gate 112; a second input end of the first and gate 112 is configured to receive a timing trigger-analog-to-digital conversion enable Signal TimerTrigADC _ EN set by a user, and an output end of the first and gate is configured to output a timing trigger-analog-to-digital conversion Signal Timer _ Trig _ ADC _ Signal to the outside of the trigger apparatus 100, where the timing trigger-analog-to-digital conversion enable Signal TimerTrigADC _ EN triggers an analog-to-digital converter to perform analog-to-digital conversion; the input terminal of the second comparator 108 is used for receiving the pulse width modulation signal PWMx from the outside of the trigger apparatus 100, and the output terminal is connected to the input terminal of the edge generator 110; the output of the edge generator 110 is connected to a first input of a second logical and gate 114; a second input terminal of the second and logic gate 114 is configured to receive a PWM-Timer-Align-EN enable signal PWM _ Timer _ Align _ EN set by a user.

Here, the pulse width modulation signal PWMx may be one of the PWM signals selected by the signal selector from among 4, 6, or 8 PWM signals generated by the PWM controller. The pulse width modulated signal PWMx can be flexibly configured to accommodate variations in different control algorithms.

The triggering device 100 for the analog-to-digital converter according to the embodiment of the utility model can realize single triggering of the analog-to-digital converter based on the pulse width modulation signal. Therefore, an increase in the CPU burden caused by the CPU triggering the ADC can be avoided, and an increase in the circuit complexity of the PWM controller caused by the PWM controller triggering the ADC can be avoided.

Fig. 2 shows an exemplary block diagram of a triggering device 100' for an analog-to-digital converter according to another embodiment of the present invention. As shown in fig. 2, the trigger apparatus 100' for an analog-to-digital converter includes a D flip-flop 116, a third logical and gate 118, and a logical or gate 120, in addition to a system clock 102, a timing counter 104, a first comparator 106, a second comparator 108, an edge generator 110, a first logical and gate 112, and a second logical and gate 114, wherein: the timing counter 104 has a clock terminal (i.e., CLK terminal) coupled to the system clock 102, a clear terminal coupled to the output terminal of the or gate 120, and an output terminal coupled to the non-inverting input terminal of the first comparator 106; an inverting input terminal of the first comparator 106 is configured to receive a threshold signal TimerPeriod set by a user, and an output terminal thereof is connected to a first input terminal of the first logical and gate 112; a second input end of the first and gate 112 is configured to receive a timing trigger-analog-to-digital conversion enable Signal TimerTrigADC _ EN set by a user, and an output end of the first and gate is configured to output a timing trigger-analog-to-digital conversion Signal Timer _ Trig _ ADC _ Signal for triggering an analog-to-digital converter to perform analog-to-digital conversion to the outside of the trigger apparatus 100' and is connected to a clock end of the D flip-flop 116; the input terminal of the second comparator 108 is used for receiving the pulse width modulation signal PWMx from the outside of the trigger device 100', and the output terminal is connected to the input terminal of the edge generator 110; the output of the edge generator 110 is connected to a first input of a second logical and gate 114; a second input end of the second and logic gate 114 is configured to receive a pulse width modulation-timing synchronization enable signal PWM _ Timer _ Align _ EN set by a user, and an output end thereof is connected to a first input end of the or logic gate 120; the output (i.e., Q terminal) of the D flip-flop 116 is connected to a first input of a third logical and gate 118; a second input terminal of the third logic and gate 118 is configured to receive a Continuous trigger enable signal continuoustrig _ EN set by a user, and an output terminal thereof is connected to a second input terminal of the logic or gate 120.

Similarly, the PWM signal PWMx may be one of the 4, 6, or 8 PWM signals generated by the PWM controller by the signal selector. The pulse width modulated signal PWMx can be flexibly configured to accommodate variations in different control algorithms.

According to the triggering device 100' for the analog-to-digital converter, continuous triggering of the ADC can be realized based on the pulse width modulation signal, and the requirement of a motor control algorithm on the computing capacity of a CPU can be remarkably reduced when the triggering device is applied to an MCU for motor control.

As shown in fig. 1-2, in some embodiments, the system clock 102 may include an oscillator, a divider, and a signal selector, wherein: the output end of the oscillator is connected to the input end of the frequency divider and the first input end of the signal selector; the output end of the frequency divider is connected to the second input end of the signal selector; the output of the signal selector is connected to the clock terminal of the timing counter 104. Specifically, the oscillator generates a first clock signal, the frequency divider divides the first clock signal to generate a second clock signal, and the signal selector selects one clock signal from the first clock signal and the second clock signal to supply to the timing counter 104.

Fig. 3 to 7 show waveform diagrams of a plurality of signals related to the triggering apparatus 100' for an analog-to-digital converter shown in fig. 2. The operation of the triggering device 100' for an analog-to-digital converter will be described with reference to fig. 3 to 7. It should be noted that the operation principle of the same-name functional blocks in the triggering devices 100 and 100' for the analog-to-digital converter is the same, so that the description of the operation principle of the triggering device 100 for the analog-to-digital converter is omitted here.

In the triggering apparatus 100' for an analog-to-digital converter shown in fig. 2, the second comparator 108 determines whether the pulse width modulation signal PWMx is at an Active level, and outputs an Active level indicating signal PWMx _ Active indicating whether the pulse width modulation signal PWMx is at the Active level. In some examples, the pulse width modulated signal PWMx is considered to be an active level when the pulse width modulated signal PWMx is at a high level. In other examples, the pulse width modulated signal PWMx is considered to be active when the pulse width modulated signal PWMx is low. Here, when the Active level indicating signal PWMx _ Active is at a high level, the pulse width modulation signal PWMx is indicated as an Active level; when the Active level indicating signal PWMx _ Active is at a low level, the pwm signal PWMx is indicated as an inactive level.

In the triggering apparatus 100' for an analog-to-digital converter shown in fig. 2, the edge generator 110 generates a rising edge Signal Pos-edge _ Signal when detecting that the Active level indicating Signal PWMx _ Active transits from a low level to a high level; the second logic and gate 114 performs logic and on the PWM-timing synchronization enable Signal PWM _ Timer _ Align _ En and the rising edge Signal Pos-edge _ Signal to obtain the PWM-timing synchronization Signal PWM _ Timer _ Align _ Signal. In practical applications, the output of the rising edge generator 110 may be turned off by setting the PWM-Timer-Align _ En to a low level. Fig. 3 illustrates a waveform diagram of a plurality of signals associated with the second comparator 108 and the edge generator 110 shown in fig. 2.

In the flip-flop device 100' for an analog-to-digital converter shown in fig. 2, the count value of the timing counter 104 is accumulated with the transition of the clock signal CLK from the system clock 102. The first comparator 106 compares the count value Timer _ Counter of the Timer Counter 104 with a threshold Timer _ period set by a user to obtain an overflow Signal, i.e., a Timing Signal Timing _ Signal. The adjustable timing time can be obtained by matching a threshold value set by a user with a certain clock frequency. The first and gate 112 logically and the timing Signal from the first comparator 106 and the timing trigger-analog-to-digital conversion enable Signal TimerTrigADC _ EN to obtain a timing trigger-analog-to-digital conversion Signal Timer _ Trig _ ADC _ Signal for triggering the ADC to perform analog-to-digital conversion. Fig. 4 illustrates a waveform diagram of a plurality of signals related to the system clock, the timing counter, and the first comparator illustrated in fig. 2.

In practical applications, it is required that the start point of the timing counter is synchronized with the rising edge of the pulse width modulation signal PWMx. Therefore, it is necessary to generate the pulse width modulation-timing synchronization Signal PWM _ Timer _ Align _ Signal based on the Active level indication Signal PWMx _ Active. The pulse width modulation-timing synchronization Signal PWM _ Timer _ Align _ Signal clears the counter in the timing counter 104 by 0, and the counter counts again, that is, the rising edge of the Active level indication Signal PWMx _ Active resets the counter, so as to obtain a controllable delay time. Fig. 5 illustrates a waveform diagram of a plurality of signals related to the second comparator, the timing counter, and the first comparator illustrated in fig. 2.

The triggering device 100' for the ADC shown in fig. 2 can also trigger the ADC continuously, and generate a continuous timing trigger _ ADC Signal Timer _ Trig _ ADC _ Signal. Specifically, as shown in fig. 2, the timing trigger _ a/D conversion Signal Timer _ Trig _ ADC _ Signal is returned to the clock terminal of the D flip-flop 116, and the D flip-flop 116 generates another counter reset Signal, which is controlled by the Continuous trigger enable Signal Continuous _ Trig _ EN. The output Signal of the third and logic gate 118 is a Continuous trigger Signal continuoustrig Signal, which resets the counter of the timing counter 104, and restarts timing until the next timing trigger Signal Timer _ Trig _ ADC _ Signal is generated; and repeating the steps to obtain a continuous timing trigger _ analog-to-digital conversion Signal Timer _ Trig _ ADC _ Signal. Fig. 6 illustrates a waveform diagram of a plurality of signals related to the first comparator and the D flip-flop illustrated in fig. 2.

In practical applications, the triggering device 100' for the analog-to-digital converter may be configured to continuously trigger the ADC during an active level interval of the pulse width modulation signal PWMx and not trigger the ADC during an inactive level interval of the pulse width modulation signal PWMx. Therefore, in some embodiments, the triggering device 100' for an analog-to-digital converter may further include an inverter 122 and a fourth logical and gate 124, wherein an input of the inverter 122 is connected to the output of the second comparator 108, an output thereof is connected to a first input of the fourth logical and gate 124, a second input of the fourth logical and gate 124 is configured to receive the disable enable signal Inactive _ EN set by the user, and an output thereof is connected to the clear terminal (CLR terminal) of the D flip-flop 116. The inverter 122 inverts the Active level indication signal PWMx _ Active to obtain a signal PWMx _ Inactive, and the fourth logic and gate 124 logically and-combines the signal PWMx _ Inactive and the disable enable signal Inactive _ En to control the D flip-flop 116 to operate only in the Active level interval of the pwm signal PWMx. Fig. 7 illustrates a waveform diagram of a plurality of signals related to the timing counter, the first and second comparators, and the D flip-flop illustrated in fig. 2.

In summary, the trigger apparatus 100' for the analog-to-digital converter shown in fig. 2 involves a plurality of enable signals. By configuring these enable signals, different functions can be obtained. Table 1 shows a correspondence table of the enable signals and the corresponding functions.

TABLE 1

It should be understood that the triggering device for an analog-to-digital converter according to the embodiment of the present invention can be used not only in motors such as brushless dc motors and permanent magnet synchronous motors, but also in electric power conversion devices such as inverters.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The present embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the utility model being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. A triggering mechanism for an analog-to-digital converter comprising a system clock, a timing counter, an edge generator, first and second comparators, and first and second logical and gates, wherein:

the clock end of the timing counter is connected to the system clock, the zero clearing end of the timing counter is connected to the output end of the second logic AND gate, and the output end of the timing counter is connected to the positive phase input end of the first comparator;

the inverting input end of the first comparator is used for receiving a threshold signal set by a user, and the output end of the first comparator is connected to the first input end of the first logic AND gate;

the second input end of the first logic AND gate is used for receiving a timing trigger-analog-to-digital conversion enabling signal set by a user, and the output end of the first logic AND gate is used for outputting a timing trigger-analog-to-digital conversion signal which triggers an analog-to-digital converter to perform analog-to-digital conversion to the outside of the trigger device;

the input end of the second comparator is used for receiving a pulse width modulation signal from the outside of the trigger device, and the output end of the second comparator is connected to the input end of the edge generator;

the output end of the edge generator is connected to the first input end of the second logic AND gate;

and the second input end of the second logic AND gate is used for receiving a pulse width modulation-timing synchronization enabling signal set by a user.

2. The trigger apparatus of claim 1, wherein the system clock comprises an oscillator, a frequency divider, and a signal selector, wherein:

an output of the oscillator is connected to an input of the frequency divider and a first input of the signal selector;

the output end of the frequency divider is connected to the second input end of the signal selector;

the output end of the signal selector is connected to the clock end of the timing counter.

3. A triggering mechanism for an analog-to-digital converter comprising a system clock, a timing counter, an edge generator, a D flip-flop, a logical or gate, first and second comparators, and first, second, and third logical and gates, wherein:

the clock end of the timing counter is connected to the system clock, the zero clearing end is connected to the output end of the logic OR gate, and the output end is connected to the positive phase input end of the first comparator;

the second input end of the first logic AND gate is used for receiving a timing trigger-analog-to-digital conversion enabling signal set by a user, and the output end of the first logic AND gate is used for outputting a timing trigger-analog-to-digital conversion signal which triggers an analog-to-digital converter to perform analog-to-digital conversion to the outside of the trigger device and is connected to the clock end of the D flip-flop;

the second input end of the second logic AND gate is used for receiving a pulse width modulation-timing synchronization enabling signal set by a user, and the output end of the second logic AND gate is connected to the first input end of the logic OR gate;

the output end of the D flip-flop is connected to the first input end of the third logic AND gate;

and the second input end of the third logic AND gate is used for receiving a continuous trigger enable signal set by a user, and the output end of the third logic AND gate is connected to the second input end of the logic OR gate.

4. The flip-flop device of claim 3, further comprising an inverter and a fourth logical AND gate, wherein:

the input end of the inverter is connected to the output end of the second comparator, and the output end of the inverter is connected to the first input end of the fourth logic AND gate;

and a second input end of the fourth logic AND gate is used for receiving an invalid enable signal set by a user, and an output end of the fourth logic AND gate is connected to a zero clearing end of the D trigger.

5. The trigger apparatus of claim 3, wherein the system clock comprises an oscillator, a frequency divider, and a signal selector, wherein:

6. A micro-control unit for motor control, characterized in that it comprises a triggering device for an analog-to-digital converter according to any one of claims 1 to 5.

7. An electrical machine comprising a triggering device for an analog-to-digital converter according to any one of claims 1 to 5.